CN106449453B - A kind of NATURAL CONVECTION COEFFICIENT OF HEAT of semiconductor package body and the method for detecting of thermal resistance - Google Patents
A kind of NATURAL CONVECTION COEFFICIENT OF HEAT of semiconductor package body and the method for detecting of thermal resistance Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/73265—Layer and wire connectors
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/181—Encapsulation
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Abstract
The invention discloses the method for detecting of a kind of NATURAL CONVECTION COEFFICIENT OF HEAT of semiconductor package body and thermal resistance, comprising: establishes finite element thermal analysis model to the semiconductor package body；One group of initial convection transfer rate is set, and the initial convection transfer rate of each of the initial convection transfer rate of the group is respectively correspondingly loaded onto the corresponding node in the thermal model；Steady-state thermal analysis is carried out, under specific environment temperature to obtain the surface temperature of each node in the thermal model；The convection transfer rate of each node is obtained according to the surface temperature of each node；It is iterated processing according to the convection transfer rate of each node and initial convection transfer rate, to obtain the NATURAL CONVECTION COEFFICIENT OF HEAT of each node；The thermal resistance of the semiconductor package body is obtained according to the NATURAL CONVECTION COEFFICIENT OF HEAT of each node.By way of above-mentioned iteration, the present invention can be improved the accuracy of encapsulating products simulation thermal resistance calculation.
Description
Technical field
The present invention relates to field of semiconductor package, more particularly to a kind of NATURAL CONVECTION COEFFICIENT OF HEAT of semiconductor package body
And the method for detecting of thermal resistance.
Background technique
With the continuous improvement of semiconductor packages integrated level, the unit area power of inside chip is increasing, encapsulation
The operating temperature of product is higher and higher, and therefore, carrying out heat analysis to semiconductor package body is particularly important.Currently, frequently with
Physical model finite element modelling tool carries out heat analysis to semiconductor package body, specially by convection transfer rate with surface load
Form be applied on the physical model of semiconductor package body to analysis obtain thermal resistance.Thermal resistance is to measure substance heat conduction property
An important parameter, and convection transfer rate be influence thermal resistance analysis key parameter.At present frequently with constant value or
Empirical equation obtains convection transfer rate, and the thermal resistance value result obtained according to the convection transfer rate often has with actual value centainly
Gap.
Summary of the invention
The invention mainly solves the technical problem of providing a kind of NATURAL CONVECTION COEFFICIENT OF HEAT of semiconductor package body and heat
The method for detecting of resistance can be improved the accuracy of encapsulating products simulation thermal resistance calculation.
In order to solve the above technical problems, one technical scheme adopted by the invention is that: a kind of semiconductor package body is provided
The method for detecting of NATURAL CONVECTION COEFFICIENT OF HEAT, comprising:
Finite element thermal analysis model is established to the semiconductor package body；
Set one group of initial convection transfer rate, and by the initial convection current of each of the initial convection transfer rate of the group
The coefficient of heat transfer is respectively correspondingly loaded onto the corresponding node in the thermal model；
Steady-state thermal analysis is carried out, under specific environment temperature to obtain each node in the thermal model most
Big temperature value；
The convection transfer rate of each node is obtained according to the surface temperature of each node；
It is iterated processing according to the convection transfer rate of each node and initial convection transfer rate, it is every to obtain
The NATURAL CONVECTION COEFFICIENT OF HEAT of a node.
Wherein, step is iterated processing according to the convection transfer rate and initial convection transfer rate of each node
To obtain the NATURAL CONVECTION COEFFICIENT OF HEAT of each node, further comprise:
Judge difference between the convection transfer rate of each node and its initial convection transfer rate absolute value whether
Less than range of tolerable variance value；
As the absolute value of difference between the convection transfer rate of each node and its initial convection transfer rate is less than institute
Range of tolerable variance value is stated, then the iterative processing terminates and using the convection transfer rate of each node as the naturally right of each node
Flow the coefficient of heat transfer；Otherwise, then using the convection transfer rate of each node as the initial convection transfer rate of each node, and
Steady-state thermal analysis is carried out under the specific environment temperature again to obtain the table of each node in the thermal model
Face temperature obtains the new convection transfer rate of each node according to the surface temperature of each node, thereby executing next time
Iterative processing.
Wherein, step obtains the convection transfer rate of each node according to the surface temperature of each node, further wraps
It includes:
According to the surface temperature of each node using experience convection coefficient formula to obtain the heat convection of each node
Coefficient.
Wherein, the experience convection coefficient formula are as follows:
H=0.83*f* ((Ts-T∞)/P1)n
Wherein, h is convection transfer rate (W/m3℃)；TsFor planar surface temperature (DEG C)；T∞For plate ambient air temperature
(℃)；
Vertical surface: P1=H, f=1.22, n=0.35；
Level board upper surface: P1=W*L/2 (W+L), f=1.00, n=0.33；
Level board lower surface: P1=W*L/2 (W+L), f=0.50, n=0.33；
Above-mentioned L is horizontal plane length, and W is horizontal plane width, and H is vertical height, and f and n are to rely on the normal of surface heat transfer
Amount.
In order to solve the above technical problems, there is provided a kind of semiconductor package bodies for another technical solution used in the present invention
Thermal resistance method for detecting, comprising:
Finite element thermal analysis model is established to the semiconductor package body；
Set one group of initial convection transfer rate, and by the initial convection current of each of the initial convection transfer rate of the group
The coefficient of heat transfer is respectively correspondingly loaded onto the corresponding node in the thermal model；
Steady-state thermal analysis is carried out, under specific environment temperature to obtain the table of each node in the thermal model
Face temperature；
The convection transfer rate of each node is obtained according to the surface temperature of each node；
It is iterated processing according to the convection transfer rate of each node and initial convection transfer rate, it is every to obtain
The NATURAL CONVECTION COEFFICIENT OF HEAT of a node；
The thermal resistance of the semiconductor package body is obtained according to the NATURAL CONVECTION COEFFICIENT OF HEAT of each node.
Wherein, step is iterated processing according to the convection transfer rate and initial convection transfer rate of each node
To obtain the NATURAL CONVECTION COEFFICIENT OF HEAT of each node, further comprise:
Judge difference between the convection transfer rate of each node and its initial convection transfer rate absolute value whether
Less than range of tolerable variance value；
As the absolute value of difference between the convection transfer rate of each node and its initial convection transfer rate is less than institute
Range of tolerable variance value is stated, then the iterative processing terminates and using the convection transfer rate of each node as the naturally right of each node
Flow the coefficient of heat transfer；Otherwise, then using the convection transfer rate of each node as the initial convection transfer rate of each node, and
Steady-state thermal analysis is carried out under the specific environment temperature again to obtain the table of each node in the thermal model
Face temperature obtains the new convection transfer rate of each node according to the surface temperature of each node, thereby executing next time
Iterative processing.
Wherein, step obtains the convection transfer rate of each node according to the surface temperature of each node, further wraps
It includes:
According to the surface temperature of each node using experience convection coefficient formula to obtain the heat convection of each node
Coefficient.
Wherein, the experience convection coefficient formula are as follows:
H=0.83*f* ((Ts-T∞)/P1)n
Wherein, h is convection transfer rate (W/m3℃)；TsFor planar surface temperature (DEG C)；T∞For plate ambient air temperature
(℃)；
Vertical surface: P1=H, f=1.22, n=0.35；
Level board upper surface: P1=W*L/2 (W+L), f=1.00, n=0.33；
Level board lower surface: P1=W*L/2 (W+L), f=0.50, n=0.33；
Above-mentioned L is horizontal plane length, and W is horizontal plane width, and H is vertical height, and f and n are to rely on the normal of surface heat transfer
Amount.
Wherein, step obtains the thermal resistance of the semiconductor package body according to the NATURAL CONVECTION COEFFICIENT OF HEAT of each node,
Further comprise:
The section temperature of the semiconductor package body is obtained according to the NATURAL CONVECTION COEFFICIENT OF HEAT of each node；
The thermal resistance of the semiconductor package body is obtained according to the section temperature of the semiconductor package body.
Wherein, step obtains the thermal resistance of the semiconductor package body according to the section temperature of the semiconductor package body, into
One step includes:
The thermal resistance of the semiconductor package body is obtained using following formula according to the section temperature of semiconductor package body:
θJA=(TJ-TA)/P,
Wherein: TJIt is junction temperature, i.e. the temperature of chip surface, DEG C；TAIt is ambient air temperature, DEG C；P is the total consumption of chip
Power, W；θJAIt is thermal resistance of the chip surface to ambient enviroment, DEG C/W.
The beneficial effects of the present invention are: being in contrast to the prior art, the present invention calculates convection current using the method for iteration
The coefficient of heat transfer, then the convection transfer rate that iteration convergence is obtained are loaded into finite element solid analysis model, and sunykatuib analysis obtains
The thermal resistance of encapsulating products out can be improved the accuracy of simulation thermal resistance.
Detailed description of the invention
Fig. 1 is a kind of method for detecting process of the NATURAL CONVECTION COEFFICIENT OF HEAT of semiconductor package body of embodiment of the present invention
Figure；
Fig. 2 is the detailed step flow chart of step 105 in Fig. 1；
Fig. 3 is a kind of NATURAL CONVECTION COEFFICIENT OF HEAT method for detecting flow chart of FCBGA packaging body of embodiment of the present invention；
Fig. 4 is a kind of FCBGA package body structure schematic diagram of embodiment of the present invention；
Fig. 5 is a kind of finite element thermal analysis model schematic of FCBGA packaging body of embodiment of the present invention；
Fig. 6 is a kind of NATURAL CONVECTION COEFFICIENT OF HEAT method for detecting flow chart of QFP packaging body of embodiment of the present invention；
Fig. 7 is a kind of QFP package interior structural schematic diagram of embodiment of the present invention；
Fig. 8 is a kind of finite element thermal analysis model schematic of QFP packaging body of embodiment of the present invention；
Fig. 9 is a kind of method for detecting flow chart of the thermal resistance of semiconductor package body of embodiment of the present invention；
Figure 10 is the detailed step flow chart of step S906 in Fig. 9；
Figure 11 A is a kind of Temperature Distribution cloud atlas of the FCBGA packaging body of embodiment of the present invention without iteration；
Figure 11 B is that a kind of FCBGA packaging body of embodiment of the present invention carries out the Temperature Distribution cloud atlas of an iteration；
Figure 11 C is that a kind of FCBGA packaging body of embodiment of the present invention carries out the Temperature Distribution cloud atlas of iteration twice；
Figure 11 D is that a kind of FCBGA packaging body of embodiment of the present invention carries out the Temperature Distribution cloud atlas of iteration three times；
Figure 12 A is a kind of Temperature Distribution cloud atlas of the QFP packaging body of embodiment of the present invention without iteration；
Figure 12 B is that a kind of QFP packaging body of embodiment of the present invention carries out the Temperature Distribution cloud atlas of an iteration；
Figure 12 C is that a kind of QFP packaging body of embodiment of the present invention carries out the Temperature Distribution cloud atlas of iteration twice；
Figure 12 D is that a kind of QFP packaging body of embodiment of the present invention carries out the Temperature Distribution cloud atlas of iteration three times.
Specific embodiment
Refering to fig. 1 and Fig. 2, Fig. 1 be embodiment of the present invention a kind of semiconductor package body NATURAL CONVECTION COEFFICIENT OF HEAT
Method for detecting flow chart, specifically includes the following steps:
S101 establishes finite element thermal analysis model to semiconductor package body；
In an application scenarios, APDL programming mode can be used and establish semiconductor package body finite element thermal analysis model,
The modes such as GUI, extraneous importing can also be used in other scenes, which is not limited by the present invention.Specifically, firstly, establishing envelope
Fill the geometrical model of body, model pel be set, including body, face, line, key point, using boolean operation to the model pel into
Row combination calculates；Secondly, setting unit attribute, the features such as material properties, cell type, the real constant of designated analysis object；Most
Afterwards, mesh of finite element division is carried out to entity finite element structural model, including defines said units attribute, setting size of mesh opening.
S102 sets one group of initial convection transfer rate, and each of initial convection transfer rate of the group is initial
Convection transfer rate is respectively correspondingly loaded onto the corresponding node in thermal model；
Specifically, above-mentioned initial convection transfer rate preparation method is, can be pre- according to the practical heat condition of encapsulating products
First estimate that the maximum temperature of a node can derive initial heat convection so that it is determined that the temperature difference, then calculates according to formula
Coefficient.
S103 carries out steady-state thermal analysis under specific environment temperature, to obtain the table of each node in thermal model
Face temperature.
S104 obtains the convection transfer rate of each node according to the surface temperature of each node；
Specific implementation is that each section is obtained using experience convection coefficient formula according to the surface temperature of each node
The convection transfer rate of point.In an application scenarios, experience convection coefficient formula can change for the QuanLi free convection proposed
Hot coefficient:
H=0.83*f* ((Ts-T∞)/P1)n (1)
Wherein, h is convection transfer rate (W/m3℃)；TsFor planar surface temperature (DEG C)；T∞For plate ambient air temperature
(℃)；
Vertical surface: P1=H, f=1.22, n=0.35；
Level board upper surface: P1=W*L/2 (W+L), f=1.00, n=0.33；
Level board lower surface: P1=W*L/2 (W+L), f=0.50, n=0.33；
Above-mentioned L is horizontal plane length, and W is horizontal plane width, and H is vertical height, and f and n are to rely on the normal of surface heat transfer
Amount.
In other embodiments, other experience convection transfer rate formula can also be used, this is not limited by the present invention, such as
Elhson convection coefficient formula can be used,
hp-up=1.336* ((Ts-T∞)/P1)0.25 (2)
hp-dn=0.668* ((Ts-T∞)/P1)0.25 (3)
Wherein, hp-up、hp-dnFor convection transfer rate (W/m3℃)；TsFor planar surface temperature (DEG C)；T∞Around plate
Air themperature (DEG C)；Formula (2) be used to calculate two kinds of isothermal free-convection factors, one is for encapsulate upper surface, one is
For the upper surface of PCB substrate；Formula (3) is used to calculate PCB substrate lower surface.
S105 is iterated processing according to the convection transfer rate and initial convection transfer rate of each node, with
To the NATURAL CONVECTION COEFFICIENT OF HEAT of each node.
To realize above-mentioned steps, Fig. 2 gives specific steps flow chart, comprising:
S201 judges the absolute value of difference between the convection transfer rate of each node and its initial convection transfer rate
Whether range of tolerable variance value is less than；
The absolute value of difference is small between S202 such as the convection transfer rate and its initial convection transfer rate of each node
In range of tolerable variance value, then iterative processing is terminated and is changed using the convection transfer rate of each node as the free convection of each node
Hot coefficient；
S203 otherwise, then using the convection transfer rate of each node as the initial convection transfer rate of each node,
And again under specific environment temperature carry out steady-state thermal analysis to obtain the surface temperature of each node in thermal model,
The new convection transfer rate of each node is obtained according to the surface temperature of each node, at iteration next time
Reason.
Fig. 3-Fig. 5 is please referred to, package body structure is specifically below in conjunction with practical FCBGA (flip chip ball grid lattice array)
The method for detecting of bright above-mentioned NATURAL CONVECTION COEFFICIENT OF HEAT.
Fig. 3 is the flow chart of the NATURAL CONVECTION COEFFICIENT OF HEAT method for detecting of FCBGA semiconductor package body, including walks as follows
It is rapid:
S301: FCBGA encapsulating products finite element thermal analysis model is established；
Referring to Figure 4 together, Fig. 4 is FCBGA package structure diagram, and the process flow being typically prepared is, first in chip
401 electrode surfaces do 402 salient point of solder ball, then tip upside down on substrate 403, by Reflow Soldering by solder ball 402 and substrate 403
Pad connection, then fill out 404 the bottom of with and carry out underfill, solidify underfill glue, then encapsulate chip with encapsulating material 405
401 peripheries, are integrally welded on pcb board 407 finally by soldered ball 406 by above-mentioned.
The following table 1 is that FCBGA packaging body closes parameter, the thermal coefficient including geometric structure diamete parameter and each structure；This
The pcb board of FCBGA packaging body can be 1S1P doubling plate in embodiment, and S and P respectively represent signals layer and bus plane, in other realities
Applying can also be tetra- laminate of 2S2P etc. in example, and the present invention is without limitation.
1 FCBGA packaging body relevant parameter of table
| Structure | Size, mm | Thermal coefficient, w/ (m DEG C) |
| Chip | 12.4*15.3*0.86 | 180 |
| Bottom is filled out | 12.4*15.3*0.07 | 0.8 |
| Substrate | 33*33*1.2 | 193 (horizontal direction)/0.7 (vertical direction) |
| Soldered ball | Diameter 0.6 | 46 |
| Encapsulating material | 33*33*1.2 | 0.94 |
| PCB | 104*76*1.6 | 193 (horizontal direction)/0.94 (horizontal direction) |
According to the relevant parameter and above-mentioned preparation process in table 1, using the building FCBGA encapsulation of APDL programming mode
Body finite element thermal analysis model, model structure are as shown in Figure 5.It is respectively encapsulating material 504, chip 501, substrate under upper
505, pcb board 506, wherein Fig. 4 indsole fills out 404 and is reduced to soldered ball 406 in one layer of 502, Fig. 4 with solder ball 402 and is reduced to one layer
503。
S302: assuming that initial convection transfer rate h1；
For calculating the upper surface PCB convection transfer rate, first according to the practical heat condition of encapsulating products, pre-estimate
Node temperature is 30 DEG C, and environment temperature is 25 DEG C under Natural Convection Conditions, according to above-mentioned formula (1) and the dimension data of pcb board,
It is 5w/ (m that initial coefficient of heat transfer h1, which is calculated,3℃)；
S303: according to convection transfer rate h1, fluid temperature (F.T.) T1, steady-state thermal analysis is carried out, the temperature on model node is obtained
Angle value T；
Setting concurrent condition is free convection, and fluid temperature (F.T.) is that T1 is 25 DEG C, is loaded on finite element model according to model
Temperature Distribution cloud atlas obtain egress temperature value T be 66 DEG C.
S304: the new convection transfer rate h2 of egress is obtained according to surface temperature T；
66 DEG C of temperature T value are brought into above-mentioned formula (1), acquiring h2 is 9.95w/ (m3℃)。
S305: compare the size of I h1-h2 I and range of tolerable variance, if I h1-h2, I < range of tolerable variance, iteration convergence obtain convection current
The coefficient of heat transfer h, h=h2；Otherwise, by h1=h2, step S302 is turned to；
Range of tolerable variance is preferably 1.5 in the present embodiment, can be changed according to the actual situation in other embodiments, this
Invention to this with no restriction.
The value of h1 need to be assigned a value of h2 significantly more than range of tolerable variance 1.5 by the value through above-mentioned I h1-h2 I of an iteration, into
Row next iteration, iterative process data are as shown in table 2 below, as can be seen that passing through 3 iteration from 2 data of table, obtain most
The coefficient of heat transfer of the whole upper surface PCB is 6.79w/ (m3℃)。
2 upper surface FCBGA package body structure PCB convection transfer rate iterative data of table
| The number of iterations | The upper surface PCB convection transfer rate value, w/ (m3℃) |
| 0 | 5 |
| 1 | 9.95 |
| 2 | 7.97 |
| 3 | 6.79 |
Fig. 6-Fig. 8 is please referred to, is further illustrated below in conjunction with another practical QFP (four side pins are flat) encapsulating structure
The method for detecting of above-mentioned NATURAL CONVECTION COEFFICIENT OF HEAT.
Fig. 6 is the NATURAL CONVECTION COEFFICIENT OF HEAT method for detecting flow chart of QFP packaging body, the free convection with above-mentioned FCBGA
The method for detecting of the coefficient of heat transfer is compared, the difference is that step S601, establish the finite element thermal analysis model of QFP packaging body with
Above-mentioned FCBGA model is variant, remaining step is identical, and details are not described herein for identical content.
Referring to Fig. 7, Fig. 7 is QFP package interior structural schematic diagram.QFP packaging body generally uses copper or copper alloy etc.
The nead frame of material production, the nead frame is for providing external pin 704.The preparation process flow of QFP packaging body is, first
Chip 701 and substrate 706 are first filled out into 705 bondings the bottom of by and form a chip entirety, then leads to the pin of nead frame 704
It crosses lead 703 to be bonded on chip, is then packaged said chip entirety by encapsulating material 702 with nead frame；Most
Afterwards by above-mentioned encapsulation integral installation on pcb board 707, external pin 704 is processed after molded.
The following table 3 is QFP packaging body relevant parameter, the thermal coefficient including geometric structure diamete parameter and each structure；This
The pcb board of QFP packaging body can be 1S1P doubling plate in embodiment, and S and P respectively represent signals layer and bus plane, in other implementations
It can also be tetra- laminate of 2S2P etc. in example, the present invention is without limitation.
3 QFP packaging body relevant parameter of table
| Structure | Size, mm | Thermal coefficient, w/ (m DEG C) |
| Chip | 6*6*0.28 | 180 |
| Bottom is filled out | 6*6*0.04 | 0.8 |
| Substrate | 8*8*0.1 | 193 (horizontal direction)/0.7 (vertical direction) |
| Encapsulating material | 20*20*1.4 | 0.94 |
| PCB | 104*76*1.6 | 193 (horizontal direction)/0.94 (vertical direction) |
According to the relevant parameter and above-mentioned preparation process in table 3, QFP packaging body is constructed using APDL programming mode
Finite element thermal analysis model, model structure are as shown in Figure 8.It is respectively encapsulating material 804, chip 801, substrate under upper
802, pcb board 805, wherein Fig. 7 indsole fills out 705 and is reduced to pin 704 in one layer of 803, Fig. 7 and omits in the schematic diagram draw.
By taking the convection transfer rate of QFP packaging body pcb board upper surface as an example, range of tolerable variance is selected as 1.5, the results are shown in Table 4, warp
After iteration twice, show that the coefficient of heat transfer of the upper surface PCB is 10.98w/ (m3℃)。
4 upper surface QFP package body structure PCB convection transfer rate iterative data of table
| The number of iterations | The upper surface PCB convection transfer rate value, w/ (m3℃) |
| 0 | 5 |
| 1 | 12.16 |
| 2 | 10.98 |
The convection transfer rate of each structure of semiconductor package body is loaded on finite element thermal analysis model, can be simulated
The thermal resistance for obtaining packaging body please refers to Fig. 9-Figure 10, and the present invention also provides a kind of method for detecting of semiconductor package body thermal resistance.
Fig. 9 is a kind of specific steps of the method for detecting of semiconductor package body thermal resistance, comprising:
S901: finite element thermal analysis model is established to semiconductor package body；
S902: one group of initial convection transfer rate of setting, and just by each of initial convection transfer rate of the group
Beginning convection transfer rate is respectively correspondingly loaded onto the corresponding node in thermal model；
S903: carrying out steady-state thermal analysis under specific environment temperature, to obtain each node in thermal model
Surface temperature；
S904: the convection transfer rate of each node is obtained according to the surface temperature of each node；
S905: being iterated processing according to the convection transfer rate of each node and initial convection transfer rate, with
Obtain the NATURAL CONVECTION COEFFICIENT OF HEAT of each node；
S906: the thermal resistance of semiconductor package body is obtained according to the NATURAL CONVECTION COEFFICIENT OF HEAT of each node.
The content of step S901-S905 is consistent with above-mentioned test semiconductor package body convection transfer rate content, herein not
It repeats again.
Wherein, step S906 further comprises:
S1001: the section temperature of semiconductor package body is obtained according to the NATURAL CONVECTION COEFFICIENT OF HEAT of each node；
S1002: the thermal resistance of semiconductor package body is obtained according to the section temperature of semiconductor package body.
In the present embodiment, using following formula realize step S1002 according to the section temperature of semiconductor package body and
Obtain the thermal resistance of semiconductor package body:
θJA=(TJ-TA)/P (4)
Wherein: TJIt is junction temperature, i.e. the temperature of chip surface, DEG C；
TAIt is ambient air temperature, DEG C；
P is the power of the total consumption of chip, W；
θJAIt is thermal resistance of the chip surface to ambient enviroment, DEG C/W.
Specifically, one group of convection transfer rate is loaded on finite element analysis model, by Temperature Distribution cloud atlas, obtain
Maximum temperature, the temperature are junction temperature TJ, then by TJAnd TAValue bring formula (4) into, obtain thermal resistance value.
To verify the accuracy for using alternative manner calculating simulation thermal resistance, the present invention is sealed using JESD51-14 standard detection
The practical thermal resistance of body is filled, by practical thermal resistance value compared with simulating thermal resistance value.Analog chip heating power is 1W in the present embodiment, at it
In his embodiment, other performance numbers, the invention is not limited in this regard can be.
In an application scenarios, thermal resistance analysis, finite element thermal analysis model and above-mentioned reality are carried out to FCBGA packaging body
It applies FCBGA packaging body in example and carries out identical when convection transfer rate analysis, thermal resistance analysis data result is as shown in table 5 below,
The Temperature Distribution cloud atlas of its iterative process is as shown in fig. s 11a through 11d.
5 FCBGA packaging body thermal resistance analysis data of table
As can be seen from the table, with the increase of the number of iterations, thermal resistance value and actual test value difference are simulated away from shortening, through three
After secondary iteration, simulation thermal resistance value is 12.65 DEG C/W, compared with 13 DEG C/W of actual measurement thermal resistance value, error 2.7%.
In another application scenarios, thermal resistance analysis, finite element thermal analysis model and above-mentioned reality are carried out to QFP packaging body
It applies QFP packaging body in example and carries out identical when convection transfer rate analysis, thermal resistance analysis data result is as shown in table 6 below,
The Temperature Distribution cloud atlas of iterative process is as shown in fig. s 12a through 12d.
6 QFP packaging body thermal resistance analysis data of table
As can be seen from the table, with the increase of the number of iterations, thermal resistance value and actual test value difference are simulated away from shortening, iteration
After three times, simulation thermal resistance value is 35.39 DEG C/W, compared with 35 DEG C/W of actual measurement thermal resistance value, error 1.1%.
From above two packaging body thermal resistance analysis result it is found that iteration for several times after simulation thermal resistance value close to actual test
Value, and maximum error rate is no more than 3%, so that it is determined that the availability of convection transfer rate empirical equation and the standard of alternative manner
True property, the accuracy of encapsulating products thermal resistance calculation can be improved by alternative manner.
The above is only embodiments of the present invention, are not intended to limit the scope of the invention, all to utilize the present invention
Equivalent structure or equivalent flow shift made by specification and accompanying drawing content is applied directly or indirectly in other relevant technologies
Field is included within the scope of the present invention.
Claims (4)
1. a kind of method for detecting of the NATURAL CONVECTION COEFFICIENT OF HEAT of semiconductor package body characterized by comprising
Finite element thermal analysis model is established to the semiconductor package body；
Set one group of initial convection transfer rate, and by the initial heat convection of each of the initial convection transfer rate of the group
Coefficient is respectively correspondingly loaded onto the corresponding node in the thermal model；
Steady-state thermal analysis is carried out, under specific environment temperature to obtain the surface temperature of each node in the thermal model
Degree；
The convection transfer rate of each node is obtained according to the surface temperature of each node；
Judge whether the absolute value of difference between the convection transfer rate of each node and its initial convection transfer rate is less than
Range of tolerable variance value；
The absolute value of difference is less than the appearance such as between the convection transfer rate and its initial convection transfer rate of each node
Poor value range, then iterative processing terminates and using the convection transfer rate of each node as the heat transfer free convection system of each node
Number；Otherwise, then using the convection transfer rate of each node as the initial convection transfer rate of each node, and again in institute
It states and carries out steady-state thermal analysis under specific environment temperature to obtain the surface temperature of each node in the thermal model, root
According to the surface temperature of each node using experience convection coefficient formula to obtain the new convection transfer rate of each node, from
And execute iterative processing next time.
2. method for detecting according to claim 1, which is characterized in that the experience convection coefficient formula are as follows:
H=0.83*f* ((Ts-T∞)/P1)n
Wherein, h is convection transfer rate (W/m3℃)；TsFor planar surface temperature (DEG C)；T∞For plate ambient air temperature
(℃)；
Vertical surface: P1=H, f=1.22, n=0.35；
Level board upper surface: P1=W*L/2 (W+L), f=1.00, n=0.33；
Level board lower surface: P1=W*L/2 (W+L), f=0.50, n=0.33；
Above-mentioned L is horizontal plane length, and W is horizontal plane width, and H is vertical height, and f and n are to rely on the constant of surface heat transfer.
3. a kind of method for detecting of the thermal resistance of semiconductor package body characterized by comprising
Finite element thermal analysis model is established to the semiconductor package body；
Set one group of initial convection transfer rate, and by the initial heat convection of each of the initial convection transfer rate of the group
Coefficient is respectively correspondingly loaded onto the corresponding node in the thermal model；
Steady-state thermal analysis is carried out, under specific environment temperature to obtain the surface temperature of each node in the thermal model
Degree；
The convection transfer rate of each node is obtained according to the surface temperature of each node；
Judge whether the absolute value of difference between the convection transfer rate of each node and its initial convection transfer rate is less than
Range of tolerable variance value；
The absolute value of difference is less than the appearance such as between the convection transfer rate and its initial convection transfer rate of each node
Poor value range, then iterative processing terminates and using the convection transfer rate of each node as the heat transfer free convection system of each node
Number；Otherwise, then using the convection transfer rate of each node as the initial convection transfer rate of each node, and again in institute
It states and carries out steady-state thermal analysis under specific environment temperature to obtain the surface temperature of each node in the thermal model, root
The new convection transfer rate of each node is obtained using experience convection coefficient formula according to the surface temperature of each node, thus
Execute iterative processing next time；
The section temperature of the semiconductor package body is obtained according to the NATURAL CONVECTION COEFFICIENT OF HEAT of each node；
The thermal resistance of the semiconductor package body: θ is obtained using following formula according to the section temperature of semiconductor package bodyJA=
(TJ-TA)/P, wherein: TJIt is junction temperature, i.e. the temperature of chip surface, DEG C；TAIt is ambient air temperature, DEG C；P, which is that chip is total, to disappear
The power of consumption, W；θJAIt is thermal resistance of the chip surface to ambient enviroment, DEG C/W.
4. method for detecting according to claim 3, which is characterized in that the experience convection coefficient formula are as follows:
H=0.83*f* ((Ts-T∞)/P1)n
Wherein, h is convection transfer rate (W/m3℃)；TsFor planar surface temperature (DEG C)；T∞For plate ambient air temperature
(℃)；
Vertical surface: P1=H, f=1.22, n=0.35；
Level board upper surface: P1=W*L/2 (W+L), f=1.00, n=0.33；
Level board lower surface: P1=W*L/2 (W+L), f=0.50, n=0.33；
Above-mentioned L is horizontal plane length, and W is horizontal plane width, and H is vertical height, and f and n are to rely on the constant of surface heat transfer.
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| CN105301468A (en) * | 2014-06-19 | 2016-02-03 | 上海时代之光照明电器检测有限公司 | Method for detecting heat dispersion of LED chip or package |
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| CN105301468A (en) * | 2014-06-19 | 2016-02-03 | 上海时代之光照明电器检测有限公司 | Method for detecting heat dispersion of LED chip or package |
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