CN102608511A - Method for measuring junction temperature and thermal resistance of metal-oxide semiconductor tube - Google Patents

Method for measuring junction temperature and thermal resistance of metal-oxide semiconductor tube Download PDF

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CN102608511A
CN102608511A CN2012100595022A CN201210059502A CN102608511A CN 102608511 A CN102608511 A CN 102608511A CN 2012100595022 A CN2012100595022 A CN 2012100595022A CN 201210059502 A CN201210059502 A CN 201210059502A CN 102608511 A CN102608511 A CN 102608511A
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temperature
under test
source
drain
grid
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CN2012100595022A
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CN102608511B (en
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钱钦松
刘斯扬
张頔
孙伟锋
陆生礼
时龙兴
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东南大学
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Abstract

The invention discloses a method for measuring the junction temperature and thermal resistance of a metal-oxide semiconductor tube. The method comprises the following steps of: placing an insulating substrate with a device to be measured into a temperature control box, and adjusting the temperature control box to 25 DEGC; applying a DC (direct current) voltage to the drain end and source end of the device to be measured, and applying a grid DC working voltage to the grid; measuring the current at the drain and source ends of the device to be measured when the voltage on the grid is a DC working voltage; removing the DC working voltage on the grid; applying a square-wave pulse voltage to the grid; gradually increasing the temperature in the temperature control box, wherein the maximum temperature does not exceed the junction temperature of the measured device; continuously measuring the leakage current at the drain and source ends of the device to be measured; and when the measured leakage current at the drain and source ends of the device to be measured is equal to the current at the drain and source ends of the device to be measured, calculating the thermal resistance of the device to be measured by taking the temperature in the temperature control box as an equivalent junction temperature.

Description

A kind of junction temperature of MOS transistor and thermal resistance measurement method
Technical field
This technology belongs in the microelectric technique, and the semiconductor devices field of measuring technique relates in particular to a kind of junction temperature and thermal resistance measurement method of MOS transistor.
Background technology
After the chip manufacturing of large scale integrated circuit is accomplished,, it is carried out outside the integrated situation of secondary, in most cases all need encapsulation except adopting thick-film technique or thin-film technique.The encapsulation of large scale integrated circuit is called the back operation again.The effect of encapsulation is to connect for chip provides electricity, machinery carries; Make it easy to manipulate; For the user of large scale integrated circuit provides the mounting structure and the size of a standard, avoid chip to receive the external force effect, scratch, receive the erosion of water vapor or other harmful gases, sometimes can also in same encapsulating structure, encapsulate a plurality of chips; Thereby the function that IC chip can be brought into normal play, and guarantee that it has high stability and reliability.Be accompanied by the continuous development of power device and manufacture of microchips, also increasing for the input of semiconductor packages industry, the encapsulation industry has also got into a high-speed developing period.
The design of semiconductor packages and the quality of quality, very big to the good and bad influence of the overall performance of integrated circuit, because encapsulation should have stronger mechanical property, good performance of heat dissipation, chemical stability and electric property.Encapsulation also must adapt to the needs and the development of product fully, because the function and application of various product is different, its general structure is also often different with the encapsulation requirement, so the integrated circuit encapsulation must be varied, could satisfy the needs of various products.
Power semiconductor device always produces certain heat at work, if these heats can not blaze abroad timely and effectively, will cause the device inside heat accumulation; Junction temperature rises; Make device reliability reduce, even cause device function to lose efficacy, can't trouble free service.
The heat-sinking capability of power semiconductor device characterizes with packaging thermal resistance usually, and thermal resistance is more little, and then heat-sinking capability is good more.Therefore, physical significance, use-pattern and the measuring technique of correctly understanding packaging thermal resistance is for the analysis that improves the device heat-sinking capability and be designed with very big help.According to different needs, packaging thermal resistance has the various definitions form, and topmost is following two kinds of definition modes, and each big semiconductor manufacturer also generally only gives the thermal resistance information of these two kinds of definition.
A. tie the thermal resistance R of external environment θ JA: under natural convection or conditions of forced convection, connect the thermal resistance of face to the atmosphere from chip, be used for the comparison package cooling easily whether.
B. tie the thermal resistance R of shell θ JC: being meant that heat connects the thermal resistance that face passes to the IC package casing by chip, when measuring, need contacting an isothermal surface, mainly is the heat dispersion that is used to assess heat radiator.
Measuring method to semiconductor devices working temperature and thermal resistance mainly contains at present: thermal infrared imager method, electrical parameter method, spectroscopic methodology, photo-thermal resistance scanning method and luminous power method etc.These methods can be measured the Temperature Distribution of semiconductor device surface or the medial temperature on certain meaning based on different measurement principles, and these methods often all need special-purpose testing apparatus or complicated test macro.As: infrared scan thermal imagery method is to use infrared thermometer to come the characterizing device surface temperature distribution.Accurately the junction temperature of measuring element, junction temperature distribute and thermal resistance parameters, help to take corrective action in the development and design stage, improve the serviceable life of device, also can be used for the screening of high reliability device.But the infrared scan device structure is complicated, method of operating is complicated, testing efficiency is low, must expend the more time; Cost is high; And can only be that device or chip are the states for encapsulation or Kaifeng to device or direct measurement of chip surface, therefore the examination to practical devices or chip finished product can not meet the demands.
Summary of the invention
Shortcoming to prior art; The purpose of this invention is to provide a kind of simple a kind of junction temperature and thermal resistance measurement method of MOS transistor fast; After adopting the present invention; Only need to use standing testing apparatus and instrument, just can realize nondestructive testing semiconductor devices working junction temperature and steady state heat resistance.
The present invention adopts following technical scheme:
A kind of junction temperature of MOS transistor and thermal resistance measurement method,
The insulated substrate that step 1 will be placed with device under test is placed in the temperature-controlled cabinet; And temperature-controlled cabinet transferred to 25 ℃, according to the scope of device under test safety operation area, guarantee that device under test can the prerequisite of operate as normal under; Apply DC voltage for device under test drain-source two ends
Step 2 applies the direct grid current WV on grid, the electric current at device under test drain-source two ends when the voltage on the measurement grid is direct-current working volts,
Step 3 removes the direct-current working volts on the grid; On grid, apply square wave pulse voltage again, the amplitude of said square wave pulse voltage equals the described direct-current working volts of step 2, dutycycle less than 1% and the cycle be not more than 1 millisecond; After this; Increase the temperature-controlled cabinet temperature inside gradually, maximum temperature is no more than the test component junction temperature, and the leakage current at device under test drain-source two ends can constantly descend along with the rising gradually of temperature-controlled cabinet internal temperature; Use current measure device constantly to measure the leakage current at device under test drain-source two ends
When the leakage current at the device under test drain-source two ends that record equates with the electric current at the device under test drain-source two ends that recorded by step 2; Note the temperature-controlled cabinet internal temperature of this moment and with the temperature-controlled cabinet internal temperature of this moment as equivalent junction temperature, and get into step 5;
When if the temperature-controlled cabinet internal temperature is increased to the maximum junction temperature that device under test allows; Measured leakage current still is higher than the measured leakage current of step 2, then removes the square wave pulse voltage on the grid, reduces the DC voltage at device under test drain-source two ends; Return step 2
Step 4 is calculated the thermal resistance value of device under test, according to formula,
R θJA = T J - T A P H = T J - T A V ds · I ds
Wherein, T JBe the equivalent junction temperature of record in the step 3, T ABe 25 ℃ of the room temperatures that set, P HBe the power consumption of device under test, V DsBe the magnitude of voltage at device under test drain-source two ends in the step 2, I DsBe the current value at device under test drain-source two ends measured in the step 2, R θ JATie the stable state packaging thermal resistance value of environment temperature for device under test, will test the gained data and bring above-mentioned formula into, calculate the steady state thermal resistance of device under test.
Compared with prior art, the present invention has following advantage:
1. junction temperature of the present invention and thermo-resistance measurement system cost are low.Compare with the thermo-resistance measurement instrument that adopts in the industry; Equipment that test macro of the present invention comprised and instrument; For example, temperature-controlled cabinet, pulse producer, oscillograph, power meter etc. are general electronic experiment chamber interior indispensable testing apparatus and instrument; And on the market the quotation of standard set apparatus of heat resistance test generally at hundreds of thousands about up to a million, cost an arm and a leg.
2. thermo-resistance measurement method of the present invention is simple to operate, does not have the complicated operations step, and desired data all shows through the instrument numeral.
3. thermo-resistance measurement method of the present invention is nondestructive.Contact class methods with other physics and the optics method is compared, method of testing of the present invention can not cause substantial damage to device under test, need be to operations such as device under test break a seal.
4. thermo-resistance measurement method of the present invention has the wider scope of application.Thermo-resistance measurement method provided by the invention not only can test package level semiconductor discrete device junction temperature and thermal resistance, junction temperature and the thermal resistance value that can also test specific integrated device in the package level chip that meets test condition of the present invention.In addition, the junction temperature of the present invention under also can test wafer level semiconductor device duty.
5. thermo-resistance measurement of the present invention system has suitable dirigibility.In the production practices of reality, sometimes need semiconductor devices at different packing forms, different substrates, the junction temperature under the varying environment temperature and thermal resistance information.In this case, only need the application conditions of reality be transplanted in this test macro and get final product, very convenient.
6. thermo-resistance measurement of the present invention system does not receive the restriction of device under test packing forms.
Description of drawings
Fig. 1 is a test flow chart of the present invention.
Fig. 2 is package level semiconductor devices steady state heat resistance R θ JAThe definition synoptic diagram.
Fig. 3 is a semiconductor devices self-heating effect synoptic diagram.
Fig. 4 is operated under the impulsive condition for device under test, the electric current that leaks hunting with the change curve of environment temperature.
Fig. 5 is operated under the impulsive condition for device under test, and leakage current is with the variation diagram in gate pulse cycle.Wherein, the amplitude of gate pulse, hold time and rise and fall all remained unchanged along the time.
Embodiment
A kind of junction temperature of MOS transistor and thermal resistance measurement method,
The insulated substrate that step 1 will be placed with device under test is placed in the temperature-controlled cabinet; And temperature-controlled cabinet transferred to 25 ℃, according to the scope of device under test safety operation area, guarantee that device under test can the prerequisite of operate as normal under; Apply DC voltage for device under test drain-source two ends
Step 2 applies the direct grid current WV on grid, the electric current at device under test drain-source two ends when the voltage on the measurement grid is direct-current working volts,
Step 3 removes the direct-current working volts on the grid, on grid, applies square wave pulse voltage again, and the amplitude of said square wave pulse voltage equals the described direct-current working volts of step 2; Dutycycle less than 1% and the cycle be not more than 1 millisecond; In the present embodiment, the amplitude of said square wave pulse voltage equals the described direct-current working volts of step 2, and dutycycle is 0.5% and 1 millisecond of cycle; After this; Increase the temperature-controlled cabinet temperature inside gradually, maximum temperature is no more than the test component junction temperature, and the leakage current at device under test drain-source two ends can constantly descend along with the rising gradually of temperature-controlled cabinet internal temperature; Use current measure device constantly to measure the leakage current at device under test drain-source two ends
When the leakage current at the device under test drain-source two ends that record equates with the electric current at the device under test drain-source two ends that recorded by step 2; Note the temperature-controlled cabinet internal temperature of this moment and with the temperature-controlled cabinet internal temperature of this moment as equivalent junction temperature, and get into step 5;
When if the temperature-controlled cabinet internal temperature is increased to the maximum junction temperature that device under test allows; Measured leakage current still is higher than the measured leakage current of step 2, then removes the square wave pulse voltage on the grid, reduces the DC voltage at device under test drain-source two ends; Return step 2
Step 4 is calculated the thermal resistance value of device under test, according to formula,
R θJA = T J - T A P H = T J - T A V ds · I ds
Wherein, T JBe the equivalent junction temperature of record in the step 3, T ABe 25 ℃ of the room temperatures that set, P HBe the power consumption of device under test, V DsBe the magnitude of voltage at device under test drain-source two ends in the step 2, I DsBe the current value at device under test drain-source two ends measured in the step 2, R θ JATie the stable state packaging thermal resistance value of environment temperature for device under test, will test the gained data and bring above-mentioned formula into, calculate the steady state thermal resistance of device under test.
Principle of work of the present invention is:
For semiconductor devices, the computing formula of thermal resistance can be expressed as,
R θJX = [ ΔT J ] X P H = T J - T X V ds · I ds
T J=Y J0+ΔT J
X in the formula is the RP of thermal resistance definition, such as, measuring element is tied the thermal resistance of working environment, and then X represents a bit in the working environment; If measuring element is tied the thermal resistance of package casing, then X represents a bit on the package casing.Correspondingly, temperature rise Δ T JDifference for junction temperature under the semiconductor devices duty to be measured and RP temperature.T J0Be initial temperature, P HPower input for semiconductor devices to be measured.Wherein, initial temperature and power input are easy to record.Therefore, how the key of test thermal resistance is for recording the junction temperature of device under a certain power input.
In order to record the junction temperature of semiconductor devices to be measured under a certain power input condition, we adopt following principle.
At first, at given environment temperature T ADown, because the power attenuation of device inside can cause the device inside temperature to raise, carrier mobility descends, the direct current output characteristics appearance of negative inhibition effect of device.And be operated in impulsive condition following time when semiconductor devices, owing at the device blocking interval, have the regular hour to dispel the heat, therefore, the medial temperature under the relative dc condition of the medial temperature of semiconductor device inside is much smaller.When enough little of the pulsewidth that applies pulse, same enough hour of dutycycle, the heat production time of device, seldom it was chronic to dispel the heat, and the self-heating effect of semiconductor devices can be ignored, and is referred to as to remove the self-heating state.
When same device is operated in dc state respectively and removes the self-heating state; And this device drain-source voltage is identical; The grid voltage amplitude is identical; Cause the inconsistent main difference of device creepage to be device when being operated in dc state, because the influence of self-heating causes leakage current to be operated in the leakage current under the removal self-heating state under the identical biasing much smaller than device.
In addition, device is operated in when removing the self-heating state, and the temperature of device inside is identical with ambient temperature, is in equilibrium state, promptly the device inside temperature can be along with the variation of ambient temperature respective change.At this moment, when raising environment temperature gradually, element leakage fails to be convened for lack of a quorum and descends gradually thereupon, and environment temperature continues to raise, and device creepage also can continue to reduce.When device creepage drops to leakage current when being operated in the dc state under the identical biasing with device and equates; Because under identical bias condition; The leakage current of device is identical; Represent the junction temperature of device inside identical, therefore, the average junction temperature of device inside when the environment temperature of this moment promptly is equivalent to device and is operated in dc state under the identical bias condition.
After obtaining device through this theory and being operated in the inside junction temperature under a certain bias condition (being a certain power input), just can obtain the thermal resistance value of device through the computing formula of thermal resistance.
A preferred embodiment of the present invention accompanying drawings is following:
Standing testing apparatus and instrument comprise following part when using the method for the invention: pulse producer, voltage source generator, current measure device, voltage measuring apparatus, temperature-controlled cabinet, and device under test and substrate.Temperature-controlled cabinet is used to control the environment temperature of device under test; Pulse producer is used for gate pulse stress to device under test being provided; The voltage generator is used for applying direct current drain-source voltage and direct current grid voltage to device under test, and voltage, current measure device are used for monitoring in real time the current value at device under test drain-source two ends and grid end actual voltage value and drain-source two ends.
The junction temperature of above-mentioned MOS transistor and thermo-resistance measurement system and method are tested according to the junction temperature and the thermo-resistance measurement system of above-mentioned MOS transistor, it is characterized in that test operating procedure is following:
1. according to the packing forms and the test request of device under test, substrate is used in the test of selecting to gear to actual circumstances, and through high temperature wire the port of semiconductor devices to be measured is drawn.Simultaneously, measure for ease of follow-up four line sonde methods, each port of device under test will be drawn two higher temperature lines simultaneously.
2. device under test is placed in the constant temperature oven, and the temperature of constant temperature oven is set at 25 ℃ of room temperatures.
3. apply constant DC voltage Vg=5V for device grid end, the drain-source two ends apply constant DC voltage Vd=3.88V.Through after a while, after setting up hot stable state inside and outside the device, the leakage current of the device under test that records is 0.283A.And use the voltage at the device under test drain-source two ends that multimeter records to be 3.855V.
4. cancel the electric stress that applies in the step on the device under test.Then, apply square-wave pulse for device under test grid end, the amplitude of square-wave pulse is Vg=5V; Through continuous adjustment gate pulse parameter, finally definite minimum pulse is held time and is tp=3e-6s, recurrence interval T=0.01s; As shown in Figure 5, when pulse hold time and amplitude certain after, the device under test leakage current increases along with the increase in cycle; Finally tend towards stability, rise and fall are 100ns along the time.After hot stable state was set up inside and outside the device under test, the leakage current that records was 0.485A; The drain-source two ends apply constant DC voltage Vd=3.95V; The voltage of device under test at the terminal corresponding drain-source two ends that gate pulse is held time that uses digital oscilloscope to record is 3.855V, and is consistent with the actual drain-source voltage value that device under test is operated under the dc state.At this moment, environment temperature still is 25 ℃ of room temperatures.
5. be operated in above-mentioned impulsive condition following time when device, the environment temperature that raises gradually, the leakage current of observation device under test changes.When environment temperature rises to 132 ℃, and after hot stable state set up, the leakage current of the device under test that records dropped to 0.283A.Therefore, 132 ℃ of the environment temperatures of this moment are device under test, and to be operated in grid voltage be Vg=5V, leaks and press Vd=3.88V, and environment temperature is 25 ℃, the inside junction temperature under the DC condition.As shown in Figure 4.
6 calculate thermal resistance.According to formula,
R θJA = T J - T A P H = T J - T A V ds · I ds
Wherein, T JBe 132 ℃ of junction temperatures, T ABe 25 ℃ of environment temperature room temperatures, V DsBe the virtual voltage 3.855V at the device under test drain-source two ends that record with multimeter, I DsFor device under test is operated in the DC condition leakage current 0.283A in following time.Then, the steady state heat resistance of device under test is 97.9 ℃/W.
Those skilled in the art do not break away from essence of the present invention and spirit; Can there be the various deformation scheme to realize the present invention; The above is merely the preferable feasible embodiment of the present invention; Be not so limit to interest field of the present invention, the equivalence that the accompanying drawing content is done shown in all utilization present disclosures changes, and all is contained within the interest field of the present invention.

Claims (1)

1. the junction temperature of a MOS transistor and thermal resistance measurement method is characterized in that,
The insulated substrate that step 1 will be placed with device under test is placed in the temperature-controlled cabinet; And temperature-controlled cabinet transferred to 25 ℃, according to the scope of device under test safety operation area, guarantee that device under test can the prerequisite of operate as normal under; Apply DC voltage for device under test drain-source two ends
Step 2 applies the direct grid current WV on grid, the electric current at device under test drain-source two ends when the voltage on the measurement grid is direct-current working volts,
Step 3 removes the direct-current working volts on the grid; On grid, apply square wave pulse voltage again, the amplitude of said square wave pulse voltage equals the described direct-current working volts of step 2, dutycycle less than 1% and the cycle be not more than 1 millisecond; After this; Increase the temperature-controlled cabinet temperature inside gradually, maximum temperature is no more than the test component junction temperature, and the leakage current at device under test drain-source two ends can constantly descend along with the rising gradually of temperature-controlled cabinet internal temperature; Use current measure device constantly to measure the leakage current at device under test drain-source two ends
When the leakage current at the device under test drain-source two ends that record equates with the electric current at the device under test drain-source two ends that recorded by step 2; Note the temperature-controlled cabinet internal temperature of this moment and with the temperature-controlled cabinet internal temperature of this moment as equivalent junction temperature, and get into step 5;
When if the temperature-controlled cabinet internal temperature is increased to the maximum junction temperature that device under test allows; Measured leakage current still is higher than the measured leakage current of step 2, then removes the square wave pulse voltage on the grid, reduces the DC voltage at device under test drain-source two ends; Return step 2
Step 4 is calculated the thermal resistance value of device under test, according to formula,
R θJA = T J - T A P H = T J - T A V ds · I ds
Wherein, T JBe the equivalent junction temperature of record in the step 3, T ABe 25 ℃ of the room temperatures that set, P HBe the power consumption of device under test, V DsBe the magnitude of voltage at device under test drain-source two ends in the step 2, I DsBe the current value at device under test drain-source two ends measured in the step 2, R θ JATie the stable state packaging thermal resistance value of environment temperature for device under test, will test the gained data and bring above-mentioned formula into, calculate the steady state thermal resistance of device under test.
CN201210059502.2A 2012-03-08 2012-03-08 Method for measuring junction temperature and thermal resistance of metal-oxide semiconductor tube CN102608511B (en)

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CN103175861A (en) * 2013-02-20 2013-06-26 中国科学院电工研究所 Junction-to-case thermal resistance testing method
CN103278761A (en) * 2013-05-19 2013-09-04 北京工业大学 Method for measuring interface temperature rise and thermal resistance of thin-layer extrinsic semiconductor material
CN103499782A (en) * 2013-08-21 2014-01-08 深圳市晶导电子有限公司 Method for measuring vertical double-diffusion MOSFET
CN103616628A (en) * 2013-11-21 2014-03-05 北京工业大学 Method and device for measuring temperature rising and heat resistance of Schottky grid field effect transistor
CN104407280A (en) * 2014-12-01 2015-03-11 苏州立瓷电子技术有限公司 Thermal resistance measuring method of LED lamp
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CN107329070A (en) * 2017-06-09 2017-11-07 常州银河电器有限公司 A kind of method of junction temperature during fast estimator part hot operation
CN107436402A (en) * 2017-08-01 2017-12-05 华北电力大学 A kind of adjusting method and regulating system of thermostat temperature
CN107621600A (en) * 2017-08-28 2018-01-23 北京工业大学 A kind of method using the reverse grid ource electric current on-line measurement junction temperature of GaN base HEMT device
CN108680779A (en) * 2018-05-18 2018-10-19 浙江欧兰顿电器科技有限公司 A kind of test method of PTC heat generating components dash current
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CN103278761B (en) * 2013-05-19 2015-08-26 北京工业大学 A kind of method measuring the material interface temperature rise of thin layer heterogeneous semiconductor and thermal resistance
CN103278761A (en) * 2013-05-19 2013-09-04 北京工业大学 Method for measuring interface temperature rise and thermal resistance of thin-layer extrinsic semiconductor material
CN103499782A (en) * 2013-08-21 2014-01-08 深圳市晶导电子有限公司 Method for measuring vertical double-diffusion MOSFET
CN103499782B (en) * 2013-08-21 2017-02-22 深圳市晶导电子有限公司 Method for measuring vertical double-diffusion MOSFET
CN103616628A (en) * 2013-11-21 2014-03-05 北京工业大学 Method and device for measuring temperature rising and heat resistance of Schottky grid field effect transistor
CN103616628B (en) * 2013-11-21 2017-03-01 北京工业大学 Schottky gate field-effect transistor temperature rise and thermal resistance measurement method and device
CN104458799A (en) * 2014-11-27 2015-03-25 天津大学 Method and device for measuring transient thermal resistance of IGBT module
CN104407280A (en) * 2014-12-01 2015-03-11 苏州立瓷电子技术有限公司 Thermal resistance measuring method of LED lamp
CN106199366A (en) * 2016-06-25 2016-12-07 北京工业大学 A kind of method of power MOS (Metal Oxide Semiconductor) device temperature measurement on-line
CN106199366B (en) * 2016-06-25 2018-11-20 北京工业大学 A kind of method of power MOS (Metal Oxide Semiconductor) device temperature measurement on-line
CN107329070A (en) * 2017-06-09 2017-11-07 常州银河电器有限公司 A kind of method of junction temperature during fast estimator part hot operation
CN107329070B (en) * 2017-06-09 2019-07-19 常州银河电器有限公司 A kind of method of junction temperature when fast estimator part hot operation
CN107436402A (en) * 2017-08-01 2017-12-05 华北电力大学 A kind of adjusting method and regulating system of thermostat temperature
CN107621600A (en) * 2017-08-28 2018-01-23 北京工业大学 A kind of method using the reverse grid ource electric current on-line measurement junction temperature of GaN base HEMT device
CN108680779A (en) * 2018-05-18 2018-10-19 浙江欧兰顿电器科技有限公司 A kind of test method of PTC heat generating components dash current
CN109164370A (en) * 2018-09-06 2019-01-08 上海交通大学 The thermal impedance measuring system and method for power semiconductor
CN111999630A (en) * 2020-10-28 2020-11-27 四川立泰电子有限公司 Method and system for testing working junction temperature of power device

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