CN110895635A - High-precision laminated chip junction temperature prediction model based on thermal resistance network - Google Patents
High-precision laminated chip junction temperature prediction model based on thermal resistance network Download PDFInfo
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Abstract
A high-precision laminated chip junction temperature prediction model based on a thermal resistance network is characterized in that the size and the thermal conductivity of each component in a chip are determined, the parameters are substituted into a corresponding thermal resistance calculation formula, and the thermal resistance value of each component is calculated; and finally, comparing the junction temperature predicted value with the simulated value to obtain a relative error between the junction temperature predicted value and the simulated value so as to verify the accuracy of the junction temperature prediction model. Aiming at the defects of low efficiency, high cost and the like of most of the original laminated chip junction temperature prediction models, the invention creatively constructs the thermal resistance network model of the laminated chip, and the thermal contact resistance of the adhesive glue and the thermal coupling effect among the chips are mainly considered in the model, thereby improving the prediction precision and the thermal design efficiency, and reducing the design cost.
Description
Technical Field
The invention relates to a high-precision laminated chip junction temperature prediction model based on a thermal resistance network, and belongs to the technical field of chip packaging.
Background
The development requirements of the current chip are as follows: more versatile, higher power chips are contained in more compact, thinner packages. The laminated chip package has the advantages of small volume, short interconnection, light weight and the like, has great potential in the aspects of improving circuit performance and improving chip integration level, and is an important packaging form meeting chip development. However, stacked chip packages still face many challenges in the fields of electrical, material processing, mechanical, and thermal. The main problems with respect to thermal challenges are reduced heat transfer paths, reduced heat dissipation space, more difficult heat transfer from the top chip to the PCB for heat dissipation, thermal coupling effects between chips, etc. With the increase of power consumption, the heat generation of the chip is increased, the junction temperature is continuously increased, and the chip is finally overheated and fails. Therefore, it becomes more and more important to predict the junction temperature of the stacked chips.
Today, the prediction of junction temperature for most stacked chips is achieved by a matrix of thermal resistances. There are two main methods for predicting the junction temperature of the chip by using the thermal resistance matrix. One method is to load the power of the chip in a standard JESD51-2 environment, obtain the junction temperature of the chip in a plurality of groups of experimental environments, then convert the junction temperature into the thermal resistance value of junction-air, finally substitute the thermal resistance value into a thermal resistance matrix to obtain a prediction model, and then obtain the junction temperature of the chip in any power combination. The method has the defects of high cost, long test time and long research and development period. The other method is that a standard simulation environment is set in ANSYS software, a model of the chip is established, corresponding material parameters are set, the junction temperature of the chip is obtained when the specified power combination is obtained through simulation, the junction temperature value is further converted into a thermal resistance value and is substituted into a thermal resistance matrix, and the junction temperature of the chip under other power combination conditions can be predicted. The disadvantage of this method is that the model of the chip is changed continuously as the sizes of the components of the chip are changed, and after the thermal resistance matrix is obtained, the matrix is linearly fitted to obtain a more accurate predicted value, so that the efficiency is reduced.
Disclosure of Invention
Aiming at the defects of complicated modeling, high cost of actual measurement and the like of most of the existing laminated chip junction temperature prediction models, the invention provides a high-precision laminated chip junction temperature prediction model based on a thermal resistance network.
A high-precision laminated chip junction temperature prediction model based on a thermal resistance network is characterized in that the size and the thermal conductivity of each component in a chip are determined, the parameters are substituted into a corresponding thermal resistance calculation formula, and the thermal resistance value of each component is calculated; and finally, comparing the junction temperature predicted value with the simulated value to obtain a relative error between the junction temperature predicted value and the simulated value so as to verify the accuracy of the junction temperature prediction model.
Furthermore, the laminated chip is composed of a multilayer bare chip, multilayer chip bonding glue, a low-temperature co-fired ceramic substrate, substrate bonding glue, a high-temperature co-fired ceramic substrate, pins, a PCB and the like.
Further, the calculation formula of the thermal resistance comprises calculation methods of conduction thermal resistance, convection heat transfer thermal resistance and contact thermal resistance, and further comprises a calculation method of thermal resistance of 45 degrees.
Further, the calculation formula of the conduction thermal resistance is as follows, and is used for calculating the thermal resistance value between the mutually laminated plates when the sizes of the laminated chips are consistent;
wherein R is1Representing the thermal conduction resistance, d representing the thickness of the flat plate, a representing the cross-sectional area of the thermal flow path, and λ representing the thermal conductivity of the material;
the calculation formula of the convective heat transfer thermal resistance is as follows, and the calculation formula is used for calculating the thermal resistance values from the upper surface of the chip at the top layer in the laminated chip and the upper surface and the lower surface of the PCB to air;
wherein R is2Representing the heat convection resistance, A representing the sectional area of a heat flow path, and h representing the heat convection coefficient;
the calculation formula of the contact thermal resistance is mainly used for calculating the thermal resistance value of each layer of bonding glue, and if the interface contact of the two materials is the contact of epoxy materials, the contact thermal resistance needs to be increased by 20%;
the '45-degree thermal resistance calculation method' is used for calculating the thermal resistance values of components such as the substrate, the base and the PCB.
Further, according to the topological relation of the thermal resistance network, the thermal resistance value from the chip to the ambient air when the chips of other layers apply power independently can be calculated.
Further, in the final junction temperature prediction model formula, the junction temperature prediction value of each layer of chips is related to the power applied to each layer of chips so as to embody the heat coupling effect among the chips.
Aiming at the defects of low efficiency, high cost and the like of most of the original laminated chip junction temperature prediction models, the invention creatively constructs the thermal resistance network model of the laminated chip, and the thermal contact resistance of the adhesive glue and the thermal coupling effect among the chips are mainly considered in the model, thereby improving the prediction precision and the thermal design efficiency, and reducing the design cost.
Drawings
Fig. 1 is a schematic diagram of an internal structure of a stacked chip in the embodiment.
Fig. 2 is a schematic diagram showing the dimensions of the components in the stacked chip and the thermal conductivity thereof in the embodiment.
FIG. 3 is a cloud graph showing the temperature distribution of the chips with 1W applied to each layer of the chips in the example.
FIG. 4 is a diagram of a stacked chip thermal resistance network in an embodiment.
Fig. 5 is a simplified diagram of a thermal resistance network in an embodiment.
FIG. 6 is a table of thermal resistance values in a model of a thermal resistance network in an example.
FIG. 7 is a comparison between predicted values of the junction temperature of the chips and simulated values when the chips of the respective layers are applied with 0.5W, 1W and 2.5W independently.
Fig. 8 is a comparison between the predicted value and the simulated value of the chip junction temperature when 0.5W, 1W and 1.5W are applied to each chip layer in the embodiment.
Detailed Description
The technical scheme of the invention is further explained in detail by combining the drawings in the specification.
A high-precision laminated chip junction temperature prediction model based on a thermal resistance network is characterized in that the size and the thermal conductivity of each component in a chip are determined, the parameters are substituted into a corresponding thermal resistance calculation formula, and the thermal resistance value of each component is calculated; and finally, comparing the junction temperature predicted value with the simulated value to obtain a relative error between the junction temperature predicted value and the simulated value so as to verify the accuracy of the junction temperature prediction model.
As shown in fig. 1, the overall structure of the stacked chip is composed of three layers of bare chips (die1, die2 and die3), three layers of chip bonding glue (adh1, adh2 and adh3), a low temperature co-fired ceramic Substrate (LTCC Substrate), a Substrate bonding glue (adh0), a high temperature co-fired ceramic Substrate (HTCC Substrate), pins (pins), and PCBs. The dimensions and material properties of the various components inside the chip are shown in fig. 2.
As shown in fig. 3, which is a cloud of temperature profiles of the chips when 1W was applied to each layer of the chips. From this it is clear that the junction temperature of the chip is 97.736 ℃, which occurs on the top chip, and the top chip and the bottom chip have a temperature gradient, with the temperature from the top chip to the bottom chip getting lower and lower. Therefore, most of the heat of the stacked chips is transferred from the top chip to the bottom chip, transferred to the PCB board through the pins, and finally dissipated to the ambient environment through the PCB. In addition, as can be seen from the figure, heat affects and couples the chips in different layers, and further increases the junction temperature of the chips again.
Fig. 4 shows a diagram of a thermal resistance network of a stacked chip. When calculating the thermal conduction resistance, there are two general cases, one is the mutual lamination of the flat plates with consistent size, and the heat transfer needs to be converted into the one-dimensional steady-state heat conduction problem. Another situation is when the heat flow passes from a chip with a narrow cross section to a substrate with a wider cross section, the heat flow spreads out at an angle of 45 ° to the material cross section. Furthermore, if the interface contact of the two materials is the contact of the epoxy material, the contact resistance is increased by 20%. The calculation methods of the conduction thermal resistance and the convection heat transfer thermal resistance can be respectively expressed as follows:
wherein R is1Denotes the conductive thermal resistance, R2The heat flow heat exchange resistance is shown, d is the thickness of the flat plate, A is the cross section area of a heat flow path, lambda is the heat conductivity of the material, and h is the convection heat exchange coefficient. The thermal resistance of the top chip transferring heat to the air by means of convection is denoted as Rdie3-air. According to the heat transfer path and the positions of heat sources in the chips of all layers, a thermal resistance network model can be obtained.
For convenience of presentation, note:
R3＝Rdie3+Radh3+Radh3 contact(3)
R2＝Rdie2+Radh2+Radh2contact(4)
R1＝Rdie1+Radh1+Radh1contact(5)
R0＝RLTCCSubstrate+Radh0+Radh0contact+RHTCCSubstrate+Rpin+(RPCB+RPCB-air1)//RPCB-air2(6)
wherein R isPCB-air1Represents the value of the thermal resistance, R, of heat dissipated into the air from the upper surface of the PCBPCB-air2Indicating the value of the thermal resistance of the heat dissipated from the lower surface of the PCB into the air, (R)PCB+RPCB-air1)//RPCB-air2The PCB has the beneficial effects that when heat flows through the PCB, a part of heat is radiated on the upper surface of the PCB, and the other part of heat is radiated on the lower surface of the PCB after passing through the PCB, and the two processes are simultaneously carried out, so that the two processes are expressed in a parallel connection mode. The heat generated by die3 in the top chip has two main heat transfer paths, so the thermal resistance (R) of die3 to airt3-air) The thermal resistances on the two paths can be obtained in parallel, and the following are recorded:
Rt3-air＝Rdie3-air//(R3+R2+R1+R0) (7)
according to the topological relation of the thermal resistance network, the thermal resistance value from the chip to the ambient air when the chips of other layers apply power independently can be calculated, and the calculation method comprises the following steps:
Rt2-air＝(Rdie3-air+R3)//(R2+R1+R0) (8)
Rt1-air＝(Rdie3-air+R3+R2)//(R1+R0) (9)
as shown in fig. 5, fig. 4 is simplified to simplify the diagram of the thermal resistance network, that is, equations (7) to (9). Wherein r is3＝Rt3-air-Rt2-air，r2＝Rt2-air-Rt1-air. The final calculation formula of the junction temperature of the chip is as follows:
T1＝Rt1-air·(P1+P2+P3)+Tair(10)
T2＝T1+r2·(P2+P3) (11)
T3＝T2+r3·P3(12)
wherein, T1，T2And T3Respectively representing junction temperature predicted values of the bottom chip, the middle chip and the top chip. P1，P2And P3The values of the power, T, applied to the bottom chip, the middle chip and the top chip, respectivelyairRepresenting the ambient temperature. Predicted value T of junction temperature1，T2And T3The heat coupling effect is reflected by the correlation with the power consumption of each layer of chip.
And (3) calculating the thermal resistance value of each layer of chip and the convective heat transfer thermal resistance values of the upper surface of the top layer chip and the upper surface and the lower surface of the PCB according to the formula (1) and the formula (2). The parts of the substrate, the substrate adhesive, the base, the PCB and the like are calculated according to a 'thermal resistance 45-degree calculation method', and in addition, all layers of adhesive are made of epoxy materials, so that the contact thermal resistance is increased by 20%. Selecting a representative component to calculate the thermal resistance value, wherein the calculation process is as follows:
Radh3contact＝0.2×Radh3＝1.386(℃/W)
the thermal resistance calculation process for the other components is similar to the above process and therefore will not be described in detail. All the thermal resistance values in the finally obtained thermal resistance network model are shown in fig. 6.
R can be obtained by the formulae (3) to (9)t1-air＝18.914(℃/W)，r2＝4.136(℃/W)，r38.348 (. degree.C./W). These values are then substituted into equations (10) to (12), and the final prediction model is obtained:
T1＝18.914·(P1+P2+P3)+Tair
T2＝T1+4.136·(P2+P3)
T3＝T2+8.348·P3
after obtaining the stacked chip junction temperature prediction model, model verification is also needed to prove the reasonability of the model. Fig. 7 represents the comparison between the predicted values of the chip junction temperature and the simulated values when 0.5W, 1W and 2.5W are applied to the chips of each layer, respectively, and fig. 8 represents the comparison between the predicted values of the chip junction temperature and the simulated values when 0.5W, 1W and 1.5W are applied to the chips of each layer.
It can be found that the relative error of the calculated value and the simulation value is at most-4.35% and not more than 4.5%, which verifies that the model has high reliability.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.
Claims (6)
1. A high-precision laminated chip junction temperature prediction model based on a thermal resistance network is characterized in that:
firstly, determining the size and the heat conductivity of each component in a chip, substituting the parameters into a corresponding heat resistance calculation formula, and calculating the heat resistance value of each component;
then substituting the thermal resistance value into a thermal resistance network to obtain junction temperature prediction models of the laminated chip under different working conditions,
and finally, comparing the predicted junction temperature value with the simulated value to obtain a relative error between the predicted junction temperature value and the simulated value so as to verify the accuracy of the junction temperature prediction model.
2. The high-precision laminated chip junction temperature prediction model based on the thermal resistance network as claimed in claim 1, wherein: the laminated chip comprises a multilayer bare chip, multilayer chip bonding glue, a low-temperature co-fired ceramic substrate, substrate bonding glue, a high-temperature co-fired ceramic substrate, pins, a PCB and the like.
3. The high-precision laminated chip junction temperature prediction model based on the thermal resistance network as claimed in claim 1, wherein: the calculation formula of the thermal resistance comprises calculation methods of conduction thermal resistance, convection heat transfer thermal resistance and contact thermal resistance, and further comprises a calculation method of 'thermal resistance 45 degrees'.
4. The high-precision laminated chip junction temperature prediction model based on the thermal resistance network as claimed in claim 3, wherein:
the conduction thermal resistance calculation formula is as follows, and is used for calculating the thermal resistance value between the mutually laminated plates when the sizes of the laminated chips are consistent;
wherein R is1Representing the thermal conduction resistance, d representing the thickness of the flat plate, a representing the cross-sectional area of the thermal flow path, and λ representing the thermal conductivity of the material;
the calculation formula of the convective heat transfer thermal resistance is as follows, and the calculation formula is used for calculating the thermal resistance values from the upper surface of the chip at the top layer in the laminated chip and the upper surface and the lower surface of the PCB to air;
wherein R is2Representing the heat convection resistance, A representing the sectional area of a heat flow path, and h representing the heat convection coefficient;
the calculation formula of the contact thermal resistance is mainly used for calculating the thermal resistance value of each layer of bonding glue, and if the interface contact of the two materials is the contact of epoxy materials, the contact thermal resistance needs to be increased by 20%;
the '45-degree thermal resistance calculation method' is used for calculating the thermal resistance values of components such as the substrate, the base and the PCB.
5. The high-precision laminated chip junction temperature prediction model based on the thermal resistance network as claimed in claim 1, wherein: according to the topological relation of the thermal resistance network, the thermal resistance value from the chip to the ambient air when the chips of other layers apply power independently can be calculated.
6. The high-precision laminated chip junction temperature prediction model based on the thermal resistance network as claimed in claim 1, wherein: in the final junction temperature prediction model formula, the junction temperature predicted value of each layer of chips is related to the power applied to each layer of chips so as to embody the heat coupling effect among the chips.
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| CN117556780A (en) * | 2023-11-15 | 2024-02-13 | 广州番禺职业技术学院 | Thermal resistance analysis method for each average junction temperature of MCM-QFN package |
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| CN117556780A (en) * | 2023-11-15 | 2024-02-13 | 广州番禺职业技术学院 | Thermal resistance analysis method for each average junction temperature of MCM-QFN package |
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