CN1006506B - 集成电路制造方法 - Google Patents

集成电路制造方法

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CN1006506B
CN1006506B CN87106114A CN87106114A CN1006506B CN 1006506 B CN1006506 B CN 1006506B CN 87106114 A CN87106114 A CN 87106114A CN 87106114 A CN87106114 A CN 87106114A CN 1006506 B CN1006506 B CN 1006506B
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彼得·L·特里蒙特
亚瑟·J·阿克曼
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Monsanto Co
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Abstract

一种在硅片上有多层制有图形的薄膜材料层的集成电路制造方法。在每次蚀刻之后，用含至少0.01ppm最好0.02到0.09ppm臭氧的净水溶液漂洗，基片是处于所产生的各层之间。

Description

本发明涉及制造集成电路和半导体材料的新的方法，更特别地，涉及试图提供高产品合格率的新的处理方法。
在集成电路例如超大规模集成电路的生产中，一个基本点是构成的材料和电路须与污染物分离，在生产硅片和制造电路中所需的多个步骤不可避免地会有污染，除非采用有效的预防措施和步骤。
在已有的制造硅基片的过程中，首先生长硅晶体，晶体被按规格修切，接着磨成一圆柱体。该圆柱体被切成薄的切片（即硅片），其厚度根据圆柱体的直径而定。这些硅片接着被磨平，腐蚀成形，并首次清洗。它们接着被蚀刻以达到平整并且除去缺陷，然后再清洗，抛光，蚀刻和清洗。在后一清洗过程中，用过氧化氢溶液以提供一薄的氧化物层（例如大约25到30A），该元件再用纯化水漂洗。以后，硅片以无菌形式包装并传送供电路制造。
电路的制造是复杂的过程，它需要多个步骤，其中薄膜材料成层在硅片上。在制造过程中，硅片表面的裸露部分被暴露出来。这些被暴露的区域成为电路的关键功能部分，如果暴露的硅被以任何形式污染的话，它可能使将来的电路失效，这种失效只有到该电路被测试时才能检测到。例如，不仅在裸硅和其上氧化物层间存在关键界面（ritical    interface），在硅氧化物和多晶层之间，以及许多其它界面间存在关键界面。因此使裸硅和界面免受沾污是十分重要的。
有些沾污较之于其他沾污来说，对于电路元件的功能度具有更大的消极影响，总的来说，该影响可被解释为光刻颗粒堵塞（lithographically    blocking）或化学污染。最小特征尺寸的10%到 30%的不透光的微粒能有效改变电路元件的功能特性。这是因为它们改变了印刷复制过程。如果它们改变了接近前表面的硅的化学性质，或者沉积在硅片上的膜的化学成份，即使是更小的微粒也会降低成品率。最大的问题是涉及用作栅单元的氧化物或用作栅电极或接点上的多晶硅沉积物的质量的降低。这些污染问题并不会立即引起功能失效和片子合格率的降低，但是在片子供给顾客以后会出现诸如氧化物或接点的可靠性问题。
在电路的制造过程中，一般用去电离子水清洗基片，包括清洗裸硅，和在器件的制备过程中清洗材料界面。
硅片和整个集成电路处理工艺是与氧化物相容的。所以，本发明的一个目的是，在制造集成电路过程中，以这样的方式处理硅片，使在裸硅上具有尽可能最清洁的氧化物层，并且对于所加的下一层最易接受。
本发明的另一个目的是提供一种生产集成电路的方法，其中在关键界暴露期间，基片被处理以最大限度地减少界面上的问题并提供更高的合格率。
本发明的其他目的将从下列描述中可明显看出。
我们已经发现，在硅片上制造集成电路的过程中，用含有至少0.01ppm的臭氧的纯化水来对基片漂洗以清洁硅裸表面和电路结构的各界面是有益的，我们已经发现这种处理可通过最大限度减小有机物的附着力来使污染减至最小，并使包括细菌颗粒的散粒的附着力减至最小。
根据本发明，提供了一种制造集成电路的方法，其中在半导体基片上有多层制有图形的薄膜材料层，其方法包括下列步骤：在半导体基片表面上涂覆一层材料;在该层材料上涂一层光致抗蚀剂;使光致抗蚀剂曝光以改变其特性;除去一部分光致抗蚀剂以提供该材料层的 暴露部分;除去该暴露部分的材料层，接着用含有至少0.01ppm臭氧的纯化水溶液进行漂洗。
在所述实施例中，在除去部分光致抗蚀剂和除去暴露部分的材料层的步骤之间，该电路板同样也用含有至少0.01ppm臭氧的纯化水溶液处理。
在所述实施例中，纯化水溶液最好含有0.02到0.09ppm臭氧。所述半导体基片材料是硅，但该方法同样也可适用于在砷化镓材料上制备集成电路。
本发明的更详细的说明如下列说明和权利要求所提供，并可参见附图所示。
图1是根据本发明的用于提供在硅基片上制备集成电路用的臭氧水的水处理方法的方框图;
图2A-2N表示在电路制备过程中硅片的剖视图。
根据本发明，在电路制造过程中，用臭氧和去离子的纯化水处理基片，以清洗硅的裸表面和电路构成中的各层交界面。图1示出了提供臭氧化、去离子纯化水的系统。参见附图1，原水被多介质过滤器和包含化学填充剂的预处理级10进行预处理。接着通过泵12把它抽到反渗透装置14并且通过脱气器16脱气（如果需要的话），再通过加压泵18抽到包含阴床、阳床和混合床或只具有混合床的去盐级20中。
为了取代反渗透装置，脱气装置16，加压泵18和包含阴床、阳床和混合床或只具有混合床的去盐器20，可用如皮特内的美国专利第4，574，049所揭示的双向反渗透系统。
去盐水流到去离子水存贮箱22中，它通过泵24加压，并送到包含混合床（典型的是阴阳树脂的组合）的抛光去离子交换瓶26（即混合床）中。来自混合床26的去离子水通过后置过滤器28过滤，接着通过紫外线灯30处理以控制细菌，再经亚微米级过滤装置32，后置过滤器 被用作树脂收集器。去离子纯化水通过导管34送到定压气体注入机36中。
去离子纯化水被进行如下所述的臭氧化处理。纯氧气通过能产生压力在10磅/平方英寸左右的氧气加臭氧的常用臭氧发生器38送入，具有约10磅/平方英寸压力的氧气和臭氧被送入压缩机40，其中气体被加压至85磅/平方英寸，以后被送入定压气体注入机36。被压缩的氧气和臭氧在定压气体注入机36中与纯化水混合以形成臭氧化的水并通过导管42提供臭氧化的水。用泄漏管44去掉臭氧化水管中的气泡。
导管中的去离子的、臭氧化的纯化水通过PVDF管道系统送到电路制造地。臭氧溶解表46用以监测臭氧浓度。我们已经发现在去离子纯化水中的臭氧浓度最好是在0.01到0.1ppm，以使在电路制造期间基片处于适当环境并防止对系统硬件有重大损伤。我们发现最佳的臭氧浓度在0.02到0.09ppm之间。
去离子的、臭氧化的纯化水是循环的，但是臭氧必须在水回到去离子水的存贮箱22以前去除。为此，臭氧化水用紫外线灯48处理以使去除臭氧并循环。去除臭氧后的去离子纯化水，经导管50通过背压调节器52送到去离子的水存贮箱22中。
图2A-2N说明了在得到了清洁的硅基片后集成电路的制造方法的一部分。图2A说明了从基片制造者处得到的覆盖有化学方法生长的一氧化层62的硅基片60或者从先期的过氧化氢处理得到的硅基片，其上氧化物一般具有20埃到30埃的厚度。通常电路制造者要除去该氧化物以重新清洗硅。另一方面，图2A中有氧化物层的硅可被置于炉中，在炉中它被氧化以产生具有厚度在100埃到400埃的热生长的氧化物64（图2B）。以后，在炉中形成氮化硅上层66（图2c），并且光致抗蚀层68位于氮化硅层之上。
光致抗蚀层68被光照，接着蚀刻（图2E所示）留下氮化硅的暴 露部分。接着，图2E所示的片子用含有0.01到0.1ppm，最好是0.02～0.09ppm臭氧浓度的去离子纯化水进行漂洗处理。
在上述漂洗后，不再被光致抗蚀剂68所覆盖的氮化硅66被蚀刻导致如图2F的片子，其中，光致抗蚀剂被除去并且氧化物64的部分被暴露。该片子再一次被用臭氧化水漂洗处理以后，片子被置于炉中以在氮化物被去除的地方生长厚度约为2，000埃的厚膜氧化物70，如图2G所示。以后，该片子被以臭氧水漂洗处理，氮化硅66被去除（见图2H）。该片子再被臭氧水漂洗，以后加上光致抗蚀层68（见图2I），辐照以后蚀刻（见图2I）。如图2J所示，它留下了裸露的氧化物部分，该片再一次被臭氧水漂洗处理。如图2K所示，在硅的表面上不同区域，光致抗蚀层被去除，氧化物被向下蚀刻至硅裸露，以后，如图2L所示，栅氧化物72被热生长出来，该栅氧化物厚度为150埃到300埃范围内，厚度的公差精度很高。该栅氧化物在整个集成电路制造过程中一般是最关键的氧化物，所以适当处理用于生长栅的裸硅是绝对重要的。为此，臭氧水漂洗和处理裸硅并产生一层薄的氧化层，约几个单分子层以接受栅氧化物。
在如图2L所示的栅生长以后，参见图2M，沉积了一多晶硅层74。在多晶硅沉积以后，产生另一层光致抗蚀层68，它被光照，蚀刻，用臭氧水漂洗，接着暴露的多晶硅层被蚀刻并被臭氧水漂洗，以导致如图2N所示的片子。
在电路制造过程中，还有许多其它的成层的步骤。根据本发明，典型的是提供一光致抗蚀层，它被光照，蚀刻，其剩余物被臭氧水漂洗，接着，不在光致抗蚀剂下面的材料蚀刻以后被臭氧水漂洗。
尽管当光致抗蚀层被去除时须用臭氧化水漂洗，但最主要的一点是，在没有被光致抗蚀剂覆盖的材料被蚀刻后再用臭氧水进行处理。这样，在产生上层材料以前，最主要的是用含有0.01到0.1ppm，最好 是0.02到0.09ppm臭氧浓度的去离纯化水进行漂洗处理。
我们已经发现用上面所说的臭氧水处理通过用超纯试剂控制界面的氧化从而提高了电路制造工艺，通过最大限度地减小有机物和颗粒（包括细菌颗粒）的附着力而使污染减至最小。其中只存在极少量的颗粒，这是因为将非常清洁的气体被注入到超纯化水中。注入到水中的臭氧的纯度比电路制作中的已有技术处理系统所用的化学物质的纯度高。
尽管已对所述实施例进行说明，但可以理解到对于本领域技术人员来说，在不超出本发明的精神和范围以内，还可有各种变形和替换。

Claims (12)

1、一种制造集成电路的方法，其特征在于在半导体基片上有多层制有图形的薄膜材料层，其步骤包括：
在半导体基片表面上覆一材料层；
在所述材料层上提供一光致抗蚀剂层；
使光致抗蚀剂曝光以改变其特性；
除去光致抗蚀剂一部分以提供材料层的暴露部分；
除去所述材料层的暴露部分；以及
用含至少0.01ppm臭氧的纯化水溶液漂洗该片子表面以在其上形成薄氧化物层。
2、如权利要求1所述的方法，其特征在于在去除部分光致抗蚀剂和去除材料层的暴露部分的步骤间，有一个用含0.01ppm臭氧的纯化水溶液漂洗该片的处理步骤。
3、如权利要求1所述的方法，其特征在于所述纯化水溶液含有0.02到0.09ppm臭氧。
4、如权利要求1所述的方法，其特征在于所述材料层的厚度为20到400埃。
5、如权利要求1所述的方法，其特征在于所述材料层包括氮化硅。
6、如权利要求1所述的方法，其特征在于所述材料层包括厚膜氧化物。
7、如权利要求1所述的方法，其特征在于所述半导体基片材料是硅，并且当材料层的暴露部分被去除时，先暴露出裸硅，再通过用含有臭氧的纯化水漂洗处理片子以在裸硅上形成一薄氧化物层。
8、如权利要求1所述的方法，其特征在于，在处理步骤以后还包括下列步骤：
在已处理的基片上提供第二材料层;
在所述第二材料层上提供光致抗蚀层;
使所述光致抗蚀剂暴光以改变其特性;
去除部分光致抗蚀剂以提供暴露的第二材料层部分;
去除所述第二材料层的暴露部分;以及
用含有至少0.01ppm臭氧的纯化水溶液漂洗该片。
9、一种制造集成电路的方法，其特征在于，在硅基片上有多层制有图形的薄膜材料层，其步骤包括：
在硅基片表面上覆一材料层;
在所述材料层上提供光致抗蚀层;
使光致抗蚀剂曝光以改变其特性;
去除部分光致抗蚀剂以提供暴露的材料层部分;
用含0.02～0.09ppm臭氧的纯化水溶液对其进行漂洗处理;
去除材料层的暴露部分的暴露裸硅;
用含0.02～0.09ppm臭氧的纯化水溶液漂洗处理裸硅以在其上形成一薄氧化物层。
10、如权利要求9所述的方法，其特征在于，在处理裸硅的步骤以后还包含下列步骤：
在所述处理后的基片上提供第二材料层;
在所述第二材料层上提供光致抗蚀层;
使光致抗蚀剂曝光以改变其特性;
去除部分光致抗蚀剂以暴露部分第二材料层;
去除第二材料层的暴露部分;以及
用含0.02到0.09ppm臭氧的纯化水溶液漂洗处理该片。
11、一种制造集成电路的方法，其特征在于在半导体基片上有多层制有图形的薄膜材料层，其步骤包括;
在半导体基片表面覆上材料层;覆上光致抗蚀剂层;
除去光致抗蚀剂层选出的部分;
在材料涂覆步骤之间，从基片表面去除部分材料;
以材料涂覆步骤以前，用含有至少为0.01ppm臭氧的纯化水溶液漂洗该片表面以在其上形成一薄氧化物层。
12、如权利要求11所述的方法，其特征在于所述纯化水溶液含0.02到0.09ppm臭氧。
CN87106114A 1986-09-02 1987-09-01 集成电路制造方法 Expired CN1006506B (zh)

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US06/903,022 US4749640A (en) 1986-09-02 1986-09-02 Integrated circuit manufacturing process

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NO873670L (no) 1988-03-03
KR880004543A (ko) 1988-06-04
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EP0259985A3 (en) 1990-05-30
CN87106114A (zh) 1988-05-04
US4749640A (en) 1988-06-07
DK423587D0 (da) 1987-08-13
NO873670D0 (no) 1987-09-01
CA1264870A (en) 1990-01-23
AU7683387A (en) 1988-03-10
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IN171016B (zh) 1992-07-04

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