CN100592479C - 具有最优化应力效应的双沟槽的晶体管结构及其形成方法 - Google Patents

具有最优化应力效应的双沟槽的晶体管结构及其形成方法 Download PDF

Info

Publication number
CN100592479C
CN100592479C CN200580034575A CN200580034575A CN100592479C CN 100592479 C CN100592479 C CN 100592479C CN 200580034575 A CN200580034575 A CN 200580034575A CN 200580034575 A CN200580034575 A CN 200580034575A CN 100592479 C CN100592479 C CN 100592479C
Authority
CN
China
Prior art keywords
stress
trench
transistor structure
semiconductor
feature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200580034575A
Other languages
English (en)
Chinese (zh)
Other versions
CN101124668A (zh
Inventor
陈建
迈克尔·D·特纳
詹姆斯·E·瓦谢克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN101124668A publication Critical patent/CN101124668A/zh
Application granted granted Critical
Publication of CN100592479C publication Critical patent/CN100592479C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
CN200580034575A 2004-10-29 2005-10-25 具有最优化应力效应的双沟槽的晶体管结构及其形成方法 Expired - Fee Related CN100592479C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/977,266 2004-10-29
US10/977,266 US7276406B2 (en) 2004-10-29 2004-10-29 Transistor structure with dual trench for optimized stress effect and method therefor

Publications (2)

Publication Number Publication Date
CN101124668A CN101124668A (zh) 2008-02-13
CN100592479C true CN100592479C (zh) 2010-02-24

Family

ID=36260826

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200580034575A Expired - Fee Related CN100592479C (zh) 2004-10-29 2005-10-25 具有最优化应力效应的双沟槽的晶体管结构及其形成方法

Country Status (6)

Country Link
US (1) US7276406B2 (https=)
JP (1) JP2008519434A (https=)
KR (1) KR20070069184A (https=)
CN (1) CN100592479C (https=)
TW (1) TWI433264B (https=)
WO (1) WO2006050051A2 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7670895B2 (en) 2006-04-24 2010-03-02 Freescale Semiconductor, Inc Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer
US7491622B2 (en) 2006-04-24 2009-02-17 Freescale Semiconductor, Inc. Process of forming an electronic device including a layer formed using an inductively coupled plasma
US7528078B2 (en) 2006-05-12 2009-05-05 Freescale Semiconductor, Inc. Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer
JP2007329295A (ja) * 2006-06-08 2007-12-20 Hitachi Ltd 半導体及びその製造方法
DE102006046377A1 (de) * 2006-09-29 2008-04-03 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit Isoliergräben, die unterschiedliche Arten an Verformung hervorrufen
WO2008042144A2 (en) * 2006-09-29 2008-04-10 Advanced Micro Devices, Inc. A semiconductor device comprising isolation trenches inducing different types of strain
US7829407B2 (en) 2006-11-20 2010-11-09 International Business Machines Corporation Method of fabricating a stressed MOSFET by bending SOI region
US7737498B2 (en) * 2008-05-07 2010-06-15 International Business Machines Corporation Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices
US8084822B2 (en) * 2009-09-30 2011-12-27 International Business Machines Corporation Enhanced stress-retention fin-FET devices and methods of fabricating enhanced stress retention fin-FET devices
US20110084324A1 (en) * 2009-10-09 2011-04-14 Texas Instruments Incorporated Radiation hardened mos devices and methods of fabrication
US8460981B2 (en) 2010-09-28 2013-06-11 International Business Machines Corporation Use of contacts to create differential stresses on devices
US8815671B2 (en) 2010-09-28 2014-08-26 International Business Machines Corporation Use of contacts to create differential stresses on devices
CN102446971A (zh) * 2011-09-08 2012-05-09 上海华力微电子有限公司 一种提高晶体管载流子迁移率的pmos结构
TWI565070B (zh) * 2013-04-01 2017-01-01 旺宏電子股份有限公司 半導體結構
US10801833B2 (en) * 2018-04-09 2020-10-13 The Boeing Company Strain sensitive surfaces for aircraft structural analysis and health monitoring
CN114496903B (zh) * 2022-02-10 2026-02-10 锐立平芯微电子(广州)有限责任公司 一种半导体结构及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482715B2 (en) * 2000-12-16 2002-11-19 Samsung Electronics Co., Ltd. Method of forming shallow trench isolation layer in semiconductor device
CN1469443A (zh) * 2002-06-27 2004-01-21 �뵼��Ԫ����ҵ�������ι�˾ 给出具有高沟道密度的半导体器件的低成本方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691230A (en) * 1996-09-04 1997-11-25 Micron Technology, Inc. Technique for producing small islands of silicon on insulator
US6524929B1 (en) * 2001-02-26 2003-02-25 Advanced Micro Devices, Inc. Method for shallow trench isolation using passivation material for trench bottom liner

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482715B2 (en) * 2000-12-16 2002-11-19 Samsung Electronics Co., Ltd. Method of forming shallow trench isolation layer in semiconductor device
CN1469443A (zh) * 2002-06-27 2004-01-21 �뵼��Ԫ����ҵ�������ι�˾ 给出具有高沟道密度的半导体器件的低成本方法

Also Published As

Publication number Publication date
US20060091461A1 (en) 2006-05-04
TW200627582A (en) 2006-08-01
KR20070069184A (ko) 2007-07-02
CN101124668A (zh) 2008-02-13
WO2006050051A2 (en) 2006-05-11
WO2006050051A3 (en) 2007-04-26
US7276406B2 (en) 2007-10-02
JP2008519434A (ja) 2008-06-05
TWI433264B (zh) 2014-04-01

Similar Documents

Publication Publication Date Title
CN100592479C (zh) 具有最优化应力效应的双沟槽的晶体管结构及其形成方法
JP5039901B2 (ja) 歪みシリコンオンインシュレータ構造を製造する方法およびそれによって形成された歪みシリコンオンインシュレータ構造
US8232180B2 (en) Manufacturing method of semiconductor device comprising active region divided by STI element isolation structure
CN101300664B (zh) 藉由使用包含具有高共价半径的原子的嵌入半导体层的用于硅基晶体管中工程应变的技术
US8609510B1 (en) Replacement metal gate diffusion break formation
US7393730B2 (en) Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same
JP4896789B2 (ja) 半導体装置の製造方法
US8368170B2 (en) Reducing device performance drift caused by large spacings between active regions
JP2010510676A (ja) 半導体構造体及び該半導体構造体を製造する方法
TW200539381A (en) Semiconductor manufacturing method and semiconductor device
CN1959959B (zh) 使用应变硅用于集成pmos和nmos晶体管的单掩模设计方法和结构
CN101772839A (zh) 具有金属栅极和高k电介质的电路结构
KR20090012573A (ko) 반도체 소자 및 그 제조 방법
TW200840038A (en) Electronic device including insulating layers having different strains and a process for forming the electronic device
US7541259B2 (en) Semiconductor device having a compressed device isolation structure
US7737466B1 (en) Semiconductor device and manufacturing method thereof
CN100495706C (zh) 半导体器件及其制造方法
US20090090974A1 (en) Dual stress liner structure having substantially planar interface between liners and related method
JP4029884B2 (ja) 半導体装置の製造方法
CN100421262C (zh) 半导体元件
JP5454130B2 (ja) 半導体およびその製造方法
US7288447B2 (en) Semiconductor device having trench isolation for differential stress and method therefor
JP2010141102A (ja) 半導体装置およびその製造方法
KR100497672B1 (ko) 자기 배열 에스오아이 더블 게이트 트랜지스터를 이용한디램 및 이의 제조방법
KR100827531B1 (ko) 반도체 소자 및 그 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100224

Termination date: 20171025

CF01 Termination of patent right due to non-payment of annual fee