CN100580938C - Active part array base plate and LCD panel - Google Patents
Active part array base plate and LCD panel Download PDFInfo
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- CN100580938C CN100580938C CN200810086306A CN200810086306A CN100580938C CN 100580938 C CN100580938 C CN 100580938C CN 200810086306 A CN200810086306 A CN 200810086306A CN 200810086306 A CN200810086306 A CN 200810086306A CN 100580938 C CN100580938 C CN 100580938C
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Abstract
An active element array base plate and a liquid crystal display panel. The active element array base plate includes a base plate, an array of pixel and at least one gasket. The base plate has a display area and a periphery circuit area which is adjacent to the display area. The array of pixel disposes in the display area on the base plate. The gasket disposes around the periphery circuit area on the base plate and has at least one transparent area as well as an interlamination conducting area; the gasket includes a first conducting layer, a dielectric layer, an electrode layer and a protective layer. The first conducting layer disposes on the base plate and has a first opening at the transparent area. The dielectric layer covers the first conducting layer and has a second opening in the interlamination conducting area. The electrode layer covers the dielectric layer, and the electrode layer electrically connects to the first conducting layer through the second opening. The protective layer covers the electrode layer of the interlamination conducting area exposing the electrode layer of the transparent area. The invention can effectively avoid the corrosion, ensure that the gasket has both the transparent and conducting characteristic, and it is compatible with the prior art without extra cost of manufacture.
Description
Technical field
The present invention relates to a kind of production method of pixel structure, and be particularly related to and a kind ofly use less photo-marsk process (photolithography and etching process PEP) makes the production method of pixel structure with chromatic filter layer.
Background technology
Because the demand of display grows with each passing day, so industry drops in the exploitation of related display with all strength.Wherein, (Cathode Ray Tube CRT) again because of having excellent display quality and technology maturation, therefore monopolizes the monitor market to cathode ray tube all the year round.Yet, recently the rise of environmental protection notion, since the cathode ray tube energy resource consumption big with produce the bigger characteristic of amount of radiation, add that product flattening space is limited, therefore can't satisfy the market trend of light, thin, short, little on the market, U.S. and low consumpting power.Therefore, (Thin Film Transistor Liquid Crystal Display TFT-LCD) becomes the main flow in market gradually to have the Thin Film Transistor-LCD of high image quality, high spatial utilization ratio, low consumpting power, advantageous characteristic such as radiationless.
Fig. 1 is the generalized section of traditional display panels.Please refer to Fig. 1, traditional display panels 100 comprises active elements array substrates 110, subtend substrate 120, liquid crystal layer 130 and glue frame 140, wherein liquid crystal layer 130 and glue frame 140 are disposed between active elements array substrates 110 and the subtend substrate 120, and glue frame 140 is around liquid crystal layer 130.In addition, subtend substrate 120 has the common electrode 122 towards active elements array substrates 110, and active elements array substrates 110 has a plurality of joint sheets 112.
In addition, the glue frame 140 that is positioned at joint sheet 112 tops in traditional display panels 100 has conductive characteristic usually, makes that the glue frame 140 between these joint sheets 112 and common electrode 122 is able to both are electrically connected.Because common electrode 122 is electrically connected on the active elements array substrates 110 by these joint sheets 112 and glue frame 140, therefore by being positioned at the chip for driving (not shown) on the active elements array substrates 110, common voltage can be inputed in the common electrode 122 of subtend substrate 120.
It should be noted that glue frame 140 ultraviolet cured adhesive normally, in fact with conductive characteristic; after being coated in glue frame 140 between active elements array substrates 110 and the subtend substrate 120; usually can utilize the mode of irradiation, impel 140 sclerosis of glue frame, thereby form the glue frame 140 of solid phase kenel.In other words, the design of joint sheet 112 must have the function of irradiation and conduction concurrently.
Generally speaking, traditional joint sheet 112 adopts the electrode layer of indium tin oxide as the top layer usually, utilizes the direct conductive layer that covers in order to conducted signal of this electrode layer.Yet the electrode layer on top layer can't envelope conductive layer usually fully on technology, makes conductive layer under the electrode layer be easy to generate hole and contact with the external world, thereby produce the phenomenon of corroding, and causes the display abnormality of display panels.For example, electrode layer produces hole and exposes beneath conductive layer in common meeting after the film forming in film, and perhaps the film forming thickness of electrode layer is crossed thin and can't be covered conductive layer fully on the surface with gradient fluctuating.Therefore, how to allow joint sheet avoid the phenomenon of corroding and have the function of printing opacity and conduction concurrently, become a big problem of joint sheet.
Summary of the invention
The invention provides a kind of active elements array substrates, it has the joint sheet that can effectively avoid etching problem.
The invention provides a kind of display panels, it has the joint sheet that can effectively avoid etching problem.
The present invention proposes a kind of active elements array substrates, and this active elements array substrates comprises substrate, pel array and at least one joint sheet.Substrate have the viewing area and with the periphery circuit region of viewing area adjacency.In the viewing area of pixel array configuration on substrate.In the periphery circuit region of bond pad arrangement on substrate, joint sheet has at least one transparent area and at least one interlayer conducting region, and joint sheet comprises first conductive layer, dielectric layer, electrode layer and protective layer.Wherein, first conductive layer is disposed on the substrate, and has first opening at transparent area.Dielectric layer covers first conductive layer, and has second opening in the interlayer conducting region.Electrode layer covers dielectric layer, and electrode layer electrically connects by second opening and first conductive layer.The electrode layer of conducting region between the protective layer cover layer, and expose the electrode layer of transparent area.
The present invention proposes a kind of display panels, and this display panels comprises active elements array substrates, subtend substrate, glue frame and liquid crystal layer.Wherein, active elements array substrates comprises substrate, pel array, a plurality of joint sheet.Substrate have the viewing area and with the periphery circuit region of viewing area adjacency.In the viewing area of pixel array configuration on substrate.In the periphery circuit region of bond pad arrangement on substrate, each joint sheet has at least one transparent area and at least one interlayer conducting region, and each joint sheet comprises first conductive layer, dielectric layer, electrode layer and protective layer.Wherein, first conductive layer is disposed on the substrate, and first conductive layer has first opening at transparent area.Dielectric layer covers first conductive layer, and dielectric layer has second opening in the interlayer conducting region.Electrode layer covers dielectric layer, and electrode layer electrically connects by second opening and first conductive layer.The electrode layer of conducting region between the protective layer cover layer, and expose the electrode layer of transparent area.The subtend substrate has common electrode.The glue frame is between common electrode and active elements array substrates, and the glue frame is positioned at joint sheet top, and common electrode is via the electrode layer electric connection that is exposed on glue frame and the joint sheet.Liquid crystal layer is disposed in the space that active elements array substrates, subtend substrate and glue frame crossed.
In one embodiment of the invention, engage to pay somebody's debt and expect repayment later and comprise the electrode layer that is disposed at the interlayer conducting region and second conductive layer between first conductive layer, so that electrode layer is connected with first conductive layer via second conductive layer in the interlayer conducting region.
In one embodiment of the invention, when the number of the transparent area of each joint sheet and interlayer conducting region was respectively a plurality of, transparent area and interlayer conducting region were arrayed each other in fact.In one embodiment, the interlayer conducting region is positioned at first row and first row of each joint sheet, and transparent area is arrayed corresponding to the interlayer conducting region.
In one embodiment of the invention, protective layer for example is siliceous insulating barrier.In another embodiment, protective layer for example is an organic insulator.
In one embodiment of the invention, pel array comprises a plurality of pixel cells, and wherein each pixel cell comprises thin-film transistor and pixel electrode.Thin-film transistor has grid, source electrode and drain electrode.Pixel electrode is disposed in the part drain electrode, and pixel electrode directly contacts with drain electrode.
The present invention proposes a kind of active elements array substrates in addition, and this active elements array substrates comprises substrate, pel array and at least one joint sheet.Substrate have the viewing area and with the periphery circuit region of viewing area adjacency.In the viewing area of pixel array configuration on substrate.In the periphery circuit region of bond pad arrangement on substrate, joint sheet has at least one transparent area and at least one interlayer conducting region, and joint sheet comprises first conductive layer, second conductive layer, dielectric layer, electrode layer and protective layer.First conductive layer is disposed on the substrate.Second conductive layer is positioned on first conductive layer and with first conductive layer and electrically connects.Dielectric layer covers first conductive layer.Electrode layer covers second conductive layer, and electrically connects by second conductive layer and first conductive layer.Protective layer is positioned on the electrode layer and covers second conductive layer substantially.
In one embodiment of the invention, first conductive layer has first opening at transparent area, and dielectric layer is by first opening and substrate contacts.
In one embodiment of the invention, dielectric layer has second opening in the interlayer conducting region, and second conductive layer electrically connects by second opening and first conductive layer.
In one embodiment of the invention, protective layer is siliceous insulating barrier.
The present invention proposes a kind of display panels in addition, comprises above-mentioned active elements array substrates, subtend substrate and glue frame.The subtend substrate has common electrode.The glue frame is between common electrode and active elements array substrates and be positioned at transparent area substantially, and common electrode electrically connects via the electrode layer that is exposed on glue frame and the joint sheet.Liquid crystal layer is disposed in the space that active elements array substrates, subtend substrate and glue frame crossed.
In one embodiment of the invention, the material of electrode layer is transparent.
The present invention utilizes first conductive layer of conducting region between protective layer and electrode layer cover layer; and utilize electrode layer and dielectric layer to cover first conductive layer of transparent area; therefore compare with traditional joint sheet; can effectively avoid first conductive layer to produce the phenomenon of corrosion, guarantee that joint sheet has the element characteristic of printing opacity and conduction concurrently.And joint sheet in active elements array substrates of the present invention and the display panels and existing process compatible do not need extra cost of manufacture.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the generalized section of traditional display panels.
Fig. 2 is the schematic diagram of the active elements array substrates in the first embodiment of the present invention.
Fig. 3 A is the generalized section of a kind of joint sheet in the first embodiment of the present invention.
Fig. 3 B is the another kind of joint sheet in the second embodiment of the present invention and the generalized section of pixel cell.
Fig. 4 is the schematic top plan view of a kind of joint sheet in the second embodiment of the present invention.
Fig. 5 is the generalized section of a kind of display panels of third embodiment of the invention.
Wherein, description of reference numerals is as follows:
100,400: display panels
110,200,410: active elements array substrates
120,420: the subtend substrate
130,440: liquid crystal layer
140,430: the glue frame
122,422: common electrode
112,230,330,450: joint sheet
210: substrate
210D: viewing area
210P: periphery circuit region
220: pel array
240: thin-film transistor
250: pixel cell
260: the first conductive layers
270: the second conductive layers
280: dielectric layer
290: electrode layer
292: protective layer
460: the external voltage source
A: transparent area
B: interlayer conducting region
D: drain electrode
G: grid
GI: gate insulation layer
H1: first opening
H2: second opening
P: pixel electrode
S: source electrode
Vcom: common voltage
Embodiment
First embodiment
Fig. 2 is the schematic diagram of the active elements array substrates in the first embodiment of the present invention.Please refer to Fig. 2, active elements array substrates 200 comprises substrate 210, pel array 220 and at least one joint sheet 230.Wherein, substrate 210 have viewing area 210D and with the periphery circuit region 210P of viewing area 210D adjacency, periphery circuit region 210P is substantially around viewing area 210D.Pel array 220 is disposed on the substrate 210 and is arranged in viewing area 210D, and 230 of joint sheets are disposed on the substrate 210 and are arranged in periphery circuit region 210P.In addition, in the present embodiment, pel array 220 for example is made up of a plurality of pixel cells 250, and wherein each pixel cell 250 comprises thin-film transistor 240 and pixel electrode P, and thin-film transistor 240 has grid G, source S and drain D.Pixel electrode P is disposed on the part drain D, and pixel electrode P directly contacts with drain D.
Fig. 3 A is the generalized section of a kind of joint sheet in the first embodiment of the present invention.Please refer to Fig. 3 A, joint sheet 230 has at least one transparent area A and at least one interlayer conducting region B, and joint sheet 230 mainly is made up of first conductive layer 260, dielectric layer 280, electrode layer 290 and protective layer 292.As shown in Figure 3A, first conductive layer 260 is positioned on the substrate 210, wherein first conductive layer 260 for example is made up of aluminium (Al), molybdenum (Mo), titanium (Ti), neodymium (Nd), its lamination or above-mentioned light tight materials such as alloy, first conductive layer 260 has the first opening H1 at transparent area A, can be so that light penetration is positioned at the rete of transparent area A by the first opening H1.In addition; dielectric layer 280 covers first conductive layer 260; and in interlayer conducting region B, has the second opening H2; this dielectric layer 280 has protection lower floor first conductive layer 260 and avoids the function that outside air or aqueous vapor etc. are invaded, and wherein the material of dielectric layer 280 for example is dielectric materials such as silica, silicon nitride or silicon oxynitride.
Please continue A with reference to Fig. 3, covers electrode layer 290 on dielectric layer 280, this electrode layer 290 electrically connects by the second opening H2 and first conductive layer 260, wherein the material of electrode layer 290 is used indium tin oxide or indium-zinc oxide usually, certainly electrode layer 290 also can be conducting metal or other electric conducting materials of other transparent conductive materials or very thin thickness, and the present invention is not as limit.In addition; be coated with protective layer 292 on the electrode layer 290 among the interlayer conducting region B; be positioned at the electrode layer 290 of interlayer conducting region B in order to protection; this protective layer 292 has protection lower floor first conductive layer 260 equally and avoids the function that outside air or aqueous vapor etc. are invaded; particularly; protective layer 292 can be siliceous insulating barrier, and protective layer 292 also can be an organic insulator.
It should be noted that; be different from prior art; the present invention utilizes protective layer 292 to protect to be arranged in first conductive layer 260 of interlayer conducting region B; in other words; duplicate protection by upper electrode layer 290 and protective layer 292 can effectively stop the infringement of external environment for first conductive layer 260, effectively prevents to corrode the generation of first conductive layer, 260 problems.On the other hand, protective layer 292 can expose the electrode layer 290 of transparent area A, so that the electrode layer 290 of signal by this transparent area A that puts on the joint sheet 230 outwards transmits, about the bang path of signal in the joint sheet 230 will be in Fig. 5 illustrated.What deserves to be mentioned is, be arranged in the duplicate protection of first conductive layer 260 of transparent area A, can reach the phenomenon of avoiding 260 corrosion of first conductive layer equally by upper electrode layer 290 and dielectric layer 280.
Second embodiment
Fig. 3 B is the another kind of joint sheet in the second embodiment of the present invention and the generalized section of pixel cell.Please refer to Fig. 3 B, joint sheet 330 is similar with the joint sheet 230 among Fig. 3 A, but the joint sheet 330 of present embodiment in interlayer conducting region B first conductive layer 260 and electrode layer 290 between second conductive layer 270 optionally is set so that electrode layer 290 is connected with first conductive layer 260 via second conductive layer 270 in interlayer conducting region B.Particularly, the material of second conductive layer 270 can be aluminium, molybdenum, titanium, neodymium, its lamination or above-mentioned alloy, and, second conductive layer 270 can further reduce the contact resistance (contact resistance) between first conductive layer 260 and the electrode layer 290, so between reinforced layer among the conducting region B each rete between transmit the effect of signal.
In fact, the rete of joint sheet 230 is made and can be finished in the lump when making pel array 220.Joint sheet 330 and pixel cell 250 with construction drawing 3B are example, in pixel cell 250, grid G for example forms when forming first conductive layer 260 in the lump, the grid G and first conductive layer 260 are same rete, source S and drain D for example form when forming second conductive layer 270 in the lump, source S and drain D and second conductive layer 270 are same rete, and pixel electrode P for example forms when forming electrode layer 290 in the lump, and pixel electrode P and electrode layer 290 are same rete.Specifically, form earlier first patterning conducting layer 260 on substrate 210, forming grid G in the 210D of viewing area, and 330 fates of the joint sheet in periphery circuit region 210P form above-mentioned first conductive layer 260 with first opening H1.Then, the dielectric layer 280 of overlay patternization on the grid G and first conductive layer 260, with formation gate insulation layer GI in the 210D of viewing area, and 330 fates of the joint sheet in periphery circuit region 210P form above-mentioned dielectric layer 280 with second opening H2.Afterwards, on dielectric layer 280, form second conductive layer 270 of patterning, with formation source S and drain D in the 210D of viewing area, and 330 fates of the joint sheet in periphery circuit region 210P form above-mentioned second conductive layer 270 that passes through the second opening H2 and 260 electric connections of first conductive layer.
Then, please continue the B with reference to Fig. 3, form the electrode layer 290 of patterning on second conductive layer 270, with formation pixel electrode P in the 210D of viewing area, and 330 fates of the joint sheet in periphery circuit region 210P form above-mentioned by electrode layer 290.Afterwards, on electrode layer 290, form patterned protective layer 292, form the protective layer 292 of above-mentioned cover part electrode layer 290 with 330 fates of the joint sheet in periphery circuit region 210P.Therefore, joint sheet 330 and existing process compatible among the present invention when improving the corrosion of metals problem, can additionally not increase cost of manufacture, can effectively promote qualification rate.
Fig. 4 is the schematic top plan view of a kind of joint sheet in the second embodiment of the present invention.Please refer to Fig. 4, when the number of the transparent area A of each joint sheet 330 and interlayer conducting region B was respectively a plurality of, the arrangement mode of transparent area A and interlayer conducting region B was for example arranged in the mode that is array each other in fact.As shown in Figure 4, a plurality of interlayer conducting region B can concentrate on first row and first row of each joint sheet 330, and transparent area A then is configured in other arrayed position accordingly, for example 4 * 4 array positions in the contiguous lower right corner among Fig. 4.
Please be simultaneously with reference to Fig. 3 B and Fig. 4, because interlayer conducting region B and transparent area A concentrate respectively to be provided with, make that the second opening H2 and the first opening H1 in first conductive layer 260 in the dielectric layer 280 can be respectively by centralized plannings, that is, in the technology of patterning first conductive layer 260, can be increased as exposure by the first opening H1 of centralized planning, develop, the process margin of technologies such as etching (processmargin), in like manner, in the technology of pattern dielectric layer 280, the second opening H2 of centralized planning also can increase as exposure, develop, the process margin of technologies such as etching.On the other hand; compare with staggered interlayer conducting region B and transparent area A; joint sheet 330 designs of arranging as Fig. 4 can reduce electrode layer 290 and produce the film mesopore because of the landform drop that bottom just rises and falls, and then intensifier electrode layer 290 and protective layer 292 are for the protection effect of first conductive layer 260 or second conductive layer 270.
The 3rd embodiment
Fig. 5 is the generalized section of a kind of display panels of third embodiment of the invention.Please refer to Fig. 5, this display panels 400 comprises active elements array substrates 410, subtend substrate 420, glue frame 430 and liquid crystal layer 440, wherein active elements array substrates 410 for example is the active elements array substrates 410 with joint sheet 450 of above-mentioned arbitrary embodiment, and wherein joint sheet 450 for example is the joint sheet 230,330 in the foregoing description.Subtend substrate 420 is disposed at the subtend of active elements array substrates 410, and has common electrode 422.In addition, glue frame 430 is between common electrode 422 and active elements array substrates 410, and liquid crystal layer 440 is disposed in the space that active elements array substrates 410, subtend substrate 420 and glue frame 430 crossed.In the present embodiment, subtend substrate 420 for example is a colored filter substrate, and display panels 400 can be penetrating type display floater, semi penetration type display floater, reflective display panel, colored filter in the display floater of (color filter on array) on the active layer, the active layer display floater of (array on color filter) or the panel of other kinds on colored filter.
Please continue with reference to Fig. 5, the joint sheet 450 in the display panels 400 is that joint sheet 330 types with second embodiment are that example explains, and joint sheet 450 also can be the type of other embodiment certainly.As shown in Figure 5, glue frame 430 is positioned at joint sheet 450 tops, and common electrode 422 electrically connects via the electrode layer 290 that is exposed on glue frame 430 and the joint sheet 450.Have simultaneously in the joint sheet 450 in order to the interlayer conducting region B that transmits signal and in order to the transparent area A of the irradiation technology that meets glue frame 430.
In more detail; in the present embodiment; the material that is positioned at the glue frame 430 of joint sheet 450 tops belongs to electric conducting material; be commonly referred to as conducting resinl; display panels 400 usually can be by the external voltage source 460 on the active elements array substrates 410; common voltage Vcom is provided first conductive layer 260 to joint sheet 450; this common voltage Vcom is passed to electrode layer 290 by the second opening H2 among the interlayer conducting region B, and the electrode layer 290 between following layer among the conducting region B is again with the electrode layer 290 of this common voltage Vcom lateral transport to transparent area A.Afterwards, the electrode layer 290 of transparent area A is passed to this common voltage Vcom on the common electrode 422 of subtend substrate 420 by the glue frame 430 of conduction.Signaling path can be passed to the signal on the active elements array substrates 410 subtend substrate 420 in view of the above, makes display panels 400 present multiple display frame.
Because first conductive layer 260 in the joint sheet 450 of present embodiment is provided with the protection lamination of duplicate protection respectively above interlayer conducting region B and transparent area A; for example be arranged in electrode layer 290 and protective layer 292 that first conductive layer, 260 tops of interlayer conducting region are covered; and the dielectric layer that covered of first conductive layer, 260 tops that are arranged in transparent area 280 and electrode layer 290; thereby help to stablize the electrical characteristic of first conductive layer 260; can effectively avoid etching problem, keep the display quality of display panels 400.
In sum; in active elements array substrates of the present invention and the display panels; main be provided with above in order to first conductive layer of transmission signals have duplicate protection the protection lamination (for example: electrode layer in the interlayer conducting region and protective layer; the dielectric layer of transparent area and electrode layer), thereby can prevent the destruction of external environment effectively for joint sheet.In addition, joint sheet in active elements array substrates of the present invention and the display panels and existing process compatible do not need extra cost of manufacture.
Though the present invention with preferred embodiment openly as above; yet it is not in order to limit the present invention; those of ordinary skill in the technical field under any; without departing from the spirit and scope of the present invention; when can doing a little change and modification, so protection scope of the present invention should be as the criterion with claims.
Claims (12)
1. active elements array substrates comprises:
Substrate, have the viewing area and with the periphery circuit region of this viewing area adjacency;
Pel array is disposed in this viewing area on this substrate; And
At least one joint sheet is disposed in this periphery circuit region on this substrate, and this joint sheet has at least one transparent area and at least one interlayer conducting region, and this joint sheet comprises:
First conductive layer is disposed on this substrate, and this first conductive layer has first opening at this transparent area;
Dielectric layer covers this first conductive layer, and this dielectric layer has second opening in this interlayer conducting region;
Electrode layer covers this dielectric layer, and this electrode layer electrically connects by this second opening and this first conductive layer; And
Protective layer covers this electrode layer of this interlayer conducting region, and exposes this electrode layer of this transparent area.
2. active elements array substrates as claimed in claim 1, wherein this joint is paid somebody's debt and expected repayment later and is comprised: second conductive layer, be disposed between this electrode layer and this first conductive layer of this interlayer conducting region, so that this electrode layer is connected with this first conductive layer via this second conductive layer in this interlayer conducting region.
3. active elements array substrates as claimed in claim 1, wherein when the number of this transparent area of each joint sheet and this interlayer conducting region is respectively a plurality of, described a plurality of transparent area and described a plurality of interlayer conducting region are arrayed each other, and wherein said a plurality of interlayer conducting region is positioned at first row and first row of each joint sheet, and described a plurality of transparent areas are arrayed corresponding to described a plurality of interlayer conducting regions.
4. active elements array substrates as claimed in claim 1, wherein this protective layer is siliceous insulating barrier, and this protective layer is an organic insulator.
5. active elements array substrates as claimed in claim 1, wherein this pel array comprises a plurality of pixel cells, each described pixel cell comprises:
Thin-film transistor has grid, source electrode and drain electrode; And
Pixel electrode is disposed in this drain electrode of part, and this pixel electrode and this drain electrode electric connection.
6. display panels comprises:
Active elements array substrates comprises:
Substrate, have the viewing area and with the periphery circuit region of this viewing area adjacency;
Pel array is disposed in this viewing area on this substrate; And
A plurality of joint sheets are disposed in this periphery circuit region on this substrate, and each joint sheet has at least one transparent area and at least one interlayer conducting region, and each joint sheet comprises:
First conductive layer is disposed on this substrate, and this first conductive layer has first opening at this transparent area;
Dielectric layer covers this first conductive layer, and this dielectric layer has second opening in this interlayer conducting region;
Electrode layer covers this dielectric layer, and this electrode layer electrically connects by this second opening and this first conductive layer;
Protective layer covers this electrode layer of this interlayer conducting region, and exposes this electrode layer of this transparent area;
The subtend substrate has common electrode;
The glue frame, between this common electrode and this active elements array substrates, and this glue frame is positioned at described a plurality of joint sheets top, and this common electrode is via the described a plurality of electrode layers electric connections that are exposed on this glue frame and the described a plurality of joint sheet; And
Liquid crystal layer is disposed in the space that this active elements array substrates, this subtend substrate and this glue frame crossed.
7. display panels as claimed in claim 6, wherein each joint is paid somebody's debt and expected repayment later and is comprised: second conductive layer, be disposed between this electrode layer and this first conductive layer in this interlayer conducting region, so that this electrode layer is connected with this first conductive layer via this second conductive layer in this interlayer conducting region.
8. display panels as claimed in claim 6, wherein when the number of this transparent area of each joint sheet and this interlayer conducting region is respectively a plurality of, described a plurality of transparent area and described a plurality of interlayer conducting region are arrayed each other, and described a plurality of interlayer conducting region is positioned at first row and first row of each joint sheet, and described a plurality of transparent areas are arrayed corresponding to described a plurality of interlayer conducting regions.
9. display panels as claimed in claim 6, wherein this protective layer is siliceous insulating barrier, and this protective layer is an organic insulator.
10. display panels as claimed in claim 6, wherein this pel array comprises a plurality of pixel cells, each described pixel cell comprises:
Thin-film transistor has grid, source electrode and drain electrode; And
Pixel electrode is disposed in this drain electrode of part, and this pixel electrode and this drain electrode electric connection.
11. display panels as claimed in claim 6, wherein the material of this glue frame is an elargol.
12. an active elements array substrates comprises:
Substrate, have the viewing area and with the periphery circuit region of this viewing area adjacency;
Pel array is disposed in this viewing area on this substrate; And
At least one joint sheet is disposed in this periphery circuit region on this substrate, and this joint sheet has at least one transparent area and at least one interlayer conducting region, and this joint sheet comprises:
First conductive layer is disposed on this substrate, and this first conductive layer has first opening at this transparent area;
Second conductive layer is positioned on this first conductive layer and electrically connects with this first conductive layer;
Dielectric layer covers this first conductive layer, and this dielectric layer is by this first opening and this substrate contacts, and this dielectric layer has second opening in this interlayer conducting region, and this second conductive layer is by this second opening and the electric connection of this first conductive layer;
Electrode layer covers this second conductive layer, and electrically connects by second conductive layer and this first conductive layer; And
Protective layer is positioned on this electrode layer and covers this second conductive layer substantially.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810086306A CN100580938C (en) | 2008-03-25 | 2008-03-25 | Active part array base plate and LCD panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810086306A CN100580938C (en) | 2008-03-25 | 2008-03-25 | Active part array base plate and LCD panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101241919A CN101241919A (en) | 2008-08-13 |
| CN100580938C true CN100580938C (en) | 2010-01-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200810086306A Expired - Fee Related CN100580938C (en) | 2008-03-25 | 2008-03-25 | Active part array base plate and LCD panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102955628B (en) * | 2011-08-26 | 2015-12-09 | 宸鸿科技(厦门)有限公司 | The manufacture method of contact panel |
| CN112068360A (en) * | 2020-09-23 | 2020-12-11 | 北海惠科光电技术有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN115167039A (en) * | 2022-07-11 | 2022-10-11 | 广州华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
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