CN100573832C - Manufacturing has the phosphorous doping methods of the field-effect transistor of a plurality of stacked channels - Google Patents

Manufacturing has the phosphorous doping methods of the field-effect transistor of a plurality of stacked channels Download PDF

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CN100573832C
CN100573832C CNB2005100057284A CN200510005728A CN100573832C CN 100573832 C CN100573832 C CN 100573832C CN B2005100057284 A CNB2005100057284 A CN B2005100057284A CN 200510005728 A CN200510005728 A CN 200510005728A CN 100573832 C CN100573832 C CN 100573832C
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raceway groove
active
channel
layer
channel layer
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CN1702843A (en
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林珍俊
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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    • H01L29/772—Field effect transistors
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    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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    • H01L29/772—Field effect transistors
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

By on the surface of substrate, forming pre-active figure, avoid simultaneously making integrated circuit field effect transistor devices with the pre-active figure of phosphorus doping.Pre-active figure comprises channel layer and channel layer between stacked alternately with each other series of layers.On the substrate at place, the opposite end of pre-active figure, form source/drain regions.Remove a plurality of interlayer channel layers then selectively, pass a plurality of tunnels of pre-active figure, to limit active channel figure that comprises the tunnel and a plurality of raceway grooves that comprise channel layer thus with formation.After removing a plurality of interlayer channel layers selectively, use the phosphorus doping raceway groove.In the tunnel and around raceway groove, form gate electrode then.

Description

Manufacturing has the phosphorous doping methods of the field-effect transistor of a plurality of stacked channels
Related application
The application requires the rights and interests of the Korean Patent Application No. 2004-0037517 of application on May 25th, 2004, therefore here its disclosure is incorporated herein by reference fully.
Technical field
The present invention relates to make the method for integrated circuit (IC)-components.More specifically, the present invention relates to make the method for field-effect transistor.
Background technology
Integrated circuit field effect transistor devices is widely used in logic, memory, processor and other integrated circuit (IC)-components.Integrated circuit field effect transistor devices comprises that source region and drain region, raceway groove therebetween that separates and the gate electrode that is close to raceway groove are known for the technical staff.Integrated circuit field effect transistor devices usually is called mos field effect transistor (MOSFET) or is called the MOS device simply.And integrated circuit field effect transistor devices can provide two kinds of complementary types: the N slot field-effect transistor, usually be called the N-MOS device, and the P-channel field-effect transistor (PEFT) transistor, usually be called the P-MOS device.When providing two kinds of complementary transistor types in an integrated circuit, they can be called cmos device.Although will use these terms in this application, they are commonly used to represent integrated circuit field effect transistor devices and are not limited to the field-effect transistor with metal gate or oxide gate insulator body.
Because the integrated level of integrated circuit field effect transistor devices continues to increase, the size of active area and channel length can continue to reduce.Along with transistorized channel length reduces, source/drain regions becomes quite big to the influence of electric field in the channel region or current potential.These are known as " short-channel effect ".And along with active dimensions scale downward, channel width reduces to increase threshold voltage.These are known as " narrow width effect ".
Various structures have been researched and developed in order to make great efforts in the component size that on reducing substrate, forms to improve or maximize device performance.For example, vertical transistor structure, DELTA (inclination-channel transistor that exhausts fully) structure and GAA (the Gate All Around) structure that is called as fin structure arranged.
For example, U.S. Patent number 6,413,802 disclose a kind of FinFET device.Summary as this patent is pointed, and the FinFET device uses conventional smooth MOSFFT technology to make.(for example, make this device in silicon layer SIMOX), insulating barrier has from the device of insulating barrier such as the extension of fin-shaped thing at the lapped insulation layer.On the side of raceway groove, provide bigrid, with drive current that enhancing is provided with suppress short-channel effect effectively.Can between source region and drain region, provide a plurality of raceway grooves in order to increase current capacity.In one embodiment, can be in a fin stacked two transistors, so that the CMOS with shared grid to be provided transistor.
At U.S. Patent number 4,996, the example of the MOS transistor with DELTA structure is disclosed in 574.Summary as this patent is pointed, the metal-insulator semiconductor transistor comprises insulator layer, provides and comprises the source region on insulator layer, the semiconductor body of the channel region that extends in drain region and the first direction between interconnection source region and drain region, on semiconductor body, provide, contact with gate insulating film so that cover the gate electrode of the electric conducting material of the channel region under the gate insulating film except that the part channel region that contacts with insulating barrier so that cover the gate insulating film of the channel region except that the part channel region that contacts with insulating barrier and provide.Channel region has basically the width less than the maximum extension of twice of the depletion region that forms in the channel region.
At U.S. Patent number 5,583, the example of the thin-film transistor with GAA structure is disclosed in 362.In the typical MOS transistor of GAA structure, soi layer is as active figure, and form gate electrode around the channel region of active figure, and the surface of the channel region of active figure is covered with gate insulation layer.
In on July 1st, 2003 application, name is called the patent application serial numbers 10/610 of Field Effect Transistors HavingMultiple Stacked Channels, field-effect transistor and manufacture method thereof with a plurality of stacked channels have been described in 607, therefore this application transfers assignee of the present invention, here the disclosure of its its elaboration all is incorporated herein by reference.According to some embodiment of patent application serial numbers 10/610,607, form pre-active figure by surface and make integrated circuit field effect transistor devices at substrate.Pre-active figure comprises channel layer and channel layer between stacked alternately with each other series of layers.Source/drain regions is formed on the substrate at opposite end place of pre-active figure.A plurality of interlayer channel layers are removed selectively, pass a plurality of tunnels of pre-active figure with formation, to limit active channel figure that comprises the tunnel and a plurality of raceway grooves that comprise channel layer thus.Gate electrode is formed in the tunnel and centers on raceway groove.
Summary of the invention
Some embodiment according to the present invention avoids making integrated circuit field effect transistor devices with the pre-active figure of phosphorus doping by form pre-active figure on the surface of substrate simultaneously.Pre-active figure comprises channel layer and channel layer between stacked alternately with each other series of layers.On the substrate of the opposite end of pre-active figure, form source/drain regions.Remove a plurality of interlayer channel layers then selectively, pass a plurality of tunnels of pre-active figure, to limit active channel figure that comprises the tunnel and a plurality of raceway grooves that comprise channel layer thus with formation.After removing a plurality of interlayer channel layers selectively, use the phosphorus doping raceway groove.In the tunnel and around raceway groove, form gate electrode then.
In certain embodiments, integrated circuit field effect transistor devices is a P raceway groove integrated circuit field effect transistor devices.In certain embodiments, channel layer comprises monocrystalline silicon, and the interlayer channel layer comprises monocrystalline silicon-germanium and/or uses conventional poly-etching agent to carry out and remove selectively.As used in this, " poly-etching agent (poly-etchant) " refers to be used for monocrystalline silicon/or the wet etching liquid of polysilicon, comprises the mixture of nitric acid (HNOs) and hydrofluoric acid (HF) and can comprise other components such as water (H2O).And, can use ion to inject and/or plasma doping execution doped channel.
Some embodiment of the present invention can be recognize channel layer with respect to the monocrystalline silicon that comprises phosphorus doping use conventional poly-etching agent selectively the etching phosphorus doping the interlayer channel layer with provide a plurality of interlayer channel layers of aforesaid selective removal be difficulty the result.On the contrary, can the plain monocrystalline silicon-germanium of successfully selective etching with respect to plain monocrystalline silicon use conventional " poly-etching agent ".In pre-active figure forming process, postpone or avoid according to embodiments of the invention with the pre-active figure of phosphorus doping, after removing a plurality of interlayer channel layers selectively with phosphorus after doped channel.For example use conventional poly-etching agent can finish selective removal effectively thus.
According to integrated circuit field effect transistor devices such as P-MOS device inventive embodiment has been described above.Other embodiment of the present invention are as being used for making integrated circuit N raceway groove and the P-channel field-effect transistor (PEFT) transistor that is commonly referred to cmos device with the embodiment that describes now.
More particularly, form pre-active figure of N raceway groove and the pre-active figure of P raceway groove, avoid simultaneously with phosphorus doping N raceway groove and the active figure of P raceway groove on the surface of substrate.The pre-active figure of each N raceway groove and P raceway groove comprises channel layer and each N channel layer and P channel layer between stacked alternately with each other series of layers.On the substrate of the opposite end of each the N raceway groove of pre-active figure and P raceway groove, form source/drain regions then.Remove a plurality of interlayers then selectively and pass a plurality of tunnels of N raceway groove and the pre-active figure of P raceway groove, limit a plurality of various N raceway grooves and the P raceway groove that comprises each the active N raceway groove of N and the P raceway groove figure in tunnel and comprise channel layer thus with formation.After removing a plurality of interlayer channel layers selectively, use the P raceway groove of the active P raceway groove of phosphorus doping figure then, after removing a plurality of interlayer channel layers selectively, avoid N raceway groove simultaneously with the active N raceway groove of phosphorus doping figure.In the tunnel and around N raceway groove and P raceway groove, form gate electrode then.
In certain embodiments, after removing a plurality of interlayer channel layers selectively,, avoid simultaneously with the mix P raceway groove of active P raceway groove figure of boron with the mix N raceway groove of active N raceway groove figure of boron.In other embodiments, before removing a plurality of interlayer channel layers selectively, carry out N channel layer, avoid P channel layer simultaneously with the pre-active figure of boron doping P raceway groove with the pre-active figure of boron doping N raceway groove.In another embodiment, after removing a plurality of interlayer channel layers selectively, with boron mix the N raceway groove of active N raceway groove figure and the P raceway groove of active P raceway groove figure.In another embodiment, before removing a plurality of interlayer channel layers selectively with the N channel layer of the pre-active figure of boron doping N raceway groove and the P channel layer of the pre-active figure of P raceway groove.Therefore, can carry out in N raceway groove figure that boron mixes and also can carry out the boron doping in P raceway groove figure, and can be before removing a plurality of interlayer channel layers selectively and/or afterwards.
In some CMOS embodiment, channel layer comprises monocrystalline silicon, and the interlayer channel layer comprises monocrystalline silicon-germanium and/or uses conventional many-etching agent to carry out and remove selectively.And, in some CMOS embodiment, use ion injection and/or plasma doping to carry out the doping of P raceway groove.
Description of drawings
Figure 1A is with respect to the cross section picture of boron doped single-crystal Si epitaxial layers by channel layer between the conventional boron doped N raceway groove of multiple wet etchant etching silicon-germanium layer;
Figure 1B is the cross section picture of P raceway groove silicon-germanium layer that can not be by conventional polysilicon wet etchant etching phosphorus doping;
Fig. 2 A and 2B show some embodiment according to the present invention respectively and have the active figure of MOS transistor of a plurality of raceway grooves and the perspective view of gate electrode;
Fig. 3 A is the plane graph according to the device of the first embodiment of the present invention;
Fig. 3 B and 3C are respectively the profiles along the device of the line AA ' of Fig. 2 A and BB ' figure;
Fig. 4 A to 4S illustrates the profile of the method for making device according to one embodiment of present invention;
Fig. 5 A to 5G illustrates the perspective view of making some method step of device according to the first embodiment of the present invention;
Fig. 6 A-6R illustrates the profile of the method for making device according to a second embodiment of the present invention;
Fig. 7 is the zoomed-in view of the part " A " among Fig. 4 S;
Fig. 8 A and 8B are respectively the perspective view and the profiles of the device of a third embodiment in accordance with the invention, and Fig. 8 C is the zoomed-in view of the part " B " of Fig. 8 B;
Fig. 9 A to 9N illustrates the profile that a third embodiment in accordance with the invention is made the method for device;
Figure 10 is the profile of the device of a fourth embodiment in accordance with the invention;
Figure 11 is the profile of device according to a fifth embodiment of the invention;
Figure 12 is the profile of device according to a sixth embodiment of the invention;
Figure 13 A to 13K illustrates the profile of the method for making device according to a seventh embodiment of the invention;
Figure 14 is the profile according to the device of the eighth embodiment of the present invention;
Figure 15 is the profile according to the device of the ninth embodiment of the present invention;
Figure 16 is the profile according to the device of the tenth embodiment of the present invention;
Figure 17 is the profile according to the device of the 11st embodiment of the present invention;
Figure 18 is the profile according to the device of the 12nd embodiment of the present invention;
Figure 19 is the profile according to the device of the 13rd embodiment of the present invention;
Figure 20 A to 20F illustrates the profile of making the method for device according to the 14th embodiment of the present invention;
Figure 21 is the profile according to the device of the 15th embodiment of the present invention;
Figure 22 A to 22E illustrates the profile of making the method for device according to the 16th embodiment of the present invention; And
Figure 23 A to 23C illustrates the profile of making the method for semiconductor device according to the 17th embodiment of the present invention.
Embodiment
The present invention, the preferred embodiments of the present invention shown in it are described hereinafter with reference to the accompanying drawings more completely.But the present invention can embody with different ways, should not be construed as limited to embodiment set forth herein.On the contrary, provide these embodiment, and scope of the present invention is passed to fully the technical staff in described field so that the disclosure is completely and completely.In the drawings, can amplification layer and regional size and relative size in order to know.In entire chapter, identical mark refers to components identical.
Be to be understood that when an element for example floor, district or substrate refer to another element " on " time, can directly can there be insertion element in it on another element or also.Term " directly exist ... on " mean there is not insertion element.And, this can use relative terms as " ... following " or " ... top " describe a layer or zone and other layer or regional with respect to as shown in the figure substrate or the relation of basic unit.Be to be understood that these terms are intended that the different orientation that comprises the device the orientation of describing in figure.Term as used herein " and/or " comprise one or more relevant arbitrary and all combinations of lising.
Although be to be understood that at this and can use term first and second grades to describe various elements, these elements are not limited by these terms should.Use these terms that an element is distinguished mutually with another element.For example, do not breaking away under the instruction condition of disclosure, the ground floor of discussing below can be called the second layer, and same, the second layer can be called ground floor.
Specialized vocabulary is only to be used to describe specific embodiment rather than restriction the present invention as used herein.Singulative as used herein " a ", " an " and " the " is same to plan to comprise plural form, unless context is clearly pointed out in addition.It should also be understood that, when the term that in specification, uses " comprises " and/or " comprising ", the existence of parts, integral body, step, operation, element and/or the part of statement is described, but does not get rid of existence or increase one or more miscellaneous parts, integral body, step, operation, element, part and/or its group.
Described embodiments of the invention at this with reference to sectional view, sectional view is the signal legend of idealized embodiment of the present invention (and intermediate structure).Like this, should be contemplated to the variation of consequent legend shape, for example the variation of manufacturing process and/or tolerance.Therefore, embodiments of the invention should not be considered as the given shape that is limited to zone shown here, but comprise result's form variations, for example manufacture deviation.For example, be illustrated as layer and will generally have the accurate shape shown in certain roughness rather than the figure with smooth surface.Therefore, the zone shown in the figure be in essence schematically and their shape do not plan to illustrate the true form of device area and do not plan to limit the scope of the invention.
Unless otherwise defined, all terms (comprising technology and scientific terminology) have and the identical meaning of those of ordinary skill common sense that belongs to technical field of the present invention as used herein.It should also be understood that term should be interpreted as having the meaning in the environment that meets correlation technique as those terms that define and not be interpreted as the meaning as the idealized or form perception exceedingly that clearly limits at this in normally used dictionary.
As mentioned above, U.S. Patent Application Serial Number 10/610,607 have described the method that forms pre-active figure manufacturing integrated circuit field effect transistor devices by the surface at substrate, wherein pre-active figure comprises channel layer and channel layer between stacked alternately with each other series of layers, and forms source/drain regions on the substrate at place, the opposite end of pre-active figure.Remove a plurality of interlayer channel layers selectively, pass a plurality of tunnels of pre-active figure, to limit active channel figure that comprises the tunnel and a plurality of raceway grooves that comprise channel layer thus with formation.Neutralization forms gate electrode around raceway groove in the tunnel.In certain embodiments, channel layer comprises mono-crystalline epitaxial silicon, and the interlayer channel layer comprises mono-crystalline epitaxial silicon-germanium.Boron generally is used for doped channel layer and P type interlayer channel layer and phosphorus and generally is used for doped channel layer and N type interlayer channel layer.In certain embodiments, channel layer can have approximately
Figure C20051000572800121
Thickness, the interlayer channel layer can have approximately
Figure C20051000572800122
Thickness.
Unfortunately, shown in Figure 1A and 1B, when passing a plurality of tunnel of pre-active figure with formation, the interlayer channel layer may have difficulties when removing selectively.Specifically, shown in Figure 1A, when the interlayer channel layer comprises that boron doped p type single crystal silicon-germanium layer and channel layer comprise boron doped p type single crystal silicon layer, can use the conventional multiple wet etchant boron doped P type of etching silicon-germanium effectively with respect to boron doped P type silicon.But unfortunately, in P-channel device, wherein the interlayer channel layer comprises the n type single crystal silicon-germanium of phosphorus doping, and channel layer comprises the n type single crystal silicon of phosphorus doping, by the conventional wet etchant silicon-germanium of etching phosphorus doping selectively, shown in Figure 1B.
According to embodiments of the invention, by, avoid with the pre-active figure of phosphorus doping, after forming the active channel figure, can overcome this difficulty removing a plurality of interlayer channel layers then with the phosphorus doping raceway groove.By avoiding with the pre-active figure of phosphorus doping, the pre-active figure of etching effectively, to remove the interlayer channel layer selectively and to form a plurality of tunnels, this pre-active figure can comprise channel layer and plain or boron doped silicon channel layer between plain or boron doped silicon-germanium layer.After removing the interlayer channel layer selectively, can carry out phosphorus doping then.And, because mixing, boron can not influence the selective etch of interlayer channel layer, therefore when the pre-active figure of formation or remove the interlayer channel layer selectively and can carry out afterwards the boron doping to form active figure.
Fig. 2 A and 2B show some embodiment according to the present invention respectively and have the active figure of MOS transistor of a plurality of raceway grooves and the perspective view of gate electrode.
With reference to figure 2A, as comprising a plurality of raceway groove 4a that are formed in the vertical direction, form active figure on the surface of the Semiconductor substrate (not shown) of 4b and 4c at the integrated circuit substrate.Although show three raceway groove 4a in an embodiment, 4b and 4c, the number that can form two raceway grooves or raceway groove can be above three.
Raceway groove 4a, 4b and 4c have the vertical stacked of narrow width.At raceway groove 4a, form a plurality of tunnel 2a, 2b and 2c between 4b and the 4c.Place, both sides at active figure forms source/drain regions 3, so that be connected to a plurality of raceway groove 4a, 4b and 4c.
Source/drain regions 3 forms has than raceway groove 4a the width that 4b and 4c are wideer.At source/drain regions 3 and raceway groove 4a, 4b can form between the 4c source/drain regions 4 is connected to raceway groove 4a, the source/drain regions extended layer 5 of 4b and 4c.
Particularly, active figure is included in the source/drain regions 3 that has the cuboid shape of broad width on the both sides of active figure.But, be to be understood that active figure can have the arbitrary polygon shape, and side and vertical edges needn't equate.Between source/drain regions 3 interconnected source/drain regions 3, form the channel region that has than the narrower width of cuboid shape.Channel region comprises two source/drain regions extended layers 5 that are connected to source/drain regions 3.Two a plurality of raceway groove 4as of source/drain regions extended layer 5 by forming in vertical direction, 4b and 4c are connected to each other.At raceway groove 4a, form a plurality of tunnel 2a, 2b and 2c between 4b and the 4c.Between the bottom surface section of minimum channel layer 4a and Semiconductor substrate, form minimum tunnel 2a.Go up most on the raceway groove 4c groove 2 that forms tunnel-shaped '.
With reference to figure 2B, on active figure, form gate electrode 6.Although run through and/or fill a plurality of tunnel 2a, 2b and 2c and tunnel groove 2 ', gate electrode 6 forms in the vertical direction direction of the formation direction of source/drain regions on the plane (that is, perpendicular to) around a plurality of raceway groove 4a, 4b and 4c.At gate electrode 6 and a plurality of raceway groove 4a, form grid-insulating barrier 7 between 4b and the 4c.
Semiconductor substrate comprises silicon (Si), silicon-germanium (SiGe), the silicon on the insulator (SOI), the silicon-germanium on the insulator (SGOI) and/or other conventional substrates.In certain embodiments, Semiconductor substrate comprises single crystalline Si.
Raceway groove 4a, 4b and 4c comprise single crystal semiconductor films, as silicon fiml.Source/drain regions 3 comprises selective epitaxial single crystal film or conductive film such as polysilicon film, metal film, metal silicide film etc.Under the situation of using selective epitaxial single crystal film or polysilicon film, impurity is by in source ion implantation district/drain region 3, so that source/drain regions 3 conductions.
At raceway groove 4a as shown in the figure, form under the situation of source/drain regions extended layer 5 between 4b and 4c and the source/drain regions 3, in certain embodiments, source/drain regions 3 comprises conductive film such as polysilicon film, metal film, metal silicide film etc., and source/drain regions extended layer 3 comprises the selective epitaxial single crystal film.
Gate electrode 6 comprises polysilicon film and can comprise grid stack layer 8 on the top surface that is formed on gate electrode 6.Grid stack layer 8 comprises the insulating material that is used to reduce the metal silicide of gate resistance and/or is used for covering grid electrode 6.Grid-insulating barrier 7 comprises heat oxide film or ONO film.
In the MOS transistor of some embodiment of the present invention, a plurality of thin channel 4a, 4b and 4c are connected to source/drain regions 3, source/drain regions 3 forms perpendicular to a plurality of raceway groove 4a, have uniform Impurity Distribution in the direction of 4b and 4c, can keep uniform source/drain junction capacitance although the raceway groove number increases these.So, although reduce or minimum junction capacitance, electric current can increase, to improve device speed.
And, can provide the MOS transistor that has less than the gate electrode of channel width in certain embodiments, because gate electrode 6 centers on a plurality of raceway groove 4a, 4b and 4c, so these can cause the device integrated level to improve.
In addition, in certain embodiments, etch away and to form the zone of the active figure of source/drain regions, wherein active figure comprises stacked alternately with each other a plurality of interlayer channel layers and a plurality of channel layer, the interlayer channel layer is as tunnel 2, and channel layer is as raceway groove 4a, 4b and 4c.Then, the zone of etching provides and/or is filled with epitaxy single-crystal film and/or electric conducting material, to form source/drain regions 3.Thus, only the active figure of channel region can be left, may be limited in the gate length zone so that be filled with the horizontal length in the tunnel 2 of gate electrode, to obtain integrated to heavens MOS transistor thus, this MOS transistor has the grid length littler than channel width.
Embodiment 1
Fig. 3 A is the plane graph according to the semiconductor device of the first embodiment of the present invention.Fig. 3 B and 3C are respectively the profiles along the semiconductor device of the line AA ' of Fig. 3 A and BB '.
With reference to figure 3A to 3C, on the first type surface of substrate 10, form active figure 30, active figure 30 comprises having a plurality of raceway groove 44a of being vertically formed and many raceway grooves 44 of 44b in the direction that makes progress, and substrate 10 comprises silicon (SOI), the silicon-germanium (SGOI) on the insulator and/or other conventional material/layers on silicon (Si), silicon-germanium (SiGe), the insulator.Source/drain regions 34 so forms so that be connected to raceway groove 44a and 44b at the opposite side of active figure 30.Between source/drain regions 34 and a plurality of raceway groove 44a and 44b, form the source/drain regions extended layer 32 that is connected to source/drain regions 34 and is connected to raceway groove 44 and 44b.That is source/drain regions extended layer 32 is as source/drain regions 34 is bridged to a plurality of raceway groove 44a and 44b.
Between a plurality of raceway groove 44a and 44b, form a plurality of tunnels 42.Between the bottom surface section of minimum channel layer 44a and Semiconductor substrate, that is, between the heavy doping impurity range 12 of substrate 10, form minimum tunnel 42a.On the raceway groove 44b that goes up most, form the groove 42c of tunnel-shaped.
Raceway groove 44a and 44b can comprise semi-conducting material such as monocrystalline silicon, and source/drain regions 34 can comprise electric conducting material such as polysilicon, metal, metal silicide etc.Here, use forms from the source/drain regions extended layer 32 of raceway groove 44a and 44b extension with raceway groove 44a and 44b identical materials.At some embodiment, source/drain regions extended layer 32 is made of the selective epitaxial single crystalline Si.
On active figure 30, form the gate electrode 48 that runs through and/or fill tunnel 42, tunnel 42 is included between raceway groove 44a and the 44b and centers on a plurality of tunnel 42a and the 42b of raceway groove 44a and 44b formation in vertical direction.Promptly forming gate insulation layer 46 on tunnel 42 inner surfaces and on the madial wall of the groove 42 of tunnel-shaped and basal surface between gate electrode 48 and raceway groove 44a and the 44b.In certain embodiments, form gate electrode 48 on the top surface of gate electrode 48, gate electrode 48 comprises and is used to reduce the polysilicon of gate resistance and the grid stack layer 50 of metal silicide.
Form field region 22, so that around the source/drain regions 34 except that the channel region of a plurality of raceway groove 44a and 44b.Below active figure 30, promptly form heavily doped region 12 in the first type surface of the substrate 10 below the minimum raceway groove 44a part.Heavily doped region 12 can reduce or prevent that the transistorized operation in the end from causing short-channel effect.
Fig. 4 A to 4S illustrates the profile of making the method for semiconductor device according to the first embodiment of the present invention.Fig. 5 A to 5G illustrates the perspective view of making some method step of semiconductor device according to the first embodiment of the present invention.
With reference to figure 4A, injected the first type surface of substrate 10 with the impurity of substrate 10 identical conduction types by ion, to form the heavily doped region (well region) 12 that can reduce or prevent the transistorized operation in the end.Substrate 10 comprises silicon (Si), silicon-germanium (SiGe), the silicon on the insulator (SOI), the silicon-germanium on the insulator (SGOI) and/or other conventional substrate/layer.In certain embodiments, Semiconductor substrate 10 comprises single crystalline Si.
With reference to figure 4B, stacked alternately with each other a plurality of interlayer channel layers 14 and a plurality of channel layer 16 on substrate 10.At first, form channel layer 14a between ground floor on the substrate 10, then, on channel layer 14a between ground floor, forming the first channel layer 16a.Form the interlayer channel layer 16c that goes up most in the position of going up most.
Channel layer 16 and interlayer channel layer 14 are made of the single-crystal semiconductor material that has the etching selection rate mutually.In certain embodiments, channel layer 16 is by having approximately The single crystalline Si epitaxial film formation of thickness and interlayer channel layer 14 are by having approximately
Figure C20051000572800162
The monocrystalline Ge of thickness (comprise, for example, single crystalline Si Ge) epitaxial film formation.
Can be according to the transistorized purposes control channel layer 16 that will form and the repetition number and the thickness of interlayer channel layer 14.In certain embodiments, channel layer 16 and interlayer channel layer 14 are stacked alternately with each other, so that gross thickness becomes approximately
Figure C20051000572800163
Shown in Fig. 4 B, interlayer channel layer 14 and channel layer 16 can mix with boron for another example.Can be the N channel device, in certain embodiments, also can mix, wherein, mix so that site N type to be provided with the high concentration P-channel device that mixes after with phosphorus for P-channel device provides boron.But according to embodiments of the invention, in Fig. 4 B, N raceway groove or P-channel device are not carried out phosphorus doping.Therefore, although Fig. 4 B shows optionally boron doping step, do not carry out phosphorus doping.
With reference to figure 4C, by a plurality of channel layers 16 of photo-mask process composition and a plurality of interlayer channel layer 14, with formation have the pre-figure of first channel layer (or the preliminary figure of first channel layer) 16 ' and ground floor between the pre-figure of channel layer (or between ground floor the preliminary figure of channel layer) 14 ' pre-active figure 18.A plurality of first channel layer figure 16a ' and the 16b ' of the pre-figure 16 of first channel layer ' comprise.The pre-figure 14 of channel layer between ground floor ' comprise a plurality of interlayer channel layer figure 14a ', 14b ' and 14c '.Enough carry out etching procedure for a long time, forming isolation channel 20 in substrate 10, isolation channel 20 has the degree of depth darker than impurity range 12.
Next, by chemical vapor deposition (CVD) method deposited oxide layer, so that fill isolation channel 20.By the oxide skin(coating) of deep etching technique or the smooth deposit of chemico-mechanical polishing (CMP) technology,, form field region 22 thus around pre-active figure 18 up to the surface of exposing pre-active figure 18.
With reference to figure 4D, stacked continuously etching on the substrate 10 that comprises pre-active figure 18-stop layer 23, dummy gate layer 25 and anti-reflecting layer 27.Form etching stop layer 23 by material such as the silicon nitride that has the etching selection rate with respect to virtual grid layer 25, to about
Figure C20051000572800171
Thickness.Etching-stop layer 23 plays a part to reduce in the process of the virtual grid layer 25 of etching or prevents that pre-active figure is etched down, is formed for limiting the dummy gate layer of gate regions by silica, to approximately
Figure C20051000572800172
Thickness.Be formed in the photo-mask process process, reducing or prevent the anti-reflecting layer 27 of light by the use silicon nitride, extremely approximately from following substrate reflection
Figure C20051000572800173
Thickness.
With reference to figure 4E, by photoetching process, dry etching falls anti-reflecting layer 27, virtual grid layer 25 and etching-stop layer 23 continuously, has the hard mask 29 of grid of anti-reflecting layer figure 28, dummy gate figure 26 and etching stopping layer pattern 24 with formation.The hard mask 29 of grid has the width of about 0.2～0.3 μ m, plays the effect that makes source/drain regions aim at channel region automatically.
With reference to figure 4F, use the hard mask of grid 29 as etching mask, etch away the pre-active figure 18 that exposes, exposed up to the surface of substrate 10, limit the zone 30 that will form source/drain regions thus.Therefore, only be left the channel region of pre-active figure 18.At this moment, enough carry out for a long time etching procedure, with the top of etching semiconductor substrate 10 to the drop shadow spread that is lower than heavily doped region 12.
As a result, as shown in the figure, formation comprises the active channel figure 18a of the second channel layer figure 16 " and between the second layer raceway groove layer pattern 14 " below the hard mask 29 of grid.Second channel layer figure 16 " by a plurality of second channel layer figure 16a " and 16b " constitute, and raceway groove layer pattern 14 " by a plurality of interlayer channel layer figure 14a " between the second layer, 14b " and 14b " constitutes.
Be not etched and be used as in the conventional GAA structure of source/drain regions at active area, when anisotropically between etch layer during channel layer, the tunnel can flatly extend to increase the length of gate electrode.On the contrary, in certain embodiments of the present invention, the active graph area that forms source/drain regions is etched, fills etched area with electric conducting material then, to form source/drain regions.Thus, may be limited in the gate length district owing to constitute the horizontal length of the interlayer channel layer 14 of active channel figure 18, therefore channel layer 14 between the second layer in the subsequent handling process that " it can reduce or prevent that the tunnel from flatly extending when forming the tunnel by etching anisotropically.Therefore, can obtain to have integrated MOS transistor less than the gate length of channel width.
With reference to figure 4G, on the surface of the etched area 30 of Semiconductor substrate 10 and the upper lateral part of active channel figure 18a divide ground growth selectivity epitaxy single-crystal film to approximately
Figure C20051000572800181
Thickness, form source/drain regions extended layer 32 thus.Here, if wish, inject doping selective epitaxial single crystal film by angle-tilt ion, so that each second channel layer figure 16a " and 16b " has uniform source/drain regions impurity concentration.In some cases, have or do not carry out ion and inject, dopant is to be heavily doped solid phase from the source/drain regions diffusion in the subsequent anneal operation, to form the source/drain regions extended layer 32 that has uniform source/drain regions doping content with respect to each channel layer 16 thus.
With reference to figure 4H, depositing conductive material on source/drain regions extended layer 32, and in certain embodiments,, form conductive film thus so that fully fill etched area 30.Then, lose the surface of conductive film deeply, to form the source/drain regions 34 that only is included in the heavy doping conductive film in the etched area 30 to active channel figure 18a.In certain embodiments, electric conducting material comprises polysilicon, metal and/or the metal silicide of doping.As mentioned above, in certain embodiments, because form source/drain regions 34, so source/drain regions 34 has vertically the even Impurity Distribution along active channel figure 18a by deposit.The afterbody 34a that below the side of the hard mask 29 of grid, can residually be used for the conductive film of source/drain regions here.
Optionally, for the surface roughness of the source/drain regions extended layer 32 that reduces to comprise the epitaxy single-crystal film and crystallization source/drain regions extended layer 32 again, can be before the deposit conductive film at hydrogen (H 2) high temperature in the atmosphere carries out heat treatment down.
With reference to figure 4I, deposit silicon nitride is so that the hard mask 29 of grid on covering source/drain regions 34 and the field region 22 forms mask layer 35 thus.In certain embodiments, mask layer 35 comprises the superiors with the hard mask 29 of formation grid, that is, and and anti-reflecting layer figure 28 identical materials.Here, before deposition mask layer 35, the surface portion that the surface portion by thermal oxidation process oxidation source/drain regions 34 and the active channel figure 18a of channel region expose forms oxide skin(coating).This oxide skin(coating) is as stress-resilient coating.
With reference to figure 4J, exposed up to the surface of dummy gate figure 26, remove mask layer 35 by deep erosion or chemico-mechanical polishing, expose the mask graph 36 of dummy gate figure 26 with formation.Fig. 5 A is the perspective side elevation view that specifies step shown in Fig. 4 J.
With reference to figure 4K, use mask graph 26, remove dummy gate figure 26 selectively, to form gate groove 38.Etching-stop layer pattern 24 reduces or prevents to remove in the etching procedure process of dummy gate figure 26 down that pre-active figure 18 is etched.Fig. 5 B is the perspective side elevation view that specifies step shown in Fig. 5 K.
With reference to figure 4L, if below the side of the hard mask 29 of grid residual conduction afterbody 34a, carry out oxidation operation and/or wet etching operation so to remove conduction afterbody 34a.In certain embodiments, carry out oxidation operation, change insulating barrier 40 into will conduct electricity afterbody 34a, prevent from thus to conduct electricity afterbody 34a with in subsequent handling with the gate electrode short circuit that forms.
With reference to figure 4M, remove by gate groove 38 and expose etching stopping layer pattern 24.When the raceway groove figure 18a of boron impurity doped channel regions of no use in Fig. 4 B, can carry out the boron channel ion partly by gate groove 38 and inject, shown in Fig. 4 M, to use the active channel figure 18a of boron doped channel regions thus.In certain embodiments, carry out raceway groove boron ion and inject, so that in each second channel layer figure 16a " and 16b ", form drop shadow spread.Here, reference number 41 expression raceway groove boron ion-injection regions.And, in certain embodiments, carry out raceway groove boron ion and inject, so that each second channel layer figure 16a " with 16b " can have different doping content mutually, obtaining thus can be according to the transistor of the grid voltage work that applies.
In other embodiments of the invention, can carry out boron shown in Fig. 4 B and Fig. 4 M mixes.But, should be appreciated that according to embodiments of the invention, in arbitrary process of Fig. 4 A-4M, do not carry out phosphorus doping.
Next, use source/drain regions 34, etch away field region 22 selectively, with the side of the active channel figure 18a that exposes channel region, shown in Fig. 5 C as etching mask.Fig. 5 C shows the perspective side elevation view of unshowned part in the profile of Fig. 4 M particularly.
With reference to figure 4N, by the isotropic etching operation, remove a plurality of interlayer channel layer figure 14a selectively ", 14b " and 14c "; pass many tunnel 42a of tunnel groove 42c and the 42b of active channel figure 18a and tunnel-shaped with formation, tunnel groove 42c is positioned at the position of going up most.Here, the second channel layer figure 16a " and 16b " forms a plurality of raceway groove 44a and 44b.Preferably, a plurality of tunnel 42a and 42b and a plurality of raceway groove 44a and 44b form the identical width of dummy gate figure 26 that has with in about 50% the scope.Owing to so far do not carry out phosphorus doping, therefore " can use conventional poly-the etching agent plain or boron doped interlayer channel layer of etching figure 14 selectively " with respect to channel layer figure 16.
Fig. 5 D is the perspective side elevation view that specifies step shown in Fig. 4 N.As shown in the figure, the lateral parts that partly exposes source/drain regions extended layer 32 by tunnel 42a and 42b.
With reference now to Fig. 4 O,, after having formed Close Tunnel 42, with phosphorus doping P channel region 49a and 49b.In other words, removing a plurality of interlayer channel layers 14 selectively " afterwards, with phosphorus doping raceway groove 49.If wish that also can carry out boron mixes this moment.In certain embodiments, use ion to inject the phosphorus doping of carrying out Figure 40.In other embodiments, use plasma doping to carry out the phosphorus doping of Figure 40.Can use plasma doping in certain embodiments of the present invention, to obtain uniform phosphorus doping P channel region 49.The plasma doping operation is the known technology of those skilled in the art, needn't be further described at this.
With reference to figure 4P, carry out thermal oxidation process, on the inner surface of the surface of a plurality of raceway groove 49a and 49b and tunnel groove 42c, to form gate insulation layer 46 to approximately
Figure C20051000572800211
Thickness.Fig. 5 E specifies the perspective side elevation view of the step shown in Fig. 4 P.As shown in the figure, on the part surface of the source/drain regions extended layer that exposes by raceway groove, also form gate insulation layer 46 continuously.
Here, in order to reduce the surface roughness of raceway groove 49a and 49b, can be at hydrogen (H before forming gate insulation layer 46 2) or argon gas (Ar) atmosphere in high temperature carry out down heat treatment, reduce the roughness between gate insulation layer 46 and the raceway groove thus.In addition, gate insulation layer 46 can be made of silicon oxynitride.
With reference to figure 4Q, form gate electrode 48, so that fill a plurality of tunnel 42a and 42b and tunnel groove 42c, and around a plurality of raceway groove 49a and 49b.In certain embodiments, gate electrode 48 comprises the polysilicon of doping.Fig. 5 F is the perspective side elevation view that specifies the step shown in Fig. 3 P.
With reference to figure 4R, on polygate electrodes 48, form the grid stack layer 50 comprise the metal silicide that is used to reduce gate resistance.At this moment, grid stack layer 50 can for example silica or silicon nitride constitute by the insulating material that is used for cover gate.Fig. 5 G is the perspective side elevation view that specifies the step shown in Fig. 4 R.
With reference to figure 4S, mask graph 36 is removed, and carries out subsequent handling such as metal interconnected then, to finish the vertical MOS-transistor with a plurality of raceway grooves.In some cases, mask graph 36 can be left as insulating intermediate layer.
Embodiment 2
Fig. 6 A-6R illustrates the profile of making the method for integrated circuit field effect transistor devices according to second second embodiment of the present invention.In these embodiments, in the single integrated circuit substrate, make and be commonly referred to N-MOS and P-MOS transistorized integrated circuit N raceway groove and P-channel field-effect transistor (PEFT) transistor, so that complementary MOS (CMOS) device to be provided.
As described in conjunction with Fig. 6 A-6R, form pre-active figure of N raceway groove and the pre-active figure of P raceway groove on the surface of substrate, avoid simultaneously with phosphorus doping N raceway groove and the pre-active figure of P raceway groove.The pre-active figure of each N raceway groove and P raceway groove comprises channel layer and each N channel layer and P channel layer between stacked alternately with each other series of layers.On the substrate at the place, opposite end of each the N raceway groove of pre-active figure and P raceway groove, form source/drain regions then.Remove a plurality of interlayers then selectively, pass a plurality of tunnels of N raceway groove and the pre-active figure of P raceway groove, limit each active N raceway groove and P raceway groove figure that comprises the tunnel and a plurality of each N raceway groove and the P raceway groove that comprises channel layer thus with formation.After removing a plurality of interlayer channel layers selectively,, after removing a plurality of interlayer channel layers selectively, avoid N raceway groove simultaneously then with the active N raceway groove of phosphorus doping figure with the P raceway groove of the active P raceway groove of phosphorus doping figure.In the tunnel and around N raceway groove and P raceway groove, form gate electrode then.
Described in conjunction with Fig. 6 A-6R for another example, in certain embodiments, after removing a plurality of interlayer channel layers selectively,, avoid simultaneously with the mix P raceway groove of active P raceway groove figure of boron with the mix N raceway groove of active N raceway groove figure of boron.In other embodiments, before removing a plurality of interlayer channel layers selectively,, avoid simultaneously with the mix P channel layer of pre-active P raceway groove figure of boron with the boron pre-active N raceway groove graph layer N channel layer that mixes.In another embodiment, after removing a plurality of interlayer channel layers selectively, with boron mix the N raceway groove of active N raceway groove figure and the P raceway groove of active P raceway groove figure.At last, in other embodiments, removing selectively between a plurality of N raceway grooves before the raceway groove N raceway groove, with the N channel layer of the pre-active figure of boron doping N raceway groove and the P channel layer of the pre-active figure of N raceway groove.Therefore, before removing the interlayer channel layer selectively and/or after removing the interlayer channel layer selectively, can optionally in the P raceway groove, carry out boron in the neutralization of N raceway groove and mix.But, after removing a plurality of interlayer channel layers selectively, only carry out the phosphorus doping of P raceway groove.
In Fig. 6 A-6R and subsequent figure, the similar elements of the same numbers presentation graphs 4A-4S in the N-MOS device on the left side of figure.Similar elements in the P-MOS device that the right side of figure is located will be represented by the same numbers that multiply by 10 (promptly extra add " 0 ").
With reference now to Fig. 6 A,, injected the first type surface of substrate 10 with the impurity of substrate 10 identical conduction types by ion, to form first heavily doped region (well region) 12 that can reduce or prevent end transistor operation.Injected substrate 10 with the impurity of substrate 10 films of opposite conductivity by ion, to form second heavily doped region (well region) 120 that can reduce or prevent end transistor operation.
With reference to figure 6B, as described in conjunction with Fig. 4 B, stacked a plurality of interlayer channel layers 14 and a plurality of channel layer 16.
With reference to figure 6C, as described in conjunction with Fig. 4 C, by a plurality of raceway grooves 16 of photo-mask process composition and a plurality of interlayer channel layer 14.
With reference to figure 4D, as described in conjunction with Fig. 4 D, stacked continuously etching on substrate 10-stop layer 23, dummy gate layer 25 and anti-reflecting layer 27.
With reference to figure 6E, as described in conjunction with Fig. 4 E, etching anti-reflecting layer 27, dummy gate layer 25 and etching stop layer 23 are to form hard mask 29.
With reference to figure 6F, as described in conjunction with Fig. 4 f, use the hard mask of grid 29 as etching mask, etch away the pre-active figure 18 that exposes.
With reference to figure 6G, as described in conjunction with Fig. 4 G, growth selectivity epitaxy single-crystal film partly is to form source/drain regions extended layer 32 and 320.
With reference to figure 6H, as described in conjunction with Fig. 4 H, depositing conductive material on source/drain regions extended layer 32 and 320 is to form source/ drain regions 34 and 340 thus.
With reference now to Fig. 6 I,, as formation mask layer 35 as described in conjunction with Fig. 4 I.
With reference now to Fig. 6 J,, as described in conjunction with Fig. 4 J, removes mask layer 35 selectively.
With reference to figure 6K, as described in conjunction with Fig. 4 K, remove dummy gate 26, with formation gate trench 38.
With reference to figure 6L, as formation insulating barrier 40 as described in conjunction with Fig. 4 L.
With reference now to Fig. 6 M,, removes etching stop layer 24 by the wet etching operation, and mix as execution boron as described in conjunction with Fig. 4 M.In this respect, should be noted that in certain embodiments of the present invention that only the N-MOS device can mix with boron by mask P-MOS device.In other embodiments, can be with boron mix N-MOS and P-MOS device, shown in Fig. 6 M.In another embodiment, can leave out and " the boron doping step of execution graph 6M afterwards is as following detailed description at etching channel region 14 selectively.
With reference now to Fig. 6 N,, by the isotropic etching operation, remove a plurality of interlayer channel layer figure 14a selectively "; 14b " and 14c "; pass the active channel figure of topmost office and a plurality of first tunnel 42a and 42b of the first tunnel groove 42c, a plurality of second tunnel 420a and the 420b and the second tunnel groove 420c with formation, as described in conjunction with Fig. 4 N.
With reference now to Fig. 6 O,, use ion injection and/or plasma doping operation with phosphonium ion doping P channel region 490, as described in conjunction with Fig. 4 O.By on the N-MOS device, providing mask 37 without phosphorus doping N-MOS device.Should be appreciated that also that as described in this moment also can be with boron mix N-MOS and P-MOS device, or this moment can be by mask PMOS device only with boron doping N-MOS device.
With reference now to Fig. 6 P,, as described in conjunction with Fig. 4 P, forms gate insulation layer 46.
With reference to figure 6Q, as described in conjunction with Fig. 4 Q, form gate electrode 48 and 480.
With reference to figure 6R, as described in conjunction with Fig. 4 R, on gate electrode, form gate stack 50.Can remove mask graph then and can carry out subsequent handling, to finish CMOS transistor with a plurality of raceway grooves.In some cases, mask graph 36 can stay as insulating barrier.
Embodiment 3
Fig. 7 shows the zoomed-in view of the part " A " among Fig. 4 S.With reference to figure 7, in the vertical MOS-transistor in embodiment 1, gate insulation layer 46 is present between gate electrode 48 and the source/drain regions 34 (specifically, the source/drain regions extended layer 32), between gate electrode 48 and source/drain regions 34, causing overlap capacitance thus, as by shown in the capacitor mark ().The vertical MOS-transistor of present embodiment has been proposed for the generation that reduces or suppress above-mentioned overlap capacitance.
Fig. 8 A is the perspective view according to the semiconductor device of the 3rd embodiment, and Fig. 8 B is the profile along the line C-C ' of Fig. 8 A.In the present embodiment, between gate electrode 48 and source/drain regions 34, form and comprise the barrier sheet 54 of insulating material, so that reduce or prevent that the overlap capacitance (referring to Fig. 7) between gate electrode 48 and the source/drain regions 34 from increasing.In the present embodiment, represent by identical mark with embodiment 1 components identical.
With reference to figure 8A and 8B, forms active figure 30 on the first type surface of the substrate 10 that is made of the silicon (SOI) on silicon (Si), silicon-germanium (SiGe), the insulator, silicon-germanium (SGOI) on the insulator and/or other conventional substrate/layer, active figure 30 is included in a plurality of raceway groove 44a and the 44b that is vertically formed in the direction that makes progress.Source/drain regions 34 is connected with 44b with a plurality of raceway groove 44a on the both sides of active figure 30.Between source/drain regions 34 and a plurality of raceway groove 44a and 44b, form the source/drain regions extended layer 32 that is connected to source/drain regions 34 and is connected to raceway groove 44 and 44b.
Between each raceway groove 44a and 44b, form a plurality of tunnels 42 that have than the shorter length of channel length.In the bottom surface section of minimum channel layer 44a and Semiconductor substrate, that is, between impurity doped region 12, form minimum tunnel 42a.On the raceway groove 44b that goes up most, form tunnel groove 42c with tunnel-shaped.
Fig. 8 C shows the zoomed-in view of the part " B " among Fig. 8 B.On two sidewalls in tunnel 42 and form the barrier sheet 54 of two insulating barriers on two sidewalls of tunnel groove 42, so that each barrier sheet has corresponding to half poor thickness (d) between the length in the length of raceway groove 44a shown in Fig. 8 C and 44b and tunnel 42.On last active figure 30, form and to run through and/or fill a plurality of tunnel 42a and 42b and tunnel groove 42c and around the gate electrode 48 of a plurality of raceway groove 44a and 44b.Between gate electrode 48 and a plurality of raceway groove 44a and 44b, that is, forming gate insulation layer 46 on the upper surface in tunnel 42 and the lower surface and on the lower surface of the tunnel groove 42 except the sidewall of the sidewall in tunnel and tunnel groove.
In certain embodiments, formation comprises the gate electrode 48 of polysilicon and the grid stack layer 50 that is made of metal silicide on gate electrode 48 top surfaces.Grid stack layer 50 forms around the top of the sidewall of gate electrode 48, makes the gate electrode of otch thus.Form field region 22, so that around the source/drain regions 34 except that the channel region that comprises a plurality of raceway groove 44a and 44b.
Form heavily doped region 12 in the first type surface of the substrate 10 below active figure 30 part, so that reduce or prevent end transistor work.
Fig. 9 A to 9O illustrates the profile that a third embodiment in accordance with the invention is made the method for semiconductor device.With reference to figure 9A, with with identical method shown in Fig. 4 A to 4F of embodiment 1, on substrate 10, form pre-active figure 18 and around the field region 22 of pre-active figure 18, stacked alternately with each other a plurality of interlayer channel layers 14 and a plurality of channel layer 16 in pre-active figure 18.In certain embodiments, interlayer channel layer 14 comprises monocrystalline Ge (comprise, for example, single crystalline Si Ge film), and a plurality of channel layer 16 comprises single crystalline Si film.
Next, on active figure 18, be formed for making the hard mask of grid of drain region, source region autoregistration channel region.The hard mask of grid has stacked continuously etching-stop layer pattern 24, dummy gate figure 26 and anti-reflecting layer figure 28.
Use the hard mask of grid 29 as etching mask, etch away the pre-active figure 18 that exposes, exposed, limit the zone 30 that will form source/drain regions thus up to the surface of substrate 10.By doing like this, only be left the channel region of pre-active figure 18.Further enough execution etching procedure for a long time, with the top of etching semiconductor substrate 10 to the drop shadow spread that is lower than heavily doped region 12.
As a result, as shown in the figure, formation has the active channel figure 18a of the second channel layer figure 16 " and between the second layer raceway groove layer pattern 14 " below the hard mask 29 of grid.Second channel layer figure 16 " by a plurality of second channel layer figure 16a " and 16b " constitute, and raceway groove layer pattern 14 " by a plurality of interlayer channel layer figure 14a " between the second layer, 14b " and 14c " constitutes.
With reference to figure 9B, expose side raceway groove layer pattern 14 between the lateral etching second layer selectively by active channel figure 18a ", form undercut region 31 thus.The width of undercut region 31 is formed up to apart from the sidewall surfaces of original active channel figure 18a about
Figure C20051000572800271
The degree of depth.Thus, by raceway groove layer pattern 14a between a plurality of second layers ", 14b " and 14c " forms shorter a plurality of the 3rd interlayer channel layer figure 15a of length, 15b and the 15c than the second channel layer figure 16a " and 16b ".
With reference to figure 9C, deposition insulating layer 52 is so that form insulating barrier 52 or fill undercut region 31 in the whole lip-deep undercut region 31 of resulting structures.Specifically, by chemical gas-phase deposition method deposition insulating material such as silica, so that fill the undercut region 31 of active channel figure 18a, form the insulating barrier 52 on the whole surface that covers resulting structures thus, promptly comprise the sidewall of active channel figure 18a and the total inner surface of the etched area 30 on surface.
With reference to figure 9D, lose insulating barrier 52 deeply, to form the barrier sheet 54 that constitutes by insulating material of only filling undercut region 31 such as silica.
With reference to figure 9E, identical method shown in Fig. 4 G of usefulness and embodiment 1 at the ground, side top of etched area 30 surfaces and active channel figure 18a growth selectivity epitaxy single-crystal film, forms source/drain regions extended layer 32 thus.
Then, with with identical method shown in Fig. 4 H of embodiment 1, polysilicon, metal or the metal silicide of deposit conductive film as mixing loses conductive film then deeply on the whole surface of the resulting structures that comprises source/drain regions extended layer 32, to form the source/drain regions 34 of filling etched area 30.
Here, before the deposit conductive film, can carry out angle-tilt ion and inject, with source/drain regions extended layer 32 with doping impurity selective epitaxial single crystal film.In addition or additionally, can be by from source/drain regions solid-state diffusion dopant doping source region/drain region extended layer 32 in the subsequent anneal operation.Under the situation of each, source/drain regions extended layer 32 and source/drain regions 34 can have uniform Impurity Distribution in the direction perpendicular to channel region.
With reference to figure 9F, the same method shown in Fig. 4 I of usefulness and embodiment 1, deposit silicon nitride on the active channel figure 18a of source/drain regions 34, channel region and substrate 10 forms thus and covers layer.Then, with the method the same with Fig. 4 J of embodiment 1, smooth mask layer is exposed up to the surface of dummy gate figure 26, forms the mask graph 36 that exposes dummy gate figure 26 thus.
With reference to figure 9G, identical method shown in Fig. 4 K of usefulness and embodiment 1 is removed dummy gate figure 26 selectively by using mask graph 36, forms gate groove 38 thus.Here, etching-stop layer pattern 24 prevents to remove in the etching procedure process of dummy gate figure 26 down that active figure 18a is etched.If the remaining conduction afterbody 34a that is used for source/drain regions can carry out oxidation operation with the method identical with Fig. 4 L of embodiment 1 so below the side of gate figure 26, change the insulating barrier 40 of silica into will conduct electricity afterbody 34a.
With reference to figure 9H, identical method shown in Fig. 4 M of usefulness and embodiment 1 is removed the etching stopping layer pattern 24 that exposes by gate groove 38.If the active channel figure 18a of boron doped channel regions of no use passes through gate groove 38 boron ion implantation partly, so to use the active channel figure 18a of boron doped channel regions thus.In certain embodiments, carry out channel ion and inject, so that at each channel layer 16 " in formation drop shadow spread.Additionally, in certain embodiments, carry out raceway groove boron ion and inject, so that each second channel layer figure 16a " with 16b " has different doping content mutually, the grid voltage that applies of basis operate transistor continuously thus.Do not carry out phosphorus doping.
By chemical gas-phase deposition method silicon oxide deposition on the whole surface of resulting structures, form thus to have and equal or less times greater than the insulating barrier of the same thickness of the width of undercut region 31, for example about
Figure C20051000572800291
Thickness.Then, lose insulating barrier deeply, on the madial wall of gate groove 38, to form insulating barrier partition 56.Insulating barrier partition 56 control channel width and grid widths.
With reference to figure 9I, with and Fig. 4 N of embodiment 1 identical method, use source/drain regions 34 exposes the side of the active channel figure 18a of channel region thus as etching mask etching field region 22 selectively.Then, for example use the poly-etching agent to remove a plurality of the 3rd interlayer channel layer figure 15a selectively by the isotropic etching operation, 15b and 15c form a plurality of tunnel 42a and the 42b that passes active channel figure 18a and be positioned at the tunnel groove 42c of uppermost position in fig-ure thus.Here, the second channel layer figure 16a " and 16b " forms a plurality of raceway groove 44a and 44b.Because the barrier sheet 54 that forms on its sidewall, tunnel 42a and 42b are formed with the length shorter than the horizontal length of raceway groove 44a and 44b.
With reference now to Fig. 9 J,, carries out phosphorus doping to be similar in conjunction with Fig. 4 O describing method.Also can mix as carrying out boron in conjunction with the described method of Fig. 4 O.
With reference to figure 9K, identical method shown in Fig. 4 P of usefulness and embodiment 1 is carried out thermal oxidation process, to form grid-insulating barrier 46 on the surface of raceway groove 44a and 44b (concrete, the upper surface of a plurality of tunnel 42a and 42b and lower surface and tunnel groove 42c basal surface).At this moment, in order to reduce the surface roughness of raceway groove 44a and 44b, before forming grid-insulating barrier 46 at hydrogen (H 2) or argon gas (Ar) atmosphere in high temperature carry out down heat treatment.
With reference to figure 9L, method identical shown in Fig. 4 Q of usefulness and embodiment 2 forms gate electrode 48, so that fill a plurality of tunnel 42a and 42b and tunnel groove 42c, and around a plurality of raceway groove 44a and 44b.In certain embodiments, gate electrode 48 comprises the polysilicon of doping.
With reference to figure 9M, remove insulating barrier partition 56 selectively, with top surface and the partial sidewall of exposing gate electrode 48.That is partition residue 56a remains in the bottom of the sidewall of gate electrode 48.
With reference to figure 9N, with and Fig. 4 R of embodiment 1 shown in identical method, formation grid stack layer 50 on the top surface of the gate electrode 48 that exposes and part upper side wall, grid stack layer 50 has the metal silicide that is used to reduce gate resistance.At this moment, the width of grid stack layer 50 is identical with the length of raceway groove 44a and 44b, and the width of gate electrode 48 is identical with the length in tunnel 42.Thus, form the side of otch grid in the grid stack layer 50 outstanding places of comparing with gate electrode 48.Otch grid side can reduce the contact resistance between gate electrode 48 and the grid stack layer 50.
Next, shown in Fig. 8 B, remove insulating barrier partition 56 and mask graph 36.
A third embodiment in accordance with the invention, gate electrode 48 and/form the barrier sheet 54 that constitutes by insulating material between the drain region 34, reduce the overlap capacitance between gate electrode and the source/drain regions.And, because grid stack layer 50 forms around the partial sidewall of gate electrode 48, so can reduce contact resistance between gate electrode 48 and the grid stack layer 50.
Embodiment 4
Figure 10 is the profile of the device of a fourth embodiment in accordance with the invention.The embodiment of Figure 10 is similar to the embodiment of Fig. 9, except CMOS embodiment is shown.Therefore, at this these embodiment are described in further detail no longer.
Embodiment 5
Figure 11 is the profile of device according to a fifth embodiment of the invention.The 5th embodiment is similar to embodiment 2, except polygate electrodes 48 has the width identical with the grid stack layer 50a that is made of metal silicide.
With forming gate insulation layer 46 with method identical shown in Fig. 9 A to 9J of embodiment 3.After this, form polygate electrodes 48, so that run through and/or fills tunnel 42 and tunnel groove 42c and center on a plurality of raceway groove 44a and 44b.Thus, polygate electrodes 48 is formed with the width identical with the horizontal width of tunnel 42a and 42b.
On polygate electrodes 48, form and comprise after the grid stack layer 50 of metal silicide, remove the insulating barrier partition 56 that forms on the sidewall of gate groove 38.So, grid stack layer 50 is formed with the width identical with gate electrode 48.
With the method identical with embodiment 1, deposit and deep erosion electric conducting material, forming source/drain regions 34, growing epitaxial single crystal film on the side of the active channel figure of channel region is to form the source/drain regions extended layer.In addition, the etched area of active figure is provided with or is filled with epitaxy single-crystal film or electric conducting material as the polysilicon that mixes, metal, metal silicide etc., to form source/drain regions 34 as shown in figure 11 thus.
Embodiment 6
Figure 12 is the profile of device according to a sixth embodiment of the invention.More particularly, Figure 12 illustrates the cmos device of the embodiment 5 that is similar to Figure 11.Therefore, at this these embodiment are described in further detail no longer.
Embodiment 7
Figure 13 A to 13K illustrates the profile of the method for making semiconductor device according to a seventh embodiment of the invention.In the present embodiment, with previous embodiment in components identical represent by identical mark.
With reference to figure 13A, with with identical method shown in Fig. 4 A to 4F of embodiment 1, on Semiconductor substrate 10, form pre-active figure 18 and around the field region 22 of pre-active figure 18, stacked alternately with each other a plurality of interlayer channel layers 14 and a plurality of channel layer 16 in pre-active figure 18.In certain embodiments, interlayer channel layer 14 comprises monocrystalline Ge (comprising, for example single crystalline Si Ge film), and channel layer 16 comprises single crystalline Si film.
Next, on pre-active figure 18, form the hard mask 29 of grid, dummy gate figure 26 and the anti-reflecting layer figure 28 that comprises etching stopping layer pattern 24.
Use the hard mask 29 of grid, etch away the pre-active figure 18 that exposes, exposed, form the zone 30 that will form source/drain regions thus up to the surface of substrate 10.Therefore, on the channel region under the hard mask 29, by shown in pre-active figure 18 form the active channel figure 18a that comprises the second channel layer figure 16 " and between the second layer raceway groove layer pattern 14 ".Second channel layer figure 16 " by a plurality of second channel layer figure 16a " and 16b " constitute, and raceway groove layer pattern 14 " by a plurality of interlayer channel layer figure 14a " between the second layer, 14c " and 14c " constitutes.Further enough execution etching procedure for a long time, with the top of etching semiconductor substrate 10 to the drop shadow spread that is lower than heavily doped region 12.
After this, on the surface of the surface of the inner surface of etched area 30, active channel figure 18a and field region 22, form and comprise with respect to field region 22 having the material of etching selection rate such as the oxidation barrier layer 58 of silicon nitride.
With reference to figure 13B, oxidation barrier layer 58 is anisotropically etched away, only on the inboard of the sidewall of active channel figure 18a and etched area 30, to form anti-oxidant partition 58a, the surface 59 of exposing the Semiconductor substrate 10 of etched area 30 simultaneously, the i.e. bottom of source/drain regions.
With reference to figure 13C, by the exposing surface of thermal oxidation process oxidation substrate 59, only on the bottom of source/drain regions, to form the insulating barrier figure 60 that constitutes by silica.With reference to figure 13D, peel off by wet etching operation such as phosphoric acid and to remove anti-oxidant partition 58a selectively.With reference to figure 13E, with and Fig. 4 G of embodiment 1 shown in identical method, on the side top of etched area 30 surfaces and active channel figure 18a growth selectivity epitaxy single-crystal film with formation source/drain regions extended layer 32a.
Then, with with identical method shown in Fig. 4 H of embodiment 1, the deposit conductive film is as polysilicon, metal or metal silicide of mixing or the like on the whole surface of the resulting structures that comprises source/drain regions extended layer 32a, lose conductive film then deeply, to form the source/drain regions 34a that fills etched area 30.At this moment, growing epitaxial single crystal film thickly on the side of active channel figure 18a is because it only is grown on the silicon area of removing insulating barrier figure 60.Thus, opposite with embodiment 1 to 5, below the sidewall of dummy gate figure 26, can not residually be used for the afterbody 34a of the conductive film of source/drain regions.
Here, before the deposit conductive film, can carry out angle-tilt ion and inject, with the source/drain regions extended layer 32 that constitutes by the selective epitaxial single crystal film with doping impurity.In addition or additionally, can be by from source/drain regions solid-state diffusion dopant doping source region/drain region extended layer 32 in the subsequent anneal operation.In both cases, source/drain regions extended layer 32a and source/drain regions 34a can have uniform Impurity Distribution in perpendicular to the direction of channel region.
With reference to figure 13F, the shown in Figure 41 the same method of usefulness and embodiment 1, deposit silicon nitride on the active channel figure 18a of source/drain regions 34a, channel region and substrate 10 forms thus and covers layer.Then, smooth mask layer is exposed up to the surface of dummy gate figure 26, forms the mask graph 36 that exposes dummy gate figure 26 thus.
With reference to figure 13G, identical method shown in Fig. 4 K of usefulness and embodiment 1 is removed dummy gate figure 26 selectively by using mask graph 36, forms gate groove 38 thus.Then, be similar to Fig. 4 M, remove the etching stopping layer pattern 24 that exposes by gate groove 38.If the raceway groove figure 18a of channel region does not have doped with boron, can pass through gate groove 38 boron ion implantation partly so, to use the active channel figure 18a of boron doped channel regions thus.In certain embodiments, use the channel ion of boron to inject, so that at each channel layer 16 " in formation drop shadow spread.Additionally, in other embodiments, the channel ion of carrying out with boron injects, so that each second channel layer 16 " has different doping content mutually, operates the transistor of acquisition thus according to the grid voltage that applies continuously.Note not carrying out this moment phosphorus doping.
With reference to figure 13H, with and Fig. 4 N of embodiment 1 identical method, use source/drain regions 34a exposes the side of the active channel figure 18a of channel region thus as etching mask etching field region 22 selectively.By the isotropic etching operation, remove a plurality of interlayer channel layer figure 14a selectively ", 14b " and 14c " forms a plurality of tunnels 42 and the 42b that passes active channel figure 18a and be positioned at the tunnel groove 42c of uppermost position in fig-ure thus.At this moment, the second channel layer figure 16a " and 16b " forms a plurality of raceway groove 44a and 44b.Can use the poly-etching agent.
With reference to figure 13I, then as injection phosphorus as described in conjunction with Figure 40.If wish, also can inject boron, as describing in conjunction with Figure 40.
With reference to figure 13J, identical method shown in Fig. 4 P of usefulness and embodiment 1 is carried out thermal oxidation process, to form grid-insulating barrier 46 on the surface of raceway groove 44a and 44b (concrete, as to comprise a plurality of tunnel 42a and 42b).At this moment, in order to reduce the surface roughness of raceway groove 44a and 44b, before forming grid-insulating barrier 46 at hydrogen (H 2) or argon gas (Ar) atmosphere in high temperature carry out down heat treatment.
Then, with and Fig. 4 Q of embodiment 1 shown in identical method form polygate electrodes 48 so that run through and/or fill a plurality of tunnel 41a and 41b and tunnel groove 41c, and center on a plurality of raceway groove 44a and 44b.On the top of polygate electrodes 48, form the grid stack layer 50 comprise the metal silicide that is used to reduce gate resistance.
With reference to figure 13k, identical method shown in Fig. 4 S of usefulness and embodiment 1 is removed mask graph 36, carries out subsequent handling such as metal interconnected then, to finish vertical MOS-transistor.
According to a seventh embodiment of the invention, on the bottom of source/drain regions, form insulating barrier figure 60, to reduce the source/drain regions junction capacitance thus.
Embodiment 8
Figure 14 is the sectional side view according to the eighth embodiment of the present invention.Figure 14 is similar to the CMOS embodiment of Figure 13 A-13K.In these embodiments, after forming the tunnel, use phosphorus doping P-MOS transistor.Before forming the tunnel and/or afterwards with the boron doping N-MOS and the P-MOS raceway groove that optionally mixes.Thus, there is no need the description that provides additional.
Embodiment 9
Figure 15 is the profile according to the device of the ninth embodiment of the present invention.In the present embodiment, with other embodiment in components identical represent by identical mark.
In the present embodiment, after carrying out operation, etch away pre-active figure 18, to form the etched area 30 that will form source/drain regions and active channel figure 18a with the method identical with Fig. 4 A to 4F.Then, fill etched area 30, to form source/drain regions 34 with the selective epitaxial single crystal film.Next, use and method identical shown in Figure 41 to 4S, carry out subsequent handling, to form semiconductor device.
Thus, present embodiment is similar to embodiment 1, does not have to form the source/drain regions 34 of additional source/drain regions extended layer to form except fully fill etched area 30 by epitaxy method.
In the present embodiment, can between gate electrode 48 and source/drain regions 34, form the barrier sheet 54 that comprises insulating material by the method shown in 3 or 5 in conjunction with the embodiments.And, can be by on the bottom of source/drain regions 34, forming insulating barrier 60 in conjunction with the method shown in embodiment 7.
Embodiment 10
Figure 16 is the profile according to the semiconductor device of the tenth embodiment of the present invention.In the present embodiment, with previous embodiment in components identical represent by identical mark.
The semiconductor device of present embodiment is similar to embodiment 9, wherein pre-active figure 18 is etched away, be formed for the etched area 30 and the active channel figure 18a of source/drain regions with identical method shown in Fig. 4 A to 4F of usefulness and embodiment 1, except the deposit conductive film as the polysilicon that mixes, metal, metal silicide etc., erosion deeply then, on etched area 30, to form source/drain regions 34, replace using shown in embodiment 9 the selective epitaxial single crystal film to fill outside the etched area 30.
In the present embodiment, can be unnecessary with forming additional source/drain regions extended layer with embodiment 9 identical methods.And, can by in conjunction with the embodiments 3, the method shown in embodiment 5 or the embodiment 7 obtains to have the vertical MOS-transistor of a plurality of raceway grooves.
Embodiment 11
Figure 17 is the profile of semiconductor device according to a seventh embodiment of the invention.Be different from the semiconductor device shown in the embodiment 9 except constitute the interlayer channel layer of active figure and the thickness of channel layer and the number of repetition number raceway groove 44 and the thickness in tunnel by control, the semiconductor device of present embodiment is similar to embodiment 9.
Embodiment 12
Figure 18 is the profile according to the semiconductor device of the eighth embodiment of the present invention.With on the oxide skin(coating) 70 of SOI substrate, forming the semiconductor device of present embodiment with embodiment 9 or embodiment 10 identical methods.
Specifically, vertical MOS-transistor with active channel figure is provided, comprise a plurality of raceway groove 44a on the oxide skin(coating) 70 of SOI substrate, 44b and 44c, the SOI substrate has the tunnel that inserts between each raceway groove that forms, source/drain regions 34, so as with a plurality of raceway groove 44a of the both sides of active channel figure, 44b and 44c are connected with gate electrode 48 on being formed on the active channel figure, so that run through or fill the tunnel and around a plurality of raceway groove 44a, 44b and 44c.
Can be by obtaining vertical MOS-transistor in conjunction with the method shown in other previous embodiment.The SOI substrate has following Semiconductor substrate (not shown) and the buried oxide layer 70 that forms is known on substrate concerning the those skilled in the art.
In the present embodiment, the stacked alternately with each other a plurality of channel layers that comprise a plurality of interlayer channel layers of monocrystalline Ge (comprising, for example single crystalline Si Ge film) and comprise single crystalline Si film on buried oxide layer 70.Then, a plurality of interlayer channel layers of composition and a plurality of channel layer are to form pre-active figure.
Embodiment 13
The semiconductor device of ninth embodiment of the present invention present embodiment is similar to the semiconductor device shown in Figure 15 of embodiment, except the thickness (t) in the minimum tunnel that is filled with gate electrode 48 forms thicker so that reduce or prevent the parasitic transistor operation of minimum raceway groove 44a than other tunnels.Identical mark is represented components identical.
Specifically, in by the operation shown in Fig. 4 B in the reference example 1, when stacked alternately with each other a plurality of interlayer channel layers 14 and a plurality of channel layer 16 on Semiconductor substrate 10, the thickness (t) of minimum interlayer channel layer 14a forms thicker than the thickness of other interlayer channel layer 14b and 14c.With the method identical with Fig. 4 D to 4F of embodiment 1, the a plurality of interlayer channel layers 14 of composition and a plurality of raceway groove 16, to form pre-active figure 18, etch away pre-active figure 19 then, up to the surface of exposing substrate 10, limit the zone that will form source/drain regions thus, form the active channel figure 18a that comprises interlayer channel layer figure and channel layer figure simultaneously.
With the method identical with embodiment 9, growing epitaxial single crystal film, so that fill etched area, source/drain regions 34 is formed thus at the top of up between the lower floor channel layer of mixing then.Subsequent handling is similar to the foregoing description.
Embodiment 14
Figure 20 A to 20F illustrates the profile of making the method for semiconductor device according to the 14th embodiment of the present invention.
With reference to figure 20A, with with identical method shown in Fig. 4 A to 4F of embodiment 1, on substrate 10, form pre-active figure 18 and around the field region 22 of pre-active figure 18, stacked alternately with each other a plurality of interlayer channel layers 14 and a plurality of channel layer 16 in pre-active figure 18.In certain embodiments, a plurality of interlayer channel layers 14 comprise monocrystalline Ge (comprising, for example single crystalline Si Ge film), and a plurality of channel layer 16 comprises single crystalline Si film.
After this, with and embodiment 1 in Fig. 4 D and method identical shown in the 4E, formation comprises the hard mask 29 of grid of virtual gate figure (not shown) on pre-active figure.
With with identical method shown in Fig. 4 F of embodiment 1, use hard mask 29 to etch away pre-active figure 18, exposed up to the surface of substrate 10, form the zone 30 that will form source/drain regions thus.As a result, only the pre-active figure 18 of channel region is remaining.
Then, identical method shown in Fig. 4 G of usefulness and embodiment 1 at the side of pre-active figure 18 and ground, the exposing surface top growth selectivity epitaxy single-crystal film of substrate 10, forms source/drain regions extended layer 32 thus.Can carry out angle-tilt ion and inject, to use doping impurity source region/drain region extended layer 32.
Next, shown in Figure 20 A, deposit silicon nitride on the whole surface of resulting structures is to form first insulating barrier 62.Specifically, on the whole surface of the substrate that comprises field region 22 and source/drain regions extended layer 32, form by the insulating material that has the etching selection rate with respect to pre-active figure 18 and field region 22 first insulating barrier 62 that constitutes of silicon nitride for example.
With reference to figure 20B, deposit second insulating barrier 64 on first insulating barrier 62 is so that in certain embodiments, be filled in the zone that will form source/drain regions between source/drain regions extended layer 32 and the field region 22 fully.Second insulating barrier 64 comprises the material that has the etching selection rate with respect to first insulating barrier 62.In certain embodiments, second insulating barrier 64 by with constitute field region 62 identical materials for example silica constitute.
With reference to figure 20C, second insulating barrier 64 is etched to minimum tunnel deeply, forms the second insulating barrier figure 64a thus on the bottom in the zone that will form source/drain regions.
With reference to figure 20D, use the second insulating barrier figure 64a as etching mask, lose first insulating barrier 62 deeply, with the formation first insulating barrier figure 62a below each second insulating barrier figure 64a.
With reference to figure 20E, the zone that will form source/drain regions between field region 22 and source/drain regions extended layer 32 is provided with or is filled with conductive film as the polysilicon that mixes, metal, metal silicide etc., forms source/drain regions 34 thus.
Next, with the method identical, shown in Figure 20 F, make semiconductor device with Figure 41 to 4S of embodiment 1.
According to present embodiment, on the bottom of source/drain regions 34, form the insulating barrier stepped construction that comprises the first insulating barrier figure 62a and the second insulating barrier figure 64a, this can reduce source/drain junction capacitance.
Embodiment 15
These embodiment are similar to the embodiment 14 of Figure 20 A-20F, except CMOS embodiment is shown.As described in conjunction with previous CMOS embodiment, after having formed the tunnel, p channel transistor is not mixed with phosphorus.The N channel device can mix with boron, and optionally before forming the tunnel and/or afterwards P-channel device can mix with boron.Thus, the additional of these embodiment there is no need to be described in detail.
Embodiment 16
Figure 22 A to 22E illustrates according to the semiconductor device of the 16th embodiment of the present invention and the profile of manufacture method thereof.In the present embodiment, with previous embodiment in components identical represent by identical mark.
With reference to figure 22A, for example, by chemical gas-phase deposition method, on the Semiconductor substrate 10 that constitutes by the silicon (SOI) on silicon (Si), silicon-germanium (Si-Ge), the insulator, silicon-germanium (SGOI) on the insulator and/or other conventional substrate/layer, form oxide skin(coating) 80.
With reference to figure 22B, on oxide skin(coating) 80, apply photoresist film, expose then and develop, to form the photoresist figure 82 that opening will form the regional M of a plurality of raceway grooves.
Then, use photoresist figure 82 as mask, dry etching falls oxide skin(coating) 80, to form the oxide skin(coating) figure 80a that limits a plurality of channel region M and a channel region S.That is oxide skin(coating) figure 80a only remains on the typical single channel region S.
Then, the impurity that the substrate surface intermediate ion injects the conduction type identical with substrate 10 that exposes at a plurality of channel region M forms the heavily doped region 12 that can reduce or prevent that the end transistor from operating thus.
With reference to figure 22c, remove photoresist figure 82 by ashing and stripping technology.Then, by the selective epitaxial growth method, on the zone of removing oxide skin(coating) figure 80a, that is, and stacked alternately with each other a plurality of interlayer channel layers 14 and a plurality of channel layer 16 on the substrate surface of a plurality of channel region M.
Specifically, on the surface of the substrate 10 of removing oxide skin(coating) figure 80a selectively growing single-crystal Ge epitaxial film (comprise, for example, single crystalline Si-Ge epitaxial film) to approximately
Figure C20051000572800401
Thickness, form channel layer 14a between ground floor thus.Then, growth has the single crystalline Si epitaxial film of about 300A thickness on channel layer 14a between ground floor, forms the first channel layer 16a thus.Here, in order to carry out channel doping in advance, channel layer 16 can be formed by boron doped single crystalline Si epitaxial film.But, phosphorus doping is not provided.
By doing like this, growing epitaxial film not on single channel region S, and on a plurality of channel region M, form the pre-active figure 18 of wherein stacked alternately with each other a plurality of interlayer channel layers 14 and a plurality of channel layer 16.If wish, can carry out boron and mix.But, do not carry out phosphorus doping.
With reference to figure 22D, remove interlayer channel layer 14, so that a plurality of tunnel layer 42a-42c to be provided.Then, shown in Figure 22 E, after forming tunnel 42, use ion to inject and/or the plasma doping Doping Phosphorus.If wish this moment, also can doped with boron.At last, use and identical method shown in the previous embodiment, carry out subsequent handling, to form semiconductor device.
Embodiment 17
Figure 23 A-23C illustrates the 17th embodiment of the present invention.Figure 23 A illustrates according to previous arbitrary embodiment up to forming tunnel 542a, the process of 542b and 542c.After forming tunnel 542, shown in Figure 23 E, boron is impregnated in N channel region 544 ' and optionally mix the P channel region.At last, shown in Figure 23 C, use ion to inject and/or plasma doping in P channel region 544 Doping Phosphorus, and with carrying out subsequent handling, with the formation semiconductor device with identical method shown in the previous embodiment.
According to aforesaid some embodiment of the present invention, form a plurality of thin channels by an active figure, and gate electrode forms around raceway groove.Because stacked a plurality of thin channel vertically, therefore compare and to reduce the area that occupies by channel region and source/drain regions with conventional fin type MOS transistor.
And in certain embodiments of the present invention, source/drain regions forms has uniform Impurity Distribution in the direction perpendicular to a plurality of raceway grooves, although so that the numeral of raceway groove and area increase, can keep uniform source/drain junction capacitance.Therefore, although reduce or minimum junction capacitance, electric current can increase, to improve device speed.
According to some embodiment of the present invention, with after forming active figure, the zone that forms the active figure of source/drain regions is etched away at alternately stacked a plurality of channel layer and a plurality of interlayer channel layer.In certain embodiments, fill etched area, to form source/drain regions with epitaxy single-crystal film or electric conducting material.Because the horizontal length of interlayer channel layer may be limited in the length areas of grid, therefore when anisotropically channel layer is with the formation tunnel between etch layer in subsequent handling, can prevent the tunnel horizontal-extending.So, can realize having the integrated MOS transistor of height less than the gate length of channel width.
At last, according to some embodiment of the present invention, after being removed selectively, the interlayer channel layer do not carry out phosphorus doping.Thus, conventional multiple Wet-etching agent can be used for removing selectively the interlayer channel layer.After removing a plurality of interlayer channel layers selectively, use the phosphorus doping raceway groove.Thus, but the manufacturing process that can use conventional etchant can be provided.
Can interosculate in the aspect that is to be understood that one or more embodiment of the present invention, to obtain to have the integrated vertical MOS-transistor of height of a plurality of raceway grooves.
In drawing and description, general preferred embodiment of the present invention is disclosed, although used proprietary term, they only are used for generality and descriptive sense, are not to be used for restriction, scope of the present invention will be set forth in the claim below.

Claims (21)

1. method of making integrated circuit field effect transistor devices comprises:
Form pre-active figure on the surface of substrate, avoid simultaneously with the pre-active figure of phosphorus doping, pre-active figure comprises channel layer and channel layer between stacked alternately with each other series of layers;
On the substrate at place, the opposite end of pre-active figure, form source/drain regions;
Remove a plurality of interlayer channel layers selectively, pass a plurality of tunnels of pre-active figure, limit active channel figure that comprises the tunnel and a plurality of raceway grooves that comprise channel layer thus with formation;
After removing a plurality of interlayer channel layers selectively, use the phosphorus doping raceway groove; And
In the tunnel and around raceway groove, form gate electrode.
2. method according to claim 1, wherein integrated circuit field effect transistor devices is a P raceway groove integrated circuit field effect transistor devices.
3. method according to claim 1, wherein channel layer comprises monocrystalline silicon, and wherein the interlayer channel layer comprises monocrystalline silicon-germanium.
4. according to the process of claim 1 wherein that using the poly-etching agent to carry out selectively removes.
5. according to the process of claim 1 wherein that using ion to inject carries out channel doping.
6. use plasma doping to carry out channel doping according to the process of claim 1 wherein.
7. method according to claim 1 wherein forms gate electrode and comprises the gate electrode that forms the filling tunnel and center on raceway groove.
8. method according to claim 1, wherein substrate comprises silicon (SOI) on silicon, silicon-germanium, the insulator or the silicon-germanium (SGOI) on the insulator.
9. method according to claim 1 is wherein used the isotropic etching operation to carry out selectively and is removed.
10. make integrated circuit N raceway groove and the transistorized method of P-channel field-effect transistor (PEFT) for one kind, comprising:
Surface at substrate forms pre-active figure of N raceway groove and the pre-active figure of P raceway groove, avoid simultaneously with phosphorus doping N raceway groove and the pre-active figure of P raceway groove, the pre-active figure of each N raceway groove and P raceway groove comprises channel layer and each N channel layer and P channel layer between stacked alternately with each other series of layers;
Place, opposite end at each N raceway groove and the pre-active figure of P raceway groove forms source/drain regions on substrate;
Remove a plurality of interlayer channel layers selectively, pass a plurality of tunnels of N raceway groove and the pre-active figure of P raceway groove, limit each active N raceway groove and P raceway groove figure that comprises the tunnel and a plurality of each N raceway groove and the P raceway groove that comprises channel layer thus with formation;
After removing a plurality of interlayer channel layers selectively,, after removing a plurality of interlayer channel layers selectively, avoid N raceway groove simultaneously with the active N raceway groove of phosphorus doping figure with the P raceway groove of the active P raceway groove of phosphorus doping figure; And
In the tunnel and around N raceway groove and P raceway groove, form gate electrode.
11. method according to claim 10 is wherein carried out following operation after removing a plurality of interlayer channel layers selectively:
With the mix N raceway groove of active N raceway groove figure of boron, avoid simultaneously with the mix P raceway groove of active P raceway groove figure of boron.
12. method according to claim 10 was wherein carried out following operation before removing a plurality of interlayer channel layers selectively:
With the N channel layer of the pre-active figure of boron doping N raceway groove, avoid P channel layer simultaneously with the pre-active figure of boron doping P raceway groove.
13. method according to claim 10 is wherein carried out following operation after removing a plurality of interlayer channel layers selectively:
With boron mix the N raceway groove of active N raceway groove figure and the P raceway groove of active P raceway groove figure.
14. method according to claim 10 was wherein carried out following operation before removing a plurality of interlayer channel layers selectively:
With boron mix the N channel layer of the pre-active figure of active N raceway groove and the P channel layer of the pre-active figure of P raceway groove.
15. method according to claim 10, wherein channel layer comprises monocrystalline silicon, and wherein the interlayer channel layer comprises monocrystalline silicon-germanium.
16. method according to claim 10 is wherein used the poly-etching agent to carry out selectively and is removed.
17. method according to claim 10 is wherein used ion to inject and is carried out the P channel doping.
18. method according to claim 10 wherein uses plasma doping to carry out the P channel doping.
19. method according to claim 10 wherein forms gate electrode and comprises the gate electrode that forms the filling tunnel and center on N raceway groove and P raceway groove.
20. method according to claim 10, wherein substrate comprises silicon (SOI) on silicon, silicon-germanium, the insulator or the silicon-germanium (SGOI) on the insulator.
21. method according to claim 10 is wherein used the isotropic etching operation to carry out selectively and is removed.
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