CN101740618B - Metal-semiconductor field effect transistor - Google Patents

Metal-semiconductor field effect transistor Download PDF

Info

Publication number
CN101740618B
CN101740618B CN200810202458XA CN200810202458A CN101740618B CN 101740618 B CN101740618 B CN 101740618B CN 200810202458X A CN200810202458X A CN 200810202458XA CN 200810202458 A CN200810202458 A CN 200810202458A CN 101740618 B CN101740618 B CN 101740618B
Authority
CN
China
Prior art keywords
metal
field effect
effect transistor
semiconductor field
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN200810202458XA
Other languages
Chinese (zh)
Other versions
CN101740618A (en
Inventor
肖德元
季明华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN200810202458XA priority Critical patent/CN101740618B/en
Publication of CN101740618A publication Critical patent/CN101740618A/en
Application granted granted Critical
Publication of CN101740618B publication Critical patent/CN101740618B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The invention relates to a metal-semiconductor field effect transistor, which comprises a grid electrode formed by metal, and a trench area which is made of a semiconductor material and is in Schottky contact with the grid electrode; the grid electrode is provided with a through hole inside; and at least part of the trench area is positioned in the through hole. Compared with the prior art, the meal grid electrode completely enclosing a trench area is formed in the metal-semiconductor field effect transistor so as to fully prevent the generation of leakage current.

Description

Metal-semiconductor field effect transistor
Technical field
The present invention relates to the manufacturing field of semiconductor device, relate in particular to a kind of structure of metal-semiconductor field effect transistor.
Background technology
(Metal-Semiconductor-Field-Effect-Transistor MESFET) is a kind of common transistor to metal-semiconductor field effect transistor, uses in a large number in the semiconductor device in modern times.MESFET has and mos field effect transistor (Metal-Oxide-Semiconductor-Field-Effect-Transistor, MOSFE) similar I-E characteristic.Yet in the grid part of device, MESFET utilizes metal-semiconductor Schottky contacts to replace the MOS structure of MOSFET; And in source electrode and drain electrode part, MESFET replaces the p-n junction among the MOSFET with ohmic contact.MESFET is the same with other fieldtron, when high electric current, has negative temperature coefficient, and promptly the rising electric current along with temperature descends on the contrary.Therefore even use large-sized active device or with many devices and connect when using, but still maintaining heat is stable.In addition, because MESFET can have the compound semiconductor manufacturing of high electron mobility with GaAs, InP etc., therefore have switching speed and the cut-off frequency higher than silica-based MOSFET.The basis of MESFET structure is gold half contact, and it is equivalent to the p-n junction of monolateral sudden change on electrical characteristics, yet when work, it has the quick response that majority carrier device is enjoyed.
Publication number is that the Japan Patent of JP10070139 discloses that a kind of (Silicon-On-Insulator SOI) is the MESFET structure of substrate with silicon-on-insulator.The simplified structure of this MESFET is as shown in Figure 1; Comprise insulator 101; Lightly-doped silicon raceway groove 102 on insulator 101, the heavily doped silicon source region 106 and the drain region 104 of raceway groove 102 both sides, the metal source 107 that is connected with source region 106; The metal-drain 105 that is connected with drain region 105, and the metal gates 103 that is positioned at raceway groove 102 tops and is attached thereto.Wherein metal source 107 is an ohmic contact with heavily doped silicon source region 106, and metal-drain 105 also is an ohmic contact with heavily doped silicon drain region 105, but metal gates 103 is a Schottky contacts with lightly-doped silicon raceway groove 102.So-called ohmic contact is meant the current-voltage characteristic curve that has linearity and symmetry between the metal that is in contact with one another and the semiconductor.And Schottky contacts is meant that current-voltage characteristic curve is a nonlinear curve between the metal that is in contact with one another and the semiconductor.
Adopt the MESFET of said structure can produce leakage current, particularly when size of semiconductor device was more and more littler, it is more and more obvious that this leakage current just becomes.
Summary of the invention
Technical problem to be solved by this invention is that a kind of metal-semiconductor field effect transistor of leakage current is provided.
For solving the problems of the technologies described above; The present invention provides a kind of metal-semiconductor field effect transistor; Comprise the grid that forms by metal and form the channel region that forms by semi-conducting material of Schottky contacts that be provided with through hole in the said grid, said channel region part at least is positioned at said through hole with grid.
Alternatively, said metal-semiconductor field effect transistor is formed at silicon-on-insulator substrate.
Alternatively, described semi-conducting material comprises Si, Ge, SiGe, GaAs, InP, InAs or InGaAs.
Alternatively, also comprise the source region and the drain region that link with said channel region, said channel region, source region and drain region are mixed with the impurity of identical conduction type.
Alternatively, the doping content in said source region and drain region is greater than the doping content of said channel region.
Alternatively, said grid is formed by simple substance or any two or more lamination or the alloys of W, Al, Ag, Au, Cr, Mo, Ni, Pd, Ti or Pt.
Alternatively, the length of said channel region is 5nm to 50nm.
Alternatively, said channel region is a cylinder.
Alternatively, also comprise with said source region and form the metal source of ohmic contact and form the metal-drain of ohmic contact with said drain region.
The ion concentration of mixing in the said channel region alternatively, is 1 * 10 18Cm -3To 5 * 10 18Cm -3
Compared with prior art, the present invention forms a full metal gates that surrounds channel region in metal-semiconductor field effect transistor, can prevent the generation of leakage current comprehensively.
Description of drawings
Fig. 1 is a prior art metal-semiconductor field effect transistor structural representation;
Fig. 2 is an one embodiment of the invention metal-semiconductor field effect transistor structural representation;
Fig. 3 is the III-III ' cutaway view of Fig. 2;
Fig. 4 is the transfer characteristic curve exemplary plot of one embodiment of the invention metal-semiconductor field effect transistor;
Fig. 5 is the curve of output exemplary plot of one embodiment of the invention metal-semiconductor field effect transistor;
Fig. 6 is an one embodiment of the invention metal-semiconductor field effect transistor manufacturing approach flow chart;
Fig. 7 to Figure 12 is a sketch map of making metal-semiconductor field effect transistor according to flow process shown in Figure 6.
Embodiment
Below in conjunction with accompanying drawing particular content of the present invention is done detailed description.
As shown in Figures 2 and 3, present embodiment provides a kind of metal-semiconductor field effect transistor 201, comprises the metal gates 202 and the columniform semiconductor material pillar 203 (with reference to figure 8) that are formed by metal.It is source region 204, channel region 205 and the drain region 206 of this metal-semiconductor field effect transistor 201 successively that semiconductor material pillar 203 passes through.Be provided with through hole 207 in the metal gates 202, and channel region 205 being positioned at through hole 207, also is that metal gates 202 forms the parcel of channel region 205 is exposed source region 204 and drain region 206.The length of channel region 205 is 5nm to 50nm.Accordingly, the length of metal gates 202 is smaller or equal to the length of channel region 205.Above-mentioned metal gates 202 contacts with metal-semiconductor between the channel region 203 and is Schottky contacts.
In the present embodiment, adopting columniform semiconductor material pillar 203 is preferred embodiments, and the radial cross-section that one skilled in the art will appreciate that semiconductor material pillar 203 is that other shapes also can realize the object of the invention.
In addition, this metal-semiconductor field effect transistor 201 also comprises the metal material source electrode 208 that contacts with source region 204, and the metal material that contacts with drain region 206 drain electrode 209.Here, source region 204 and source electrode 208 contact and drain region 206 is an ohmic contact with contacting of drain electrode 209.
In order to realize that the metal gates 202 and the electricity of source electrode 208 and drain electrode 209 isolate, can also near the two ends of source electrode 208 and drain electrode 209 gate isolation 210 be set at metal gates 202.The shape of gate isolation 210 and material have been that prior art is disclosed, repeat no more at this.
The semi-conducting material of making semiconductor material pillar 203 comprises Si, Ge, SiGe, GaAs, InP, InAs or InGaAs etc.
And metal gates 202 forms by the simple substance of W, Al, Ag, Au, Cr, Mo, Ni, Pd, Ti or Pt, also can be formed by any two or more laminated construction or the alloy in the aforementioned metal.
Select for use the reason of above-mentioned metal and semi-conducting material to be, when above-mentioned metal and semi-conducting material were contacted, the semiconductor energy band bending at metal-semiconductor contact interface place formed Schottky barrier, thereby embodied the asymmetry of I-V curve.The existence of this Schottky barrier has caused big interface resistance.Such metal-semiconductor contact promptly is the Schottky contacts of wanting required for the present invention.Certainly; Above-mentioned metal material and semi-conducting material only are examples; Those skilled in the art will know that; Also have other metal material and semi-conducting material also can form Schottky contacts, such metal material and semi-conducting material also can be used and form metal gates 202 and semiconductor material pillar 203 in the present invention.
Metal-semiconductor field effect transistor 201 can be formed at silicon-on-insulator (SOI) substrate.Such substrate is through enclosing the dielectric layer of imbedding of an insulation between two-layer silicon substrate, thereby active transistor unit is isolated each other.The above-mentioned material of imbedding dielectric layer is oxide normally, therefore will imbed again dielectric layer be called imbed oxide skin(coating) (Buried Oxide, BOX).Imbed dielectric layer and can make electronics flow to another transistor gate effectively, do not allow unnecessary electronics to leak on lower floor's silicon substrate from a transistor gate.Advantages such as the semiconductor device that forms with the SOI substrate has that parasitic capacitance is little, short-channel effect is little, speed is fast, integrated level is high, low in energy consumption, high temperature resistant and radioresistance.
Though above-mentioned source region 204, channel region 205 and drain region 206 are formed in the same semiconductor material pillar 203, also to mix with same impurity, the concentration of mixing is different.The doping content in source region 204 and drain region 206 is greater than the doping content of channel region 205.This is because channel region 205 need form Schottky contacts with metal gates 202, too big impurity concentration can not be arranged, and source region 204 need form ohmic contact with source electrode 208 and drain electrode 209 with drain region 206, needs bigger impurity concentration.The ion concentration of mixing in the channel region 205 can be 1 * 10 18Cm -3To 5 * 10 18Cm -3And the doping content in source region 204 and drain region 206 can be mixed with reference to doping content well-known to those skilled in the art.When metal-semiconductor field effect transistor 1 need be manufactured into the P transistor npn npn, adulterant impurity can be B+ etc., and when metal-semiconductor field effect transistor 1 need be manufactured into the N transistor npn npn, adulterant impurity can be As+ etc.
The above-mentioned metal-semiconductor field effect transistor 201 that present embodiment provides has following I-V characteristic:
I D = π μ n ( e N d ) 2 L ϵ s [ ( 1 4 w 2 4 - 2 3 a w 2 3 + 1 2 a 2 w 2 2 ) - ( 1 4 w 1 4 - 2 3 a w 1 3 + 1 2 a 2 w 1 2 ) ]
Wherein w 1 = 2 ϵ s ( V Bi + V G ) e N d , w 2 = 2 ϵ s ( V Bi + V G + V D ) e N d
In following formula, I DFor draining 209 current strength, w 1Be the depletion width of channel region 205 near source region 204 1 ends, w 2Be the depletion width of channel region 205 near drain region 206 1 ends, a is the radius of columniform semiconductor material pillar 203, μ nBe electron mobility, e is an electron charge, N d Be channel region 205 doping contents, L is a grid length, ε sBe semiconductor dielectric constant, V DFor being applied to the voltage of drain electrode on 209, and V GFor being applied to the voltage on the metal gates 202, V BiBe the interior electromotive force of building.
Work as V D=50mV, and when adopting following canonical parameter and constant, can draw the transfer characteristic curve of metal-semiconductor field effect transistor 201, i.e. I D-V GCurve is as shown in Figure 4: a=10nm, L=10nm, N d=5 * 10 18Cm -3, μ n=1350cm 2/ (V.s), e=1.6 * 10 -19C, ε s=11.7, V Bi=0.445V.
Same above-mentioned canonical parameter and the constant of adopting can draw V GCurve of output when being respectively 0.2V, 0.3V and 0.4V, i.e. I D-V DCurve is as shown in Figure 5.
In addition, present embodiment also provides the manufacturing approach of above-mentioned metal-semiconductor field effect transistor, and is as shown in Figure 6, comprises step:
S101 provides substrate, and said substrate is provided with imbeds dielectric layer and said first semiconductor material layer of imbedding on the dielectric layer;
S102 carries out light dope to described first semiconductor material layer;
S103, said first semiconductor material layer of etching with imbed dielectric layer, form semiconductor material pillar and dielectric support post;
S104, the stage casing of removing said dielectric support post makes the stage casing of dielectric support post form hollow out;
S105, it is 1000 to 1200 ℃ thermal anneal process that said semiconductor material pillar is carried out temperature;
S106, depositing metal layers is extremely buried said semiconductor material pillar at least on said substrate, and fills the hollow out place of said dielectric support post;
S107, the said metal level of etching forms metal gates;
S108 forms separator on the sidewall of said metal gates;
S109 carries out heavy doping to said semiconductor material pillar exposed part at both ends, forms source region and drain region;
S110, forming is respectively the metal source and the metal-drain of ohmic contact with source region and drain region.
To combine accompanying drawing that the manufacturing approach of above-mentioned metal-semiconductor field effect transistor is elaborated below.
At first execution in step S101 provides substrate 220 as shown in Figure 7.Substrate shown in Figure 7 also is aforesaid SOI substrate, comprises first semiconductor material layer 223, imbeds the dielectric layer 222 and second semiconductor material layer 221.Wherein, first semiconductor material layer 223 and 221 clampings of second semiconductor material layer are imbedded dielectric layer 222 and are formed the sandwich laminated construction.Wherein, the thickness of first semiconductor material layer 223 can be 10nm to 150nm, and the thickness of imbedding dielectric layer 222 can be 100nm to 300nm.Imbed dielectric layer 222 and can prevent effectively that unnecessary electronics from leaking into second semiconductor material layer 221 from first semiconductor material layer 223; Thereby advantages such as the semiconductor device that forms above that has that parasitic capacitance is little, short-channel effect is little, speed is fast, integrated level is high, low in energy consumption, high temperature resistant and radioresistance.
Used first semiconductor material layer 223 and second semiconductor material layer, 221 employed semi-conducting materials comprise Si, Ge, SiGe, GaAs, InP, InAs or InGaAs in the above-mentioned substrate 220.Such semi-conducting material can and the metal gates 202 that forms of the subsequent technique Schottky contacts that forms between metal-semiconductors, want and this contact is required for the present invention just.
Execution in step S102 carries out light dope to first semiconductor material layer 221 then.Lightly doped ion concentration is 1 * 10 18Cm -3To 5 * 10 18Cm -3For example, when forming P type metal-semiconductor field effect transistor, can use the B+ ion to mix, dosage is 1 * 10 12Cm -2To 5 * 10 12Cm -2, ion energy is 1KeV to 30KeV; And when need forming N type metal-semiconductor field effect transistor, can use the As+ ion to mix, dosage is 1 * 10 12Cm -2To 5 * 10 12Cm -2, ion energy is 1KeV to 20KeV.This doping content can guarantee to form Schottky contacts between channel region 205 and the metal gates 202 of follow-up formation.
Execution in step S103 then, etching first semiconductor material layer 221 with imbed dielectric layer 222, forms semiconductor material pillar as shown in Figure 8 203 and dielectric support post 211.The diameter of semiconductor material pillar 203 can be 2nm to 25nm, and its integral body is by 211 supports of dielectric support post.
When etching is imbedded dielectric layer 222 formation dielectric support post 211, will not imbed dielectric layer 222 complete etchings fully, and just make the thickness of imbedding dielectric layer 222 reduce.
Above-mentioned etching process can the branch multistep be carried out; For example can pass through following step carries out: elder generation is with the part of dry plasma etch first semiconductor material layer 221; Because the diameter of the semiconductor material pillar 203 of follow-up formation is less; Therefore, when adopting dry plasma etch, still can form the first half of slick and sly semiconductor material pillar 203; And then the method that adopts anisotropic wet etch continues etching first semiconductor material layer 221 and imbeds dielectric layer 222; Because anisotropic wet etch can produce undercutting (undercut) effect; Utilize this effect just in time can form the latter half of semiconductor material pillar 203; Similar, the method for anisotropic wet etch also can imbedded the regular dielectric support post 211 of formation on the dielectric layer 222.Above-mentioned dry plasma etch and anisotropic wet etch are prior art, repeat no more at this.
Diameter with above-mentioned dry plasma etch and the formed semiconductor material pillar 203 of anisotropic wet etch might not meet the reservation requirement, might not be sufficiently oily by its profile yet.Therefore can this semiconductor material pillar 203 be carried out thermal oxidation, and then put into acid solution, for example in the water-reducible HF solution of deionization with semiconductor material pillar 203 outer field oxide removals.Through such processing, just can control the size and the outline of semiconductor material pillar 203 easily, to meet the requirements.
Execution in step S104 then, the stage casing of removing dielectric support post 211 makes the stage casing of dielectric support post 211 form hollow out.Concrete grammar can be first imbedding the photoresist layer 230 that the method for utilizing spin coating and photoetching on the dielectric layer 222 forms one deck exposure dielectric support post 211 stage casings, as shown in Figure 9; (buffer oxide etchant, BOE) dielectric support post 211 stage casings of etching exposure make the stage casing of dielectric support post 211 form hollow out, take out photoresist layer 230 again, form structure shown in figure 10 to adopt the buffer oxide etching agent then.The stage casing of the dielectric support post 211 hollow out length that forms that is etched can be 5nm to 50nm.
After the step of removing dielectric support post 211 stage casings, can also carry out thermal anneal process to semiconductor material pillar 203, the temperature of thermal annealing is at 1000 ℃ to 1200 ℃.The effect of mass transmitting that thermal annealing brought can be so that semiconductor material pillar 203 be more slick and sly at the profile at the hollow out place in dielectric support post 211 stage casings, and can eliminate the damage that is produced in the process of etching semiconductor material post 203.
Execution in step S106 is then imbedding on the dielectric layer 222 depositing metal layers 231 to burying semiconductor material pillar 203 at least, and the hollow out place in filling dielectric support column 211 stage casings, forms structure shown in figure 11.The thickness of metal level 231 can be 10nm to 500nm.
The simple substance that above-mentioned metal level 231 can be W, Al, Ag, Au, Cr, Mo, Ni, Pd, Ti or Pt or any two or more lamination or alloys.Select for use the reason of these metal materials to be, form follow-up metal gates 202 with these metal materials and can form required Schottky contacts with semiconductor channel area 205.But; Here metal material of pointing out and aforesaid semi-conducting material only are some examples; Those skilled in the art will know that; Also have other metal material and semi-conducting material also can form Schottky contacts, such metal material and semi-conducting material also can be used and form metal gates 202 and semiconductor material pillar 203 in the present invention.
Execution in step S107 then, etching sheet metal 231 forms metal gates 202 shown in figure 12.The length of metal gates 202 is smaller or equal to dielectric support post 211 removed length, and makes metal gates 202 fall into the hollow out place in dielectric support post 211 stage casings.Therefore, metal gates 202 forms the parcel to semiconductor material pillar 203 at the hollow out place in dielectric support post 211 stage casings.Here, metal gates 202 is a Schottky contacts with contacting of semiconductor material pillar 203.And semiconductor material pillar 203 is by one section channel region 205 (with reference to figure 3) that promptly forms metal-semiconductor field effect transistor of said metal gates 202 parcels.
Execution in step S108 forms separator 212 on the sidewall of metal gates 202 then.The effect of separator 212 is to prevent that metal gates 202 and miscellaneous part from forming short circuit.Separator 212 can be oxide-nitride thing-oxide-isolation layer.The method of making separator 212 belongs to prior art, repeats no more at this.
Execution in step S109 carries out heavy doping to semiconductor material pillar 203 two ends institute exposed portions then, forms source region 204 and drain region 206.Here form among the heavily doped impurity that source region 204 and drain region 206 carried out and the step S102 that first semiconductor material layer 223 is carried out the conduction type of lightly doped impurity is identical.Adopt the identical doping impurity of conduction type, can form the source region-channel region-drain structure of metal-semiconductor field effect transistor preferably.
Then can execution in step S110, forming be the metal source 208 and the metal-drain 209 of ohmic contact with source region 204 and drain region 206 respectively, forms structure as shown in Figure 2.
What can also form metal gates 202 at last outreaches metal wire (figure do not show), and whole metal-semiconductor field effect transistor is sealed with dielectric substance, thereby forms complete metal-semiconductor field effect transistor.These steps belong to prior art, repeat no more at this.
Though the application with preferred embodiment openly as above; But it is not to be used for limiting claim; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so the application's protection range should be as the criterion with the scope that the application's claim is defined.

Claims (10)

1. metal-semiconductor field effect transistor; Comprise the grid that forms by metal and form the channel region that forms by semi-conducting material of Schottky contacts with grid; It is characterized in that: be provided with through hole in the said grid, said channel region part at least is positioned at said through hole.
2. metal-semiconductor field effect transistor as claimed in claim 1 is characterized in that: said metal-semiconductor field effect transistor is formed at silicon-on-insulator substrate.
3. metal-semiconductor field effect transistor as claimed in claim 1 is characterized in that: described semi-conducting material comprises Si, Ge, SiGe, GaAs, InP, InAs or InGaAs.
4. metal-semiconductor field effect transistor as claimed in claim 1 is characterized in that: also comprise the source region and the drain region that link with said channel region, said channel region, source region and drain region are mixed with the impurity of identical conduction type.
5. metal-semiconductor field effect transistor as claimed in claim 4 is characterized in that: the doping content in said source region and drain region is greater than the doping content of said channel region.
6. metal-semiconductor field effect transistor as claimed in claim 1 is characterized in that: said grid is formed by simple substance or any two or more lamination or the alloys of W, Al, Ag, Au, Cr, Mo, Ni, Pd, Ti or Pt.
7. metal-semiconductor field effect transistor as claimed in claim 1 is characterized in that: the length of said channel region is 5nm to 50nm.
8. metal-semiconductor field effect transistor as claimed in claim 1 is characterized in that: said channel region is a cylinder.
9. metal-semiconductor field effect transistor as claimed in claim 1 is characterized in that: also comprise with said source region forming the metal source of ohmic contact and forming the metal-drain of ohmic contact with said drain region.
10. metal-semiconductor field effect transistor as claimed in claim 1 is characterized in that: the ion concentration of mixing in the said channel region is 1 * 10 18Cm -3To 5 * 10 18Cm -3
CN200810202458XA 2008-11-10 2008-11-10 Metal-semiconductor field effect transistor Active CN101740618B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200810202458XA CN101740618B (en) 2008-11-10 2008-11-10 Metal-semiconductor field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN200810202458XA CN101740618B (en) 2008-11-10 2008-11-10 Metal-semiconductor field effect transistor

Publications (2)

Publication Number Publication Date
CN101740618A CN101740618A (en) 2010-06-16
CN101740618B true CN101740618B (en) 2012-01-25

Family

ID=42463786

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200810202458XA Active CN101740618B (en) 2008-11-10 2008-11-10 Metal-semiconductor field effect transistor

Country Status (1)

Country Link
CN (1) CN101740618B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034863B (en) 2009-09-28 2012-10-31 中芯国际集成电路制造(上海)有限公司 Semiconductor device, transistor having gate of around cylindrical channel and manufacturing method
US9373694B2 (en) 2009-09-28 2016-06-21 Semiconductor Manufacturing International (Shanghai) Corporation System and method for integrated circuits with cylindrical gate structures
CN104425607B (en) * 2013-09-05 2017-07-14 中芯国际集成电路制造(上海)有限公司 Nodeless mesh body pipe and preparation method thereof
CN104517847B (en) * 2013-09-29 2017-07-14 中芯国际集成电路制造(上海)有限公司 Nodeless mesh body pipe and forming method thereof
CN104638014A (en) * 2015-02-10 2015-05-20 清华大学 Junction-free multi-doped field effect transistor
CN113169221B (en) * 2020-07-17 2023-06-27 北京大学深圳研究生院 Junction-free nanowire field effect transistor and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1702843A (en) * 2004-05-25 2005-11-30 三星电子株式会社 Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels
KR20070117143A (en) * 2006-06-07 2007-12-12 삼성전자주식회사 Mos field effect transistor and method of fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1702843A (en) * 2004-05-25 2005-11-30 三星电子株式会社 Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels
KR20070117143A (en) * 2006-06-07 2007-12-12 삼성전자주식회사 Mos field effect transistor and method of fabricating the same

Also Published As

Publication number Publication date
CN101740618A (en) 2010-06-16

Similar Documents

Publication Publication Date Title
CN102097322B (en) Method of forming an insulated gate field effect transistor device having a shield electrode structure
CN102301484B (en) Asymmetric junction field effect transistor and method of manufacturing same
CN101740618B (en) Metal-semiconductor field effect transistor
CN105336735B (en) Semiconductor device having field effect structure and method of manufacturing the same
US6288425B1 (en) SOI-MOSFET device
TWI362737B (en) High energy esd structure
US8963218B2 (en) Dual-gate VDMOS device
US20070194353A1 (en) Metal source/drain Schottky barrier silicon-on-nothing MOSFET device and method thereof
US20080283918A1 (en) Ultra Thin Channel (UTC) MOSFET Structure Formed on BOX Regions Having Different Depths and Different Thicknesses Beneath the UTC and SourceDrain Regions and Method of Manufacture Thereof
US10910377B2 (en) LDMOS devices, integrated circuits including LDMSO devices, and methods for fabricating the same
CN102138217A (en) Power MOSFET with a gate structure of different material
KR20160065326A (en) Power semiconductor device and method of fabricating the same
US6812074B2 (en) SOI field effect transistor element having a recombination region and method of forming same
US20220130981A1 (en) Ldmos transistor and manufacturing method thereof
CN111370479A (en) Trench gate power device and manufacturing method thereof
CN101740388B (en) Method for manufacturing metal-semiconductor field effect transistor
US6410377B1 (en) Method for integrating CMOS sensor and high voltage device
US9059306B2 (en) Semiconductor device having DMOS integration
US9754839B2 (en) MOS transistor structure and method
US10297662B2 (en) Dielectrically isolated semiconductor device and method for manufacturing the same
WO2007109658A2 (en) Shared metallic source/drain cmos circuits and methods thereof
CN116072712A (en) Trench gate semiconductor device and method of manufacturing the same
CN101752412B (en) Bipolar transistor and manufacturing method thereof
EP1523775B1 (en) SOI field effect transistor element having a recombination region and method of forming same
US8476619B2 (en) Semiconductor device and method for fabricating the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant