CN100571038C - A kind of comparator with two kinds of logic functions - Google Patents

Abstract

The invention provides a kind of comparator with two kinds of logic functions, the structure of circuit comprises the first differential comparator circuit, the second differential comparator circuit, logic synthesis circuit.The first differential comparator circuit, the second differential comparator circuit has two-way input signal: Vin1 and Vin2 respectively, Vin3 and Vin4.The first differential comparator circuit and the second differential comparator circuit produce the input that two consequential signals output to the logic synthesis circuit, through the logic synthesis circuit, produce certain logical operation of needed comparator output result, the connection difference of four road signals will produce different logical expressions.This circuit has two kinds of logic functions, and the power consumption of comparing with commonsense method is lower, and circuit is simple.Based on the method, can derive the circuit that more comparator output signals is carried out more kinds of logical operations.

Description

A kind of comparator with two kinds of logic functions

Technical field

The present invention is a kind of comparator with two kinds of logic functions, belongs to electronic technology field, and particularly in the hybrid digital-analog integrated circuit design, digital and analogue signals is changed the design of required comparator.

Background technology

Comparator is widely used in the hybrid digital-analog integrated circuit, and analog signal is to the transfer process of digital signal.Counting-the Mo transfer process in, at first must sample to input.Then, through the signal of over-sampling by comparator with decision Analog signals'digital value, and in circuit design, the frequent comparative result that need produce some comparators, promptly these digital values are carried out logical operation.In these logical operations, as long as often know the value of one of them signal, just the comparative result that is produced by a comparator just can draw the result of logical operation, and not need the result of other comparators, for example, the output of comparator C PA and CPB A and B as a result will be carried out logical operation: F=AB, and when A was low level, B was that high or low level result is for high, just do not need the result of comparator C PB, CPB just can not work so.Imagination if these comparators can optionally be worked, so just greatly reduces power consumption.

Common comparator configuration adds that the circuit that its comparative result is carried out logical operation can realize this invention circuit function.And in the commonsense method, no matter whether its output result has effect to logic operation result to each comparator, all in work, can increase the power consumption of circuit like this.And to realize that different logic functions just needs different logic synthesis circuit, if will realize a variety of logical operations, the scale of entire circuit can be very big.High power consumption like this, the huge again circuit of scale do not meet the trend of integrated circuit development.

Summary of the invention

The objective of the invention is at above-mentioned the deficiencies in the prior art, a kind of comparator circuit with two kinds of logic functions is provided, this circuit has two kinds of logic functions, the power consumption of comparing with commonsense method is much lower, based on the method, can derive the circuit that more comparator output signals is carried out more kinds of logical operations.

For solving the problems of the technologies described above, the technical solution adopted in the present invention is such:

A kind of comparator with two kinds of logic functions comprises: the first differential comparator circuit, the second differential comparator circuit, logic synthesis circuit; The described first differential comparator circuit produces comparative result, be input to the variable of the input of logic synthesis circuit as logical operation, also can produce the control second differential comparator circuit working whether signal, be input to the control end of the second differential comparator circuit, realize the management of low-power consumption; The described second differential comparator circuit produces comparative result, be input to another input of logic synthesis circuit another variable as logical operation, the signal that produces shielding first differential comparator circuit output result simultaneously comes the auxiliary logic function that realizes to the logic synthesis circuit; Described logic synthesis circuit carries out certain logical operation to the comparative result of two comparators, and the result is exported.

The described first differential comparator circuit is managed M3 and M4 and auxiliary current source I by PMOS pipe M1 and M2, NMOS and is constituted; The grid of PMOS pipe M1 and M2 is as differential right input, wherein the grid of PMOS pipe M1 meets input voltage signal Vin1, and the grid of PMOS pipe M2 meets input voltage signal Vin2, and both source ends link to each other, received the output of auxiliary current source I again, and the input of auxiliary current source I connects power Vcc; The drain electrode of PMOS pipe M1 connects grid and the drain electrode of NMOS pipe M3, has received the grid of tail current source NMOS pipe M5 in the second differential comparator circuit simultaneously again; The drain electrode of PMOS pipe M2 connects grid and the drain electrode of NMOS pipe M4, receives the drain electrode of grid and the PMOS pipe M10 of NMOS pipe M12 in the logic synthesis circuit simultaneously again; The source electrode of NMOS pipe M3 and M4 has been connected to ground Vss simultaneously.

The described second differential comparator circuit, by NMOS pipe M6 and M7, PMOS pipe M8 and M9, and NMOS pipe M5 constitutes; The grid of NMOS pipe M6 and M7 is as differential right input, and wherein the grid of M6 meets input voltage signal Vin4, and the grid of NMOS pipe M7 meets input voltage signal Vin3, and both source ends link to each other, and has received the drain electrode of NMOS pipe M5 again; The grid of NMOS pipe M5 connects the drain electrode of PMOS pipe M1, NMOS pipe M3 in the first differential comparator circuit and the grid of M3, the source ground Vss of NMOS pipe M5; The drain electrode of NMOS pipe M6 connects grid and the drain electrode of PMOS pipe M8, and the grid of PMOS pipe M10 in the logic synthesis circuit, and the drain electrode of NMOS pipe M7 connects grid and the drain electrode of PMOS pipe M9, and the grid of PMOS pipe M11 in the logic synthesis circuit; The source electrode of PMOS pipe M8 and M9 has been received power Vcc again simultaneously.

Described logic synthesis circuit, by PMOS pipe M10 and M11, NMOS manages M12, and inverter INV constitutes; PMOS pipe M10 source electrode connects power Vcc, its grid connects NMOS pipe M6 and the drain electrode of PMOS pipe M8 and the grid of PMOS pipe M8 in the second differential comparator circuit, PMOS pipe M10 drain electrode connects NMOS pipe M12 grid, receives PMOS pipe M2 and the drain electrode of NMOS pipe M4 and the grid of NMOS pipe M4 in the first differential comparator circuit again; PMOS pipe M11 source electrode connects power Vcc, and its grid connects NMOS pipe M7 and the drain electrode of PMOS pipe M9 and the grid of PMOS pipe M9 in the second differential comparator circuit, and PMOS pipe M11 drain electrode links to each other with NMOS pipe M12 drain electrode, constitutes output F; NMOS pipe M12 source ground Vss, NMOS pipe M12 grid connects the M10 drain electrode, receives PMOS pipe M2 and the drain electrode of NMOS pipe M4 and the grid of NMOS pipe M4 in the first differential comparator circuit again; Output F connects the input of inverter INV, and INV is output as F.

The present invention has tangible advantage:

(1) circuit structure is simple, does not need huge logic synthesis circuit, and the position that only needs the change signal to be added in the input of two comparators can obtain 8 kinds of logic functions.

(2) compare with common method, according to foregoing signal shielding principle, this circuit can optionally allow comparator work, rather than all comparators work always, thereby has reduced the power consumption of circuit.

(3) building method of this circuit can derive the circuit that more comparator output signals is carried out more kinds of logical operations.

Description of drawings

Fig. 1 is the structured flowchart of the traditional circuit of this method of realization;

Fig. 2 is the physical circuit figure of comparator part in example of conventional method;

Fig. 3 is a structured flowchart of the present invention;

Fig. 4 is physical circuit figure of the present invention.

Embodiment

Describe concrete enforcement of the present invention in detail below in conjunction with accompanying drawing.

A kind of comparator circuit with two kinds of logic functions shown in Fig. 3 circuit structure diagram, is divided into the first differential comparator circuit, the second differential comparator circuit, three parts of logic synthesis circuit.Their direct current input connects DC power supply Vcc respectively.The first differential comparator circuit, the second differential comparator circuit has two-way input signal: Vin1 and Vin2 respectively, Vin3 and Vin4.Relatively produce two consequential signals and output to the input of logic synthesis circuit, comprehensive through the logic synthesis circuit, certain logical operation that produces needed comparator output result, the connection difference of four road signals will produce different logical combinations.

Wherein, as shown in Figure 4, the structure of the described first differential comparator circuit is: by PMOS pipe M1 and M2, NMOS pipe M3 and M4, and auxiliary current source I constitutes.The grid of PMOS pipe M1 and M2 is as differential right input, wherein the grid of M1 meets input voltage signal Vin1, and the grid of M2 meets input voltage signal Vin2, and both source ends link to each other, received the output of auxiliary current source I again, and the input of auxiliary current source I connects power Vcc; The drain electrode of M1 connects grid and the drain electrode of M3, has received the grid of tail current source NMOS pipe M5 among the second differential comparator circuit CPB simultaneously again; The drain electrode of M2 connects grid and the drain electrode of M4, receives the drain electrode of grid and the PMOS pipe M10 of NMOS pipe M12 in the logic synthesis circuit simultaneously again; The source electrode of M3 and M4 has been connected to ground Vss simultaneously.

The structure of the described second differential comparator circuit is: by NMOS pipe M6 and M7, PMOS pipe M8 and M9, and NMOS pipe M5 constitutes.The grid of NMOS pipe M6 and M7 is as differential right input, and wherein the grid of M6 meets input voltage signal Vin4, and the grid of M7 meets input voltage signal Vin3, and both source ends link to each other, and has received the drain electrode of NMOS pipe M5 again; The grid of NMOS pipe M5 connects the drain electrode of PMOS pipe M1, NMOS pipe M3 among the first differential comparator circuit CPA and the grid of M3, the source ground Vss of M5; The drain electrode of M6 connects grid and the drain electrode of M8, and the grid of PMOS pipe M10 in the logic synthesis circuit, and the drain electrode of M7 connects grid and the drain electrode of M9, and the grid of PMOS pipe M11 in the logic synthesis circuit; The source electrode of M8 and M9 has been received power Vcc again simultaneously.

The structure of described logic synthesis circuit is: by PMOS pipe M10 and M11, NMOS manages M12, and inverter INV constitutes.PMOS pipe M10 source electrode connects power Vcc, the M10 grid connects NMOS pipe M6 and the drain electrode of PMOS pipe M8 and the grid of M8 among the second differential comparator circuit CPB, the M10 drain electrode connects the M12 grid, receives PMOS pipe M2 and the drain electrode of NMOS pipe M4 and the grid of M4 among the first differential comparator circuit CPA again; PMOS pipe M11 source electrode connects power Vcc, and the M11 grid connects NMOS pipe M7 and the drain electrode of PMOS pipe M9 and the grid of M9 among the second differential comparator circuit CPB, and the M11 drain electrode links to each other with the M12 drain electrode, constitutes output F; NMOS pipe M12 source ground Vss, the M12 grid connects the M10 drain electrode, receives PMOS pipe M2 and the drain electrode of NMOS pipe M4 and the grid of M4 among the first differential comparator circuit CPA again, and the M12 drain electrode is connected to output F with the M11 drain electrode; Output F meets the input of inverter INV, the output F of INV.

The operation principle of this circuit: for the first differential comparator circuit, when the level of input Vin1 during greater than Vin2, M3 grid, drain terminal voltage are low level, receive the grid of M5, M5 is turn-offed, the second differential comparator circuit is not worked, M4 grid, drain terminal are high level at this moment, receive the grid of M12, make M12 that conducting pulls into low level with F, thereby F is a high level.When the level of input Vin1 during less than Vin2, the M12 grid is a low level, and F also determines, and the M5 grid is a high level, and the second differential comparator circuit working is when the level of its input Vin3 during greater than Vin4, the M11 grid is a low level, and F is drawn high in the M11 conducting, thereby F is a low level, when the level of Vin3 during less than Vin4, the M10 grid is a low level, and the M12 grid potential is raised in the M10 conducting, the M12 conducting, F is pulled into low level, thereby F is a high level.

Principle of the present invention:

Fig. 3 has provided the structural principle block diagram of the comparator circuit of being invented with two kinds of logic functions.Narrate the logic function design principle and the process of this circuit below:

(1) set a and relatively produce a-signal with the b signal through comparator C PA, this as a result the time when producing a＞b, A is a low level, and this as a result the time as generation a＜b, A is a high level, i.e. A=(a＜b); C and d signal relatively produce the B signal by comparator C PB, and this as a result the time when producing c＞d, B is a high level, and this as a result the time when producing c＜d, B is a low level, i.e. B=(c＞d).

(2) a, b two the input Vin1 and the Vin2 that are added to comparator C PA has two kinds of situation: Vin1=a, Vin2=b and Vin1=b, Vin2=a.In like manner, c, d two the input Vin3 and the Vin4 that are added to comparator C PB also has two kinds of situation: Vin3=c, Vin4=d and Vin3=d, Vin4=c.

Permutation and combination is totally 4 kinds of connection situations, according to the operation principle of aforementioned this invention circuit, can produce 4 kinds of logical operation expression formulas, and (A B) represents, adds four kinds of operation expressions of the inverted signal F of F, and common property is given birth to 8 kinds of logical operation functions to A, B with F=.Can obtain a, the b of every kind of logical expression correspondence, the connection of c, d through deriving, listed as following table 1:

Table 1

At this, be example with a kind of situation, the process of design logic function is described:

Get a kind of method of attachment: Vin1=a arbitrarily, Vin2=b, Vin3=c, Vin4=d.

Derivation under the situation of this method of attachment F to the logical function expression formula of A, B.According to the operation principle of circuit, it is listed that A, B get the truth table such as the table 2 of different value:

Table 2

By row Karnaugh map abbreviation: obtain F=AB, F=A+B promptly obtains the logic function that can obtain under this connection situation.The design class of other situations seemingly in the table 1.

In addition, this comparator circuit with two kinds of logic functions has low in power consumption, its principle is: in some logical operation, as long as often know the value of one of them signal, the comparative result that produces by comparator just, just can draw the result of logical operation, the comparator that produces other signals so just can not worked, so that reduce circuit power consumption.Here provided the rough comparison of quantitatively calculating of the traditional circuit and the circuitry consumes electric current of the present invention of realization said function.Fig. 1 is the conventional circuit structure schematic diagram, and Fig. 2 is the practical circuit of a comparator of conventional method employing.Traditional circuit is known by Fig. 1, expect that different logic functions must revise circuit, or a plurality of logic synthesis circuit are set, and obtains the Different Logic computing of compared result.The present invention is known by Fig. 3, only needs to select different input compound modes can obtain 8 kinds of logic functions.Respectively calculating chart 2 is the comparator in the conventional method and the proportionate relationship of Fig. 4 current sinking below, thereby can draw the present invention can reduce power consumption than conventional method conclusion.The bias current of known traditional circuit comparator is I, and input has two kinds of situations:

A.Vin1＞Vin2, current sinking I;

B.Vin1＜Vin2 current sinking 2I,

When the both of these case equiprobability took place, average consumed cur-rent was I _{C, AV1}'=1.5I has two comparators to work simultaneously in the conventional method, the consumption total current is I _{C, AV1}=3I.

Known comparator offset electric current of the present invention is I, and input has four kinds of combined situation:

During a.Vin1＜Vin2, when being divided into two kinds of situations: Vin3＞Vin4, the consumption total current is 2I; During Vin3＜Vin4, the consumption total current is 3I;

During b.Vin1＞Vin2, no matter Vin3＞Vin4, or Vin3＜Vin4, the total current of consumption all is I.

When various situation equiprobability take place, calculate its average consumed cur-rent I _{C, AV2}=2I * 25%+3I * 25%+I * 50%=1.75I.The present invention has the comparator of two kinds of logic functions, and its circuit topological structure can make circuit institute consumed current lack 42% than the circuitry consumes electric current of above-mentioned traditional structure, shows that fully the present invention is in the superiority that reduces on the power consumption.

On the basis of the thought that this circuit is realized, can revise the logic synthesis circuit, and derive the similar circuit of more compare result signals being carried out more kinds of logical operations by increasing number of comparators.

Claims (1)

1. comparator with two kinds of logic functions, described comparator comprises the first differential comparator circuit, the second differential comparator circuit, logic synthesis circuit; The described first differential comparator circuit produces comparative result, be input to the variable of the input of logic synthesis circuit as logical operation, also can produce the control second differential comparator circuit working whether signal, the management that realizes low-power consumption is brought in the control that is input to the second differential comparator circuit; The described second differential comparator circuit produces comparative result, be input to another input of logic synthesis circuit, as another variable of logical operation, the signal that produces shielding first differential comparator circuit output result simultaneously comes the auxiliary logic function that realizes to the logic synthesis circuit; Described logic synthesis circuit carries out logical operation to the comparative result of the first differential comparator circuit and the second differential comparator circuit, and with result's output, it is characterized in that:

The described first differential comparator circuit is managed M3 and M4 and auxiliary current source I by PMOS pipe M1 and M2, NMOS and is constituted; The grid of PMOS pipe M1 and M2 is as differential right input, wherein the grid of PMOS pipe M1 meets input voltage signal Vin1, and the grid of PMOS pipe M2 meets input voltage signal Vin2, and both source ends link to each other, received the output of auxiliary current source I again, and the input of auxiliary current source I connects power Vcc; The drain electrode of PMOS pipe M1 connects grid and the drain electrode of NMOS pipe M3, has received the grid of tail current source NMOS pipe M5 in the second differential comparator circuit simultaneously again; The drain electrode of PMOS pipe M2 connects grid and the drain electrode of NMOS pipe M4, receives the drain electrode of grid and the PMOS pipe M10 of NMOS pipe M12 in the logic synthesis circuit simultaneously again; The source electrode of NMOS pipe M3 and M4 has been connected to ground Vss simultaneously;

The described second differential comparator circuit, by NMOS pipe M6 and M7, PMOS pipe M8 and M9, and NMOS pipe M5 constitutes; The grid of NMOS pipe M6 and M7 is as differential right input, and wherein the grid of M6 meets input voltage signal Vin4, and the grid of M7 meets input voltage signal Vin3, and both source ends link to each other, and has received the drain electrode of NMOS pipe M5 again; The grid of NMOS pipe M5 connects the drain electrode of PMOS pipe M1, NMOS pipe M3 in the first differential comparator circuit and the grid of M3, the source ground Vss of NMOS pipe M5; The drain electrode of NMOS pipe M6 connects grid and the drain electrode of PMOS pipe M8, and the grid of PMOS pipe M10 in the logic synthesis circuit, and the drain electrode of NMOS pipe M7 connects grid and the drain electrode of PMOS pipe M9, and the grid of PMOS pipe M11 in the logic synthesis circuit; The source electrode of PMOS pipe M8 and M9 has been received power Vcc again simultaneously;

Described logic synthesis circuit, by PMOS pipe M10 and M11, NMOS manages M12, and inverter INV constitutes; PMOS pipe M10 source electrode connects power Vcc, its grid connects NMOS pipe M6 and the drain electrode of PMOS pipe M8 and the grid of PMOS pipe M8 in the second differential comparator circuit, PMOS pipe M10 drain electrode connects NMOS pipe M12 grid, receives PMOS pipe M2 and the drain electrode of NMOS pipe M4 and the grid of NMOS pipe M4 in the first differential comparator circuit again; PMOS pipe M11 source electrode connects power Vcc, and its grid connects NMOS pipe M7 and the drain electrode of PMOS pipe M9 and the grid of PMOS pipe M9 in the second differential comparator circuit, and PMOS pipe M11 drain electrode links to each other with NMOS pipe M12 drain electrode, constitutes output F; NMOS pipe M12 source ground Vss, NMOS pipe M12 grid connects the M10 drain electrode, receives PMOS pipe M2 and the drain electrode of NMOS pipe M4 and the grid of NMOS pipe M4 in the first differential comparator circuit again; Output F connects the input of inverter INV, and INV is output as F.

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