CN100524815C - Finfet transistor and circuit - Google Patents

Finfet transistor and circuit Download PDF

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CN100524815C
CN100524815C CNB2005100651041A CN200510065104A CN100524815C CN 100524815 C CN100524815 C CN 100524815C CN B2005100651041 A CNB2005100651041 A CN B2005100651041A CN 200510065104 A CN200510065104 A CN 200510065104A CN 100524815 C CN100524815 C CN 100524815C
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fin
longitudinal axis
crystal face
source
contact
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CN1684271A (en
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凯利·伯恩斯坦
艾德华·J·诺瓦克
贝斯安·雷尼
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

Description

Finfet field effect transistor and circuit
Technical field
The present invention relates to FinFET field (finfet field effect transistor); More specifically, it relates to the FinFET that contains adjustable drive strength, adjusts the method for FinFET drive strength and the FinFET circuit that use contains adjustable drive strength.
Background technology
Integrated circuit technique and complementary metal-oxide thing-silicon (CMOS) technology had once promoted more the high-performance and the therefore direction of small transistor size more.Appeared the technology of pursuing high performance circuit as developing in one's mind less than the FinFET technology of about 65nm.In the high performance level of using inferior 65nm size, the drive strength of trim transistors becomes very crucial in the integrated circuit, yet, because the quantized character of their structures does not have method to be used for the circuit that is made of FinFET is finely tuned at present.Like this, the needs that have the method for a kind of FinFET of fine setting drive strength and fine setting FinFET drive strength.
Summary of the invention
A first aspect of the present invention is a kind of electronic device, comprising: a source and a leakage; Monocrystalline first fin, contain first and second backward ends and first and second counter wall, and first to second end along first longitudinal axis from first fin extends the first end in contact source of first fin, and second end in contact leakage of first fin, first longitudinal axis is parallel with a crystrallographic plane; Monocrystalline second fin, contain first and second backward ends and first and second counter wall, and first to second end along second longitudinal axis from second fin extends, the first end in contact source of second fin, and second end in contact of second fin leaks, and second longitudinal axis and rotation are away from the plane parallel of crystrallographic plane; And a conductive gate, and contact at a gate dielectric that forms on first and second sidewalls of first fin and on first and second sidewalls at second fin.
Second aspect of the present invention is the method that is used to adjust an electronic device drive strength, comprising: form a source and a leakage in a monocrystal material; Form monocrystalline first fin from monocrystal material, first fin contains first and second backward ends and first and second counter wall, and first to second end along first longitudinal axis from first fin extends the first end in contact source of first fin, and the leakage of second end in contact of first fin; First longitudinal axis is parallel with a crystrallographic plane of monocrystal material; Form monocrystalline second fin from monocrystal material, second fin contains first and second backward ends and first and second counter wall, and first to second end along second longitudinal axis from second fin extends the first end in contact source of second fin, and the leakage of second end in contact of second fin; With second longitudinal axis and rotation plane parallel away from crystrallographic plane; And a conductive gate is provided, and contact at a gate dielectric that forms on first and second sidewalls of first fin and on first and second sidewalls at second fin.
The 3rd aspect of the present invention is a kind of integrated circuit, and comprising: the first transistor comprises: leak in first source and first; Monocrystalline first fin, contain first and second backward ends and first and second counter wall, and first to second end along first longitudinal axis from first fin extends, first end in contact, first source of first fin, and second end in contact, first leakage of first fin, first longitudinal axis is parallel with a crystrallographic plane; Monocrystalline second fin, contain first and second backward ends and first and second counter wall, and first to second end along second longitudinal axis from second fin extends, first end in contact, first source of second fin, and second end in contact first of second fin leaks, and second longitudinal axis and rotation are away from the plane parallel of crystrallographic plane; And first conductive gate, and contact at a gate dielectric that forms on first and second sidewalls of first fin and on first and second sidewalls at second fin; And transistor seconds comprises: leak in second source and second; Monocrystalline the 3rd fin, contain first and second backward ends and first and second counter wall, and first to second end along the 3rd longitudinal axis from the 3rd fin extends, first end in contact, second source of the 3rd fin, and second end in contact, second leakage of first fin, the 3rd longitudinal axis is parallel with crystrallographic plane; And second conductive gate, and contact at a gate dielectric that forms on first and second sidewalls of the 3rd fin and on first and second sidewalls at the 3rd fin.
The 4th aspect of the present invention is to adjust the method for the drive strength ratio between the first transistor and transistor seconds in the integrated circuit, and comprising: the first transistor is provided, and the first transistor comprises: leak in first source and first; Monocrystalline first fin, contain first and second backward ends and first and second counter wall, and first to second end along first longitudinal axis from first fin extends, first end in contact, first source of first fin, and second end in contact, first leakage of first fin, first longitudinal axis is parallel with a crystrallographic plane; Monocrystalline second fin, contain first and second backward ends and first and second counter wall, and first to second end along second longitudinal axis from second fin extends, first end in contact, first source of second fin, and second end in contact first of second fin leaks, and second longitudinal axis and rotation are away from the plane parallel of crystrallographic plane; And first conductive gate, and contact at a gate dielectric that forms on first and second sidewalls of first fin and on first and second sidewalls at second fin; And transistor seconds is provided, transistor seconds comprises: leak in second source and second; Monocrystalline the 3rd fin, contain first and second backward ends and first and second counter wall, and first to second end along the 3rd longitudinal axis from the 3rd fin extends, first end in contact, second source of the 3rd fin, and second end in contact, second leakage of first fin, the 3rd longitudinal axis is parallel with crystrallographic plane; And second conductive gate, and contact at a gate dielectric that forms on first and second sidewalls of the 3rd fin and on first and second sidewalls at the 3rd fin.
The 5th aspect of the present invention is a kind of electronic device, comprising: a source and a leakage; Monocrystalline first fin contains first and second backward ends and first and second counter wall, the first end in contact source of first fin, and the leakage of second end in contact of first fin, and first longitudinal axis is parallel with a crystrallographic plane; Monocrystalline second fin contains first and second backward ends and first and second counter wall, the first end in contact source of second fin, and second end in contact of second fin is leaked; First conductive gate, with on first and second sidewalls of first fin and a gate dielectric that on the first side wall of second fin, forms contact; And second conductive gate, contact with a gate dielectric that on second sidewall of second fin, forms.
The 6th aspect of the present invention is the method that is used to adjust an electronic device drive strength, comprise: a source and a leakage are provided, monocrystalline first fin is provided, contain first and second backward ends and first and second counter wall, the first end in contact source of first fin, and second end in contact of first fin is leaked; Monocrystalline second fin is provided, contains first and second backward ends and first and second counter wall, the first end in contact source of second fin, and second end in contact of second fin is leaked; First conductive gate is provided, with on first and second sidewalls of first fin and a gate dielectric that on the first side wall of second fin, forms contact; Second conductive gate is provided, contacts with a gate dielectric that on second sidewall of second fin, forms; And the first grid is connected at first voltage source of first voltage level and with second grid is connected to second voltage source at second voltage level, the first and second voltage level differences.
The 7th aspect of the present invention is a kind of integrated circuit, and comprising: the first transistor comprises: leak in first source and first; Monocrystalline first fin contains first and second backward ends and first and second counter wall, first end in contact, first source of first fin, and second end in contact first of first fin is leaked; Monocrystalline second fin contains first and second backward ends and first and second counter wall, first end in contact, first source of second fin, and second end in contact first of second fin is leaked; First conductive gate, with on first and second sidewalls of first fin and a gate dielectric that on the first side wall of second fin, forms contact; And second conductive gate, contact with a gate dielectric that on second sidewall of second fin, forms; And transistor seconds comprises: leak in second source and second; Monocrystalline the 3rd fin contains first and second backward ends and first and second counter wall, first end in contact, second source of the 3rd fin, and second end in contact second of the 3rd fin is leaked; And the 3rd conductive gate, and contact at a gate dielectric that forms on first and second sidewalls of the 3rd fin and on first and second sidewalls at the 3rd fin.
The 8th aspect of the present invention is to adjust the method for the drive strength ratio between the first transistor and transistor seconds in the integrated circuit, and comprise the first transistor is provided that the first transistor comprises: leak in first source and first; Monocrystalline first fin contains first and second backward ends and first and second counter wall, first end in contact, first source of first fin, and second end in contact first of first fin is leaked; Monocrystalline second fin contains first and second backward ends and first and second counter wall, first end in contact, first source of second fin, and second end in contact first of second fin is leaked; First conductive gate, with on first and second sidewalls of first fin and a gate dielectric that on the first side wall of second fin, forms contact; And second conductive gate, contact with a gate dielectric that on second sidewall of second fin, forms; Transistor seconds is provided, and transistor seconds comprises: leak in second source and second; Monocrystalline the 3rd fin contains first and second backward ends and first and second counter wall, first end in contact, second source of the 3rd fin, and second end in contact second of the 3rd fin is leaked; And the 3rd conductive gate, and contact at a gate dielectric that forms on first and second sidewalls of the 3rd fin and on first and second sidewalls at the 3rd fin; And the first grid is connected at first voltage source of first voltage level and with second grid is connected to second voltage source at second voltage level, the first and second voltage level differences.
Description of drawings
Feature of the present invention proposes in additional claims.Yet the present invention itself is by will be better understood below in conjunction with the detailed description of accompanying drawing to example embodiment, wherein:
Fig. 1 is according to various embodiments of the present invention, represent various FinFET fin part etc. appearance figure;
Fig. 2 is a FinFET at the curve to drift angle axle θ of reducing of linear and saturation region mutual conductance;
Fig. 3 A is to be end view by the line 3B-3B of Fig. 3 A according to FinFET transistor top view of first embodiment of the invention and Fig. 3 B;
Fig. 4 A is to be end view by the line 4B-4B of Fig. 4 A according to FinFET transistor top view of second embodiment of the invention and Fig. 4 B;
Fig. 5 is to use the exemplary circuit of a FinFET, and its drive strength has been adjusted according to first embodiment of the invention;
Fig. 6 is to use the exemplary circuit of a FinFET, and its drive strength has been adjusted according to second embodiment of the invention.
Embodiment
In crystalline solid, form the atom of solid and arrange with a kind of ground, periodic mode space that is called dot matrix.A lattice always comprises a volume, and it is represented whole dot matrix and spreads all over whole crystal and repeat regularly.Convention below having used when in the disclosure, describing the crystalline state semi-conducting material.
Direction in lattice is expressed by three integers of a cover, and this has identical relation with vector component in one direction.For example, in cubic lattice, for example silicon has diamond lattice, and a body diagonal exists along [111] direction, and [] square brackets are represented a concrete direction.By the many directions in lattice of a symmetry transformation is equivalent, and this depends on any selection of axis of orientation.For example, in cubic crystal [100], the crystallographic direction of [010] and [001] all is the crystallization equivalence.Direction and its all equivalent directions by＜bracket represents.Like this, sign＜100〉direction comprises [100] of equivalence, and [010] and [001] forward and equivalent negative be to [100], [0-10] and [00-1].
Plane in crystal can also use three integers of a cover to determine.They are used for defining a cover parallel plane and every cover integer is put into () round parentheses to determine an actual plane.For example appropriately represent one perpendicular to [100] to the plane be (100).Like this, if a known cubic crystal or a direction or a plane, its vertical homologue just can calculate and determine rapidly.By the many planes in lattice of a symmetry transformation is equivalent, and this depends on any selection of axis of orientation.For example, in cubic crystal (100), (010) and (001) plane all is the crystallization equivalence.A plane and its all equivalent planes are represented by { } bracket.Like this, the sign 100} plane comprise the equivalence (100), (010) and (001) horizontal frontal plane and equivalent plane (100), (0-10) with (00-1).
Fig. 1 is according to various embodiments of the present invention, represent various FinFET fin part etc. appearance figure.Among Fig. 1, a substrate 100 comprises a supporting layer 105 that contains an end face 110, contains a separator 115 of an end face 120, and this separator is formed on the end face 110 of supporting layer 105.Separator 115 can comprise that one is buried oxide skin(coating) (BOX), perhaps can comprise the semiconductor region of a doping.Fin 125 and 130 is formed by a crystalline semiconductor materials, and this material is formed on the end face 110 of burying isolation 115.Fin 125 and 130 can comprise any suitable semi-conducting material, includes but are not limited to:: Si, Ge, GaP, InAs, InP, SiGe, GaAs, or other III/V compounds of group.Fin 125 contains the parallel side wall 135 (only having a sidewall to see among Fig. 1) that is parallel to crystrallographic plane 140.Fin 135 contains the parallel side wall 145 (only having a sidewall to see among Fig. 1) that is parallel to crystrallographic plane 150.Plane 150 is about 140 1 angle θ of common axis 152 skew crystrallographic planes.In an example, when being used for a NFET FinFET (after this being NFinFET), fin 125 and 130 comprises that monocrystalline silicon and crystrallographic plane 140 are { 100} crystal faces, and when being used for a PFET FinFET (after this being P FinFET), fin 125 and 130 comprises that monocrystalline silicon and crystrallographic plane 140 are { 110} crystal faces.In an example, when crystrallographic plane 140 be during the 100} crystal face, and θ be defined as fin 130 rotation advance the 110} crystal face, and when crystrallographic plane 140 be that { during the 110} crystal face, θ is defined as fin 140 and rotates { 100} crystal face.
Fin 125 is buried the physical length that has L on end face 120 directions of separator 115 in being parallel to plane 140, and the physical height that has H on the direction perpendicular to physical length L.Fin 130 is buried the physical length that has L θ on end face 120 directions of separator 115 in being parallel to plane 150 (with plane 140 deviation angle θ), and the physical height that has H on the direction perpendicular to physical length L.Notice that in a FinFET, the physical height of fin has determined transistorized electron channel width.In a single gate FinFET (grid are formed on one side of fin), physical height H has determined the electron channel width W.Channel width is the twice of height in a double grid FinFET, because on the both sides of fin grid are arranged all, W is the function of 2H.(facing the definition of double grid FinFET as follows).The physical length of a FinFET fin has defined the channel length of FinFET, and is identical with the definition of traditional F ET, and like this, after this label L or L θ it is also understood that and be channel length.
When fin 125 and 130 was incorporated FinFET into, the transoid carrier flow was to being respectively 155 and 160 directions.Direction 155 is parallel to sidewall 135, and direction 160 is parallel to sidewall 145.Total institute is known, and the transoid carrier flow is subjected to the crystal orientation influence of a FinFET fin.To NFinFET, maximum transoid charge carrier (electronics) mobility is along { the 100} crystal orientation, to PFinFET, maximum transoid charge carrier (hole) mobility is along { 110} crystal orientation.This is reflected in the FinFET mutual conductance (Gm) as shown in Figure 2 and that hereinafter discuss.
Fig. 2 is a FinFET at the curve to drift angle axle θ of reducing of linear and saturation region mutual conductance.Mutual conductance (Gm) is the ratio of output current to input voltage, is the tolerance of a FET gain.In Fig. 2, mutual conductance when transistor is operated in linear zone Gm lin (above curve) and the mutual conductance when transistor is operated in saturation region Gm sat (below curve) are only at θ (from maximum mobility axle offset)=equated in 0 o'clock.Gm sat little by little fails from Gm lin when θ increases.
The curve of Fig. 2 can be explained at least in part by following: the mobility of the electronics in the NFET raceway groove (transoid charge carrier) is in that { the 100} face is near the highest, and in that { the 110} face is very low.{ electron mobility in the 110} face is { half of mobility in the 100} face approximately.The mobility in the hole in the PFET raceway groove (transoid charge carrier) is in that { the 110} face is the highest, and in that { the 100} face is very low.{ hole mobility in the 100} face is approximately less than { half of mobility in the 110} face.When from one when forming by vertical plane cutting on the 100} face wafer, { 100} and { the 110} face is mutually with 45 ° angular orientation.
Fig. 3 A is a FinFET transistor top view according to first embodiment of the invention, and Fig. 3 B is the end view by the line 3B-3B of Fig. 3 A.Among Fig. 3 A, FinFET 200 comprises parallel source/leakage 205A and 205B, and contacts the backward end of monocrystalline vertical fins 210 and angled monocrystalline fin 215 with electricity with physics.Vertical fins 210 is longitudinally parallel with a plane 220, and angled monocrystalline fin 215 is longitudinally parallel with a plane 225, skew (rotate with plane 210 and 225 total axles, as shown in Figure 1 and following description) 220 1 angle θ of crystal face along one.Angle θ also represents to rotate to a lower main carrier mobility direction from a higher transoid carrier mobility direction.Fin 210 is perpendicular to source/leakage 205A and 205B.A common gate 230 is formed on vertical fins 210 and the angled fin 215, and isolates with fin by the gate dielectric 235 that is formed on each fin reverse side.Vertical fins 210 has channel length L, and angled fin 215 has channel length L θ, wherein L θ=L/cos θ.Vertical fins 210 has identical height H (seeing Fig. 3 B) with angled fin 215.
Turn to Fig. 3 B, vertical fins 210 and angled fin 215 have height H as can be seen, and the end face 237 of the end face 235 of vertical fins 210 and angled fin 215 is by dielectric cap 240 and grid 230 electric isolation.Note, may replace dielectric cap 240 with gate dielectric 235.Vertical fins 210 and angled fin 215 are formed on the end face 245 of an insulating barrier 250, and this insulating barrier is formed on the end face 255 of substrate 260.
In first example, FinFET 200 is N type FinFET, and source/leakage 205A and 205B are that the N type mixes, vertical fins 210 and angled fin 215 comprise that P mixes, N light dope or intrinsic monocrystalline silicon, plane 220 are that { 100} crystal face, θ are that { the angle of 110} crystal face is entered in rotation.In second example, FinFET 200 is P type FinFET, and source/leakage 205A and 205B are that the P type mixes, vertical fins 210 and angled fin 215 comprise that N mixes, or P light dope or intrinsic monocrystalline silicon, plane 220 is that { 110} crystal face, θ are that { the angle of 100} crystal face is entered in rotation.
The lightly doped monocrystalline silicon of N or P is defined as and contains a doped level, when grid being applied with a normal working voltage, below the grid of FinFET fin, the source and leak between channel region in can not stop and form an inversion layer.In an example, lightly doped silicon has the concentration about 10 of N or P dopant 15Atm/cm 3Or it is lower.
Transistorized drive strength is defined as the tolerance of the magnitude of current that this transistor can supply.Drive strength in the integrated circuit between PFET and the NFET is than being an important consideration, and this will be described below.The relative drive strength of FinFET 200 provides in formula 1.
β(W/L)(3+(cosθ)(1-0.9(|θ/45°|)))，|θ|<45° (1)
Wherein
β=transistorized relative drive strength;
The channel width of each fin of W=;
The length of L=vertical fins 205; And
Angle between θ=vertical fins and the angled fin.
Although three vertical fins 210 and an angled fin 215 have been shown in Fig. 3 A and 3B, above a vertical fins 210, any number can be arranged, and above an angled fin 215, any number can be arranged.Must have a vertical fins 210 and an angled fin 215 at least.Generally speaking, in N vertical fins 210 and the M angled fin 215, the relative drive strength of the adjustable drive strength FinFET of ordinary circumstance provides in formula 2.
β≈(W/L)(N+Mcos(θ)(1-0.9(|θ/45°|)))，|θ|<45° (2)
Wherein
β=transistorized relative drive strength;
The number of N=vertical fins;
The number of the angled fin of M=;
The channel width of each fin of W=;
The length of L=vertical fins; And
Angle (degree) between θ=vertical fins and the angled fin.
In a FinFET who only uses vertical fins, the graininess of controlling and driving intensity relates to the number of fin and very coarse, unless a prohibitive fin number is arranged.The drive strength that comprises the FinFET of at least one vertical fins and an angled fin, fin sum that not only can be by every type but also can adjust with respect to the angle of vertical fins by angled fin.This regulating degree only is confined to the increment control of this process, promptly under the carrier mobility that can realize, describe to change with the increment of fin angle (θ), and the minimum under the corresponding maximum angular (about 45 °) reduces (about 0.5).Being lower than about 0.5 increment can use a plurality of angled fins to obtain.See Table 1.
Table I
Drive strength (multiple of W/L) The vertical fins number Angled fin number Angle between vertical fins and the angled fin
3 3 0 N/A
4 4 0 N/A
3.8 3 1 ～10°
3.2 2 2 ～10°
Before describing the second embodiment of the present invention, term double grid and branch grid need definition.Double-gated transistor is defined as the transistors that contain two grid that rely on mutually, and under the situation of FinFET, grid are positioned on the counter wall of fin and electricity links to each other.They can also be mutually complete, shown in Fig. 4 A and 4B.A branch gate transistor is defined as the transistor that contains two independent gate, and under the situation of FinFET, grid are positioned on the counter wall of fin and on the electricity isolates mutually.
Fig. 4 A is to be end view by the line 4B-4B of Fig. 4 A according to FinFET transistor top view of second embodiment of the invention and Fig. 4 B.Among Fig. 4 A, FinFET 300 comprises parallel source/leakage 305A and 305B, and contacts the backward end that monocrystalline double grid fin 310 and monocrystalline divide grid fin 315 with electricity with physics.Monocrystalline double grid fin 310 is longitudinally parallel with the plane 320 that is parallel to each other with branch grid fin 315.Plane 320 is the plane of higher transoid carrier mobility, for example to the { 100} the and to { 110} of P FinFET of N FinFET.Double grid fin 310 and branch grid fin 315 are perpendicular to source/leakage 305A and 305B.A gate dielectric 330 is formed on the sidewall of double grid fin 310 and branch grid fin 315.The first grid 335 is formed on the double grid fin 310 and contacts the gate dielectric 330 that is formed on each double grid fin 310 all sidewall.The first grid 335 also contacts the gate dielectric 330 that is formed on the branch grid fin 315 first side 340A.345 contacts of second grid are formed on the gate dielectric 330 on branch grid fin 315 second sides.Double grid fin 305A has identical channel length L and has identical height (seeing Fig. 4 B) with branch grid fin 315.
Turn to Fig. 4 B, double grid fin 310 and branch grid fin 315 have height H as can be seen, and the end face 350 of double grid fin 310 is by dielectric cap 355 and the first grid 335 electric isolation.A dielectric cap 365 is formed on the end face 360 of branch grid fin 315.Note, may replace dielectric cap 355 and 365 with gate dielectric 330.Double grid fin 310 and branch grid fin 315 are formed on the end face 370 of an insulating barrier 375, and this insulating barrier is formed on the end face 380 of substrate 385.
In first example, FinFET 300 is N type FinFET, and source/leakage 305A and 305B are that the N type mixes, and double grid fin 310 and branch grid fin 315 comprise that P mixes, N light dope or intrinsic monocrystalline silicon, and plane 320 is { 100} directions.In second example, FinFET 300 is P type FinFET, and source/leakage 305A and 305B are that the P type mixes, and double grid fin 310 and branch grid fin 315 comprise that N mixes, P light dope or intrinsic monocrystalline silicon, and plane 320 is { 110} crystal faces.
No-voltage on second grid 345 divides the drive strength contribution of grid fin 315 to be about half that double grid fin 310 drive strength are contributed.Divide the drive strength contribution of grid fin 315 to change between zero-sum is identical with the contribution of double grid fin 310 drive strength, this realizes by the voltage that change is added on second grid 345.By increasing voltage (amplitude), divide the drive strength of grid fin 315 to increase from zero to the voltage that is added to the first grid 335 (amplitude).The more negative value of the source biasing by second grid 345 comparison N FinFET, perhaps compare P FinFET the source biasing more on the occasion of, divide the drive strength of grid fin 315 to reduce.
Although be illustrated in figures 4A and 4 B three double grid fins 310 and a branch grid fin 315, above a double grid fin 310, any number can be arranged, and above a branch grid fin 315, any number can be arranged.For example two outmost fins of a cover fin can be made composition grid fin easily.Inner fin can form branch grid fin, but needs more complicated grid shape layout (when when top view or plane graph are seen).
Many high performance cmos circuits need need drive strength ratio accurately between concrete PFET and NFET, in immunity to interference, obtain a kind of balance between performance and the power.Drive strength is by effective channel width-over-length ratio (W/L) of PFET given merchant of effective channel width-over-length ratio (W/L) divided by PFET than (also be called β than).Above-mentioned FinFET allows fine setting β ratio.
Transistor body among Fig. 5 and 6 (having got rid of source/leakage) is a formation from more a plurality of monocrystalline fins, may also be referred to as body describing Fig. 5 and 6 o'clock term fins like this.
Fig. 5 is to use the exemplary circuit of a FinFET, and its drive strength has been adjusted according to first embodiment of the invention.Among Fig. 5, a latch circuit 400 comprises transistor T 1, T2, T3 and an inverter I1.Transistor T 1, T2 and T3 are double-gated transistors.Transistor T 1 is shown a N FinFET who contains a fin 405.Transistor T 2 is shown a NFinFET who contains three vertical fins 410 and an angled fin 415 and a common gate.Angled fin 410 is also demarcated with symbol theta.Transistor T 3 is shown a P FinFET who contains four vertical fins 420 and a common gate.An input signal is coupled in the source of transistor T 1, and the grid of transistor T 1 are coupled to a CLK signal, and the leakage of transistor T 1 is coupled to the grid of transistor T 2 and T3, the input and output of the leakage of transistor T 2 and T3 and inverter I1.VSS is coupled in the source that VDD and transistor T 2 are coupled in the source of transistor T 3.
The drive strength of latch circuit 400 is than (also being generally called the β ratio) β T3/ β T2Can adjust (saying it is to make in the circuitry processes to be provided with on this meaning), by the fin 415 of transistor T 2 is turned to another direction to revolve with respect to fin 410, make and reduce the transoid carrier mobility in the fin 415 with respect to the transoid carrier mobility in the fin 410.
Although should be noted that only has transistor T 2 to be shown in Fig. 5 and to be described as drive strength adjustable, T2 and T3 any one or all can adjust drive strength according to first embodiment of the invention.
Fig. 6 is to use the exemplary circuit of a FinFET, and its drive strength has been adjusted according to second embodiment of the invention.Among Fig. 6, a latch circuit 450 comprises transistor T 4, T5, T6 and an inverter I2.Transistor T 4 is double-gated transistors.Transistor T 5 and T6 are each mixed gate FinFETs that contains a plurality of double grid fins and a branch grid fin.Transistor T 4 is shown a N FinFET who contains a double grid fin 455.Transistor T 5 is shown a N FinFET, contains three fins 460 and a fin 465, with the public first grid in fin 460 all grid regions and fin 465 first grid regions, and second grid that only connect fin 465 second grid regions.Transistor T 6 is shown a P FinFET, contains three fins 470 and a fin 475, with the public first grid in fin 470 all grid regions and fin 475 first grid regions, and second grid that only connect fin 475 second grid regions.An input signal is coupled in the source of transistor T 4, and the grid of transistor T 4 are coupled to a CLK signal, and the leakage of transistor T 4 is coupled to the first grid of transistor T 5 and T6, the input and output of the leakage of transistor T 5 and T6 and inverter I2.Second grid of transistor T 5 are coupled to a voltage source V TUNE-N, and second grid of transistor T 6 are coupled to a voltage source V TUNE-P.VSS is coupled in the source that VDD and transistor T 2 are coupled in the source of transistor T 6.
The drive strength of latch circuit 450 is than (also being generally called the β ratio) β T6/ β T5Can dynamically adjust (on this meaning, saying it is to be provided with in the course of the work), by adjusting VTUNE-N, VTUNE-P or VTUNE-N and VTUNE-P.Further, can set the voltage level of VTUNE-N and VTUNE-P, make the drive strength of latch circuit 450 compare β by programmable fuse T6/ β T5Permanent fixation.
Although should be noted that transistor T 5 and T6 are shown contains adjustable drive strength transistor, only there are needs to adjust drive strength among T5 and the T6 according to second embodiment of the invention.
Other circuit by method " adjustment " the drive strength ratio of the present invention first and second embodiment comprises, but be not limited to static RAM (SRAM) circuit, phase-locked loop (PLL) circuit, dynamically domino circuit, and non-equilibrium combination CMOS logical circuit.
Like this, the method that the invention provides fine setting drive strength FinFET and be used to finely tune drive strength FinFET.
Provide above being described in of the embodiment of the invention and be used to understand the present invention.Will be understood that the specific embodiment that the present invention is not limited to describe here, but it is suitable for various modifications, resets and substitute and do not deviate from scope of the present invention, this will become clearly for those skilled in the art.For example, in the first embodiment of the present invention, whole angled fin does not need to be set to respect to angle of vertical fins, but can crooked make the part of angled fin be parallel to a vertical fins and a part and vertical fins at an angle.Therefore, following claim has covered all such modification and changes within the spirit and scope of the present invention.

Claims (20)

1. electronic device comprises:
A source and a leakage;
Monocrystalline first fin, contain first and second opposite ends and the first and second opposite sidewalls, and first to second end along first longitudinal axis from described first fin extends, the described source of first end in contact of described first fin, and the described leakage of second end in contact of described first fin, described first longitudinal axis is parallel with a crystal face;
Monocrystalline second fin, contain first and second opposite ends and the first and second opposite sidewalls, and first to second end along second longitudinal axis from described second fin extends, the described source of first end in contact of described second fin, and the described leakage of second end in contact of described second fin, described second longitudinal axis and rotation are away from the plane parallel of described crystal face, wherein, angle between described first longitudinal axis and described second longitudinal axis is θ, | θ |＜45 °; And
A conductive gate and contacts at a gate dielectric that forms on first and second sidewalls of described first fin and on first and second sidewalls at described second fin,
Wherein, described device has a drive strength, and described drive strength is the function of angle between described first longitudinal axis and described second longitudinal axis.
2. according to the device of claim 1, wherein said crystal face contains first and second of quadrature, and first and second of quadrature are contained on described plane, and first of described crystal face and described plane first is parallel to each other.
3. according to the device of claim 1, wherein said source and leakage are that the N type mixes, and described first fin and described second fin comprise P doping, N light dope or intrinsic monocrystalline silicon independently, and described crystal face is that { 100} crystal face and described plane are towards { 110} crystal face rotation.
4. according to the device of claim 1, wherein said source and leakage are that the P type mixes, and described first fin and described second fin comprise N doping, P light dope or intrinsic monocrystalline silicon independently, and described crystal face is that { 110} crystal face and described plane are towards { 100} crystal face rotation.
5. according to the device of claim 1, wherein along the transoid carrier mobility of described first longitudinal axis than transoid carrier mobility height along described second longitudinal axis.
6. method that is used to adjust the electronic device drive strength comprises:
In monocrystal material, form a source and a leakage;
Form monocrystalline first fin from described monocrystal material, described first fin contains first and second opposite ends and the first and second opposite sidewalls, and first to second end along first longitudinal axis from described first fin extends, the described source of first end in contact of described first fin, and the described leakage of second end in contact of first fin;
Described first longitudinal axis is parallel with a crystal face of described monocrystal material;
Form monocrystalline second fin from described monocrystal material, described second fin contains first and second opposite ends and the first and second opposite sidewalls, and first to second end along second longitudinal axis from described second fin extends, the described source of first end in contact of described second fin, and the described leakage of second end in contact of second fin;
With described second longitudinal axis and rotation plane parallel away from described crystal face, wherein, the angle between described first longitudinal axis and described second longitudinal axis is θ, | θ |＜45 °;
A conductive gate is provided, and contacts at a gate dielectric that forms on first and second sidewalls of described first fin and on first and second sidewalls at described second fin; And
The drive strength of described electronic device is the function of angle between described first longitudinal axis and described second longitudinal axis.
7. according to the method for claim 6, wherein said crystal face contains first and second of quadrature, and first and second of quadrature are contained on described plane, and first of described crystal face and described plane first is parallel to each other.
8. according to the method for claim 6, wherein said source and leakage are that the N type mixes, and described first fin and described second fin comprise P doping, N light dope or intrinsic monocrystalline silicon independently, and described crystal face is that { 100} crystal face and described plane are towards { 110} crystal face rotation.
9. according to the method for claim 6, wherein said source and leakage are that the P type mixes, and described first fin and described second fin comprise N doping, P light dope or intrinsic monocrystalline silicon independently, and described crystal face is that { 110} crystal face and described plane are towards { 100} crystal face rotation.
10. according to the method for claim 6, wherein along the transoid carrier mobility of described first longitudinal axis than transoid carrier mobility height along described second longitudinal axis.
11. an integrated circuit comprises:
The first transistor, it comprises:
Leak in first source and first;
Monocrystalline first fin, contain first and second opposite ends and the first and second opposite sidewalls, and first to second end along first longitudinal axis from described first fin extends, first end in contact, first source of described first fin, and second end in contact, first leakage of described first fin, described first longitudinal axis is parallel with a crystal face;
Monocrystalline second fin, contain first and second opposite ends and the first and second opposite sidewalls, and first to second end along second longitudinal axis from described second fin extends, first end in contact, first source of described second fin, and second end in contact first of described second fin leaks, and described second longitudinal axis and rotation are away from the plane parallel of described crystal face, wherein, angle between described first longitudinal axis and described second longitudinal axis is θ, | θ |＜45 °; And
First conductive gate and contacts at a gate dielectric that forms on first and second sidewalls of described first fin and on first and second sidewalls at described second fin; And
Transistor seconds, it comprises:
Leak in second source and second;
Monocrystalline the 3rd fin, contain first and second opposite ends and the first and second opposite sidewalls, and first to second end along the 3rd longitudinal axis from described the 3rd fin extends, first end in contact, second source of described the 3rd fin, and second end in contact, second leakage of described first fin, described the 3rd longitudinal axis is parallel with described crystal face; And
Second conductive gate contacts with a gate dielectric that forms on first and second sidewalls of described the 3rd fin,
Wherein, the drive strength between described the first transistor and the described transistor seconds is than the function that is angle between described first longitudinal axis and described second longitudinal axis.
12. according to the circuit of claim 11, wherein said crystal face contains first and second of quadrature, first and second of quadrature are contained on described plane, and first of described crystal face and described plane first is parallel to each other.
13. circuit according to claim 11, leak in wherein said first source and first is that the N type mixes, leak in described second source and second is that the P type mixes, described first fin and described second fin comprise P doping, N light dope or intrinsic monocrystalline silicon independently, described the 3rd fin comprises N doping, P light dope or intrinsic monocrystalline silicon, described crystal face is { 100} a crystal face, and described plane is towards { 110} crystal face a rotation.
14. circuit according to claim 11, leak in wherein said first source and first is that the P type mixes, leak in described second source and second is that the N type mixes, described first fin and described second fin comprise N doping, P light dope or intrinsic monocrystalline silicon independently, described the 3rd fin comprises P doping, N light dope or intrinsic monocrystalline silicon, described crystal face is { 110} a crystal face, and described plane is towards { 100} crystal face a rotation.
15. according to the circuit of claim 11, wherein along the transoid carrier mobility of described first longitudinal axis than transoid carrier mobility height along described second longitudinal axis.
16. the method for the ratio of the drive strength in the adjustment integrated circuit between the first transistor and the transistor seconds comprises:
The first transistor is provided, and described the first transistor comprises:
Leak in first source and first;
Monocrystalline first fin, contain first and second opposite ends and the first and second opposite sidewalls, and first to second end along first longitudinal axis from described first fin extends, first end in contact, first source of described first fin, and second end in contact, first leakage of described first fin, described first longitudinal axis is parallel with a crystal face;
Monocrystalline second fin, contain first and second opposite ends and the first and second opposite sidewalls, and first to second end along second longitudinal axis from described second fin extends, first end in contact, first source of described second fin, and second end in contact first of described second fin leaks, and described second longitudinal axis and rotation are away from the plane parallel of described crystal face, wherein, angle between described first longitudinal axis and described second longitudinal axis is θ, | θ |＜45 °; And
First conductive gate and contacts at a gate dielectric that forms on first and second sidewalls of described first fin and on first and second sidewalls at described second fin; And
Transistor seconds is provided, and described transistor seconds comprises:
Leak in second source and second;
Monocrystalline the 3rd fin, contain first and second opposite ends and the first and second opposite sidewalls, and first to second end along the 3rd longitudinal axis from described the 3rd fin extends, first end in contact, second source of described the 3rd fin, and second end in contact, second leakage of described first fin, described the 3rd longitudinal axis is parallel with described crystal face; And
Second conductive gate contacts with a gate dielectric that forms on first and second sidewalls of described the 3rd fin,
Drive strength between wherein said the first transistor and the described transistor seconds is than the function that is angle between described first longitudinal axis and described second longitudinal axis.
17. according to the method for claim 16, wherein said crystal face contains first and second of quadrature, first and second of quadrature are contained on described plane, and first of described crystal face and described plane first is parallel to each other.
18. method according to claim 16, leak in wherein said first source and first is that the N type mixes, leak in described second source and second is that the P type mixes, described first fin and described second fin comprise P doping, N light dope or intrinsic monocrystalline silicon independently, described the 3rd fin comprises N doping, P light dope or intrinsic monocrystalline silicon, described crystal face is { 100} a crystal face, and described plane is towards { 110} crystal face a rotation.
19. method according to claim 16, leak in wherein said first source and first is that the P type mixes, leak in described second source and second is that the N type mixes, described first fin and described second fin comprise N doping, P light dope or intrinsic monocrystalline silicon independently, described the 3rd fin comprises P doping, N light dope or intrinsic monocrystalline silicon, described crystal face is { 110} a crystal face, and described plane is towards { 100} crystal face a rotation.
20. according to the method for claim 16, wherein along the transoid carrier mobility of described first longitudinal axis than transoid carrier mobility height along described second longitudinal axis.
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