JPH11220032A - Mos circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to simplify the manufacturing process and to suppress the high cost, by constituting the circuit which is constituted of a plurality of MOS transistors having the different threshold-value voltage by a plurality of MOS transistors, wherein the narrow-channel effect is generated and the different gate widths are provided. SOLUTION: A high threshold-value MOS transistor(Tr) has N1 (=5) pieces of Tr, has a gate width W1 and a high threshold-value voltage Vth1 . Furthermore, an intermediate threshold value MOSTr has N2 (=4) pieces of Tr, a gate width W2 and an intermediate threshold value voltage Vth2 . Furthermore, a low threshold value MOSTr has N3 (=1) pieces of Tr, a gate width W3 and a low-value threshold value voltage Vth3 . At this time when N1.W1=N2.W 2=N3.W3=W is set, the MOSTr, whose threshold voltages are different such as Vth1 , Vth2 and Vth3 , can be manufactured at the same width W. Thus, the circuit of one chip can be constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS circuit composed of a plurality of MOS transistors having different threshold voltages.

[0002]

2. Description of the Related Art Conventionally, in a MOS circuit composed of a plurality of MOS transistors having different threshold voltages, different threshold voltages of each MOS transistor are set by controlling an impurity concentration and an impurity distribution under a channel. Was done by doing. As an example of manufacturing MOS transistors having different threshold voltages by such a method, see Reference 1 “Shin'ichiro Mutoh et al., 1-V Power Supply Hig”.
h Speed Digital Circuit Technology with Multithres
hold-Voltage CMOS, IEEE Journal of Solid-State Cir
cuits, Vol. 30, No. 8, pp. 847, 1995. "

In recent years, in order to develop a low power consumption, high speed operation LSI, a plurality of MOs having different threshold voltages have been developed.
A MOS circuit using an S transistor is used. This is described, for example, in Reference 2 “S. Thompson et a
l., Dual Threshold Voltages and Substrate Bias: Ke
ys to High Performance, Low Power, 0.1μm Logic De
signs, 6B-1, 1997 Symposium on VlSI Technology Dige
st of Technical Papers. "and Reference 3" TCHolloway
et al., 0.18μm CMOS Technology for High-Performan
ce, Low-Power and RF Applications, 2-3, 197 Sympos
inu on VLSI technology Digest of Technical Paper
s. " In these examples, a method of controlling impurities under a channel is used to form MOS transistors having different threshold voltages.

[0004]

However, manufacturing transistors having different threshold voltages by controlling impurities under the channel complicates the manufacturing process and leads to an increase in cost.

The present invention has been made in view of the above points, and has as its object to control impurities without controlling them.
An object of the present invention is to realize a MOS circuit composed of a plurality of MOS transistors having different thresholds easily at a low cost.

[0006]

In order to achieve the above object, a MOS circuit according to the present invention has a different threshold voltage obtained by a difference in threshold voltage due to a narrow channel effect generated in a MOS transistor having a narrow gate width. It was composed of a plurality of transistors having a voltage.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention utilizes a change in threshold voltage due to a narrow channel effect generated in a MOS transistor. The threshold voltage of a MOS transistor changes as the gate width decreases. Regarding this, for example, in Reference 4, “KEKroell et al., Threshold Voltage of
Narrow Channel Field Effect Transistors, Solid -S
tate Electronics, Vol.19, pp.77, 1976. "

FIG. 4 is a graph showing the relationship between the gate width of the NMOS transistor and the threshold voltage, and shows the characteristics when the threshold voltage increases as the gate width decreases as a narrow channel effect. It is also known that a threshold voltage decreases as the gate width decreases as an inverse narrow channel effect depending on a manufacturing method of a MOS transistor. Here, these two phenomena are collectively called a narrow channel effect.

In a MOS transistor having a small gate width, a change in the gate width corresponds to a change in the threshold voltage. Therefore, MOS transistors having different threshold voltages can be formed by MOS transistors having different gate widths.

According to the present invention, when manufacturing a MOS circuit composed of a plurality of MOS transistors having different threshold voltages, different gates having a narrow channel effect without controlling the impurity concentration under the channel. It is composed of a plurality of MOS transistors having a width, and enables simplification of the manufacturing process and suppression of cost increase. Further, it becomes easy to manufacture a plurality of MOS transistors having a plurality of threshold voltages.

1 to 3 are explanatory diagrams of a MOS transistor according to the present invention. Note that these are merely examples, and it goes without saying that various changes or improvements can be made without departing from the spirit of the present invention.

FIG. 1 is a layout diagram of a high-threshold MOS transistor forming a part of a MOS circuit according to the present invention. 10 is a positive power supply, 11 is ground, 12 is a drain, 13
Is a gate, 14 is a source, 15 is a LOCO for element isolation.
S and 16 are contacts. The number of transistors is N1
(= 5). The gate width W1 corresponds to W1 in FIG.
The threshold voltage of this MOS transistor is high Vth1
Becomes By arranging one or more MOS transistors having the gate width W1, it is possible to supply a current suitable for the circuit.

FIG. 2 is a layout diagram of a middle threshold MOS transistor forming a part of the MOS circuit of the present invention. 20 is a positive power supply, 21 is a ground, 22 is a drain, 23
Is the gate, 24 is the source, 25 is the LOCO for element isolation
S and 26 are contacts. The number of transistors is N2
(= 4). The MOS transistor shown here has W
It has a gate width of W2 different from 1 and corresponds to W2 in FIG. 4, and the threshold voltage of this MOS transistor is Vth2 of a medium value.

FIG. 3 is a layout diagram of a low-threshold MOS transistor forming a part of the MOS circuit of the present invention. 30 is a positive power supply, 31 is ground, 32 is a drain, 33
Is a gate, 34 is a source, and 36 is a contact. The number of transistors is N3 (= 1). MO shown here
The S transistor has a gate width of W3 different from W1 and W2 and corresponds to W3 in FIG. 4, and the threshold voltage of this MOS transistor is a low value Vth3.

Here, assuming that N1 · W1 = N2 · W2 = N3 · W3 = W, the threshold voltage is Vth1, Vth2, Vt at the same width W.
MOS transistors different from h3 can be manufactured, and these can constitute a one-chip MOS circuit.

As described above, in the present invention, different threshold voltages Vth1, Vth2, and Vth2 are used by using a plurality of MOS transistors having different gate widths in which the narrow channel effect shown in FIGS. A MOS circuit including a plurality of MOS transistors having Vth3 can be designed and manufactured. At this time, it is not necessary to control the impurity concentration below the channel of each transistor.

[0017]

As described above, according to the present invention, a MOS circuit constituted by a plurality of MOS transistors having different threshold voltages can be realized without complicating the manufacturing process and increasing the cost. .

[Brief description of the drawings]

FIG. 1 is a layout diagram of a high threshold voltage NMOS transistor.

FIG. 2 is a layout diagram of a medium threshold voltage NMOS transistor.

FIG. 3 is a layout diagram of a low threshold voltage NMOS transistor.

FIG. 4 is a diagram showing an example of a relationship between a threshold voltage and a gate width in a MOS transistor.

[Explanation of symbols]

 10, 20, 30: power supply 11, 21, 31: ground 12, 22, 32: drain 13, 23, 33: gate 14, 24, 34: source 15, 25: LOCOS for element isolation 16, 26, 36: contact

Claims (1)

[Claims] 1. A MOS circuit comprising a plurality of transistors having different threshold voltages obtained by a difference in threshold voltage caused by a narrow channel effect generated in a MOS transistor having a narrow gate width. .