WO2008005026A1 - Method and apparatus for improving integrate circuit device performance using hydrid crystal orientations - Google Patents

Method and apparatus for improving integrate circuit device performance using hydrid crystal orientations Download PDF

Info

Publication number
WO2008005026A1
WO2008005026A1 PCT/US2006/026794 US2006026794W WO2008005026A1 WO 2008005026 A1 WO2008005026 A1 WO 2008005026A1 US 2006026794 W US2006026794 W US 2006026794W WO 2008005026 A1 WO2008005026 A1 WO 2008005026A1
Authority
WO
WIPO (PCT)
Prior art keywords
crystal lattice
lattice orientation
substrate
silicon
orientation
Prior art date
Application number
PCT/US2006/026794
Other languages
French (fr)
Inventor
Xudong Wang
John J. Perkarik
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to PCT/US2006/026794 priority Critical patent/WO2008005026A1/en
Publication of WO2008005026A1 publication Critical patent/WO2008005026A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Definitions

  • the present invention relates generally to integrated circuit devices, and, more particularly, to a method and apparatus for improving integrated circuit device performance using hybrid crystal orientations.
  • CMOS Complementary metal-oxide-semiconductor
  • ULSI ultra-large scale integrated
  • CMOS technology generally employs silicon (Si) wafers as the starting material for volume production. These silicon wafers generally have a single crystal surface that is (100) oriented; i.e., the normal to the silicon wafer surface is in the [100] direction.
  • MOSFETs planar metal-oxide- semiconductor field-effect transistors
  • Electrons are known to have a relatively high mobility for a (100) Si surface orientation, whereas holes are known to have high mobility for a (1 10) surface orientation. More specifically, hole mobility values for (100) Si are roughly two to four times lower than the corresponding electron mobility values for this crystallographic orientation. As a result, n-type devices formed in (100) silicon have a higher carrier mobility than p- type devices (with comparable device geometry) formed in (100) silicon. Thus, in order to compensate for this discrepancy, PFET devices are typically designed with larger widths with respect to NFET devices in order to balance the PFET pull-up currents against the NFET pull-down currents and achieve uniform circuit switching.
  • the method includes forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation, and forming a second device of the first conductivity type on a second portion of the substrate having a second crystal lattice orientation.
  • the carrier mobility of the first device formed on the first crystal lattice orientation is greater than the carrier mobility of the second device formed on the second crystal lattice orientation.
  • an apparatus method for implementing a desired offset in device characteristics of an integrated circuit includes a first device of a first conductivity type formed on a first portion of a substrate having a first crystal lattice orientation, and second device of the first conductivity type formed on a second portion of the substrate having a second crystal lattice orientation.
  • the carrier mobility of the first device formed on the first crystal lattice orientation is greater than the carrier mobility of the second device formed on the second crystal lattice orientation.
  • Figure 1 is a pair of graphs illustrating a comparison of electron and hole mobilities with respect to different crystal orientations
  • Figure 2 is a schematic diagram of an existing NFET current mirror device
  • Figure 3(a) is a schematic diagram of an NFET current mirror device in which one NFET is formed on a substrate of a first crystalline orientation, and another NFET is formed on a substrate of a second crystalline orientation, in accordance with an embodiment of the invention
  • Figure 3(b) is a schematic diagram of a PFET implementation of a current mirror device in accordance with another embodiment of the invention
  • Figure 4 is a schematic diagram of an existing constant transconductance circuit
  • Figure 5 is a schematic diagram of a constant transconductance circuit in which one NFET is formed on a substrate of a first crystalline orientation, and another NFET is formed on a substrate of a second crystalline orientation, in accordance with another embodiment of the invention;
  • Figure 6(a) and 6(b) illustrate an inverter pair, representing an additional application for an embodiment of the invention, in which the NFET and PFET devices of a first inverter are formed on substrates that increase respective carrier mobilities and the NFET and PFET devices of a second inverter are formed on substrates that decrease respective carrier mobilities; and
  • Figure 7 is a schematic diagram of a pair of ring oscillator circuits, illustrating one possible use for inverter pair configured in accordance with Figure 6(b).
  • Figure 21 BEST MODE FOR CARRYING OUT THE INVENTION
  • Para 22 Disclosed herein is a method and apparatus for improving integrated circuit device performance using hybrid crystal orientations. For certain integrated circuit applications, there is a benefit to having NFET (or PFET) pairs manufactured on hybrid substrates having different orientations. For example, an NFET (or PFET) pair formed with the same device geometry, but on substrates of different orientations, will primarily demonstrate the same electrical performance except for performance related to carrier mobility.
  • NFET (or PFET) pairs may be used in applications such as current/voltage generators, for example, or used to generate a repeatable offset in device characteristics, rather than for maximizing speed as previously used.
  • the existing approaches included, for example, varying the dimensions, operating conditions and/or process characteristics of the devices.
  • the present invention embodiments introduce a new approach in producing repeatable offsets for device pairs.
  • the present invention embodiments provide for a pair of MOS devices of the same conductivity and geometry (e.g., an NFET pair or PFET pair), in which one of the devices is formed on a substrate of a first crystal orientation and the other device is formed on a substrate of a different crystal orientation.
  • This pair of MOS devices may in turn be used to improve the matching performance of elements included within, for example, a current mirror, a constant-gm biasing circuit and/or any other device in which highly repeatable offset characteristics are desired.
  • a hybrid silicon structure is provided by physically bonding a first substrate of a (100) crystallographic orientation with a second substrate of a (1 10) crystallographic orientation.
  • Another possible approach to forming a pair of devices in different crystal orientations is to orient the two devices at 45- degree angles with respect to one another, as is described in M.
  • HOST Hybrid Orientation Substrate Technique
  • a current mirror is a circuit device used to produce an output current that has a fixed relationship or ratio to a reference current.
  • Current mirrors are one of the most popular circuit blocks used in integrated circuits. In a typical application, the fixed relationship of the generated output current is such that its value is usually either a multiple or a fraction of the value of reference current.
  • a conventional NFET implementation of a current mirror 200 is illustrated in the schematic diagram of Figure 2.
  • the device depicted by N2 in Figure 2 may actually be implemented by K individual NFETs connected in parallel with one another, with each of the K NFETs having the same geometry as NFET Nl .
  • Such a configuration is commonly configured through "multi-finger" devices, and generally works well so long as Nl and each of the individual NFETs of N2 have the same electrical performance.
  • a multi-finger device (such as might be embodied by N2) may demonstrate different electrical performance with respect to the single finger device (Nl ) as a result of different device stresses during the formation thereof.
  • N2 single finger device
  • a HOST pair as set forth in the present disclosure provides a novel way of implementing such a current mirror, because the variation in carrier mobility due to forming like conductivity devices on differently oriented substrate provides another design variable, in addition to device number and/or device size.
  • Figure 3(a) is a schematic of a NFET type current mirror 300 configured in accordance with an embodiment of the invention.
  • the Nl is formed on a portion of a substrate having a (1 10) orientation, while N2 is formed on another portion of the substrate having a (100) orientation.
  • the ratio of the output current to the reference current is dictated by the ratio of the carrier mobility (electron in this example) of N2 to the carrier mobility of Nl ; that is, lout/lref
  • Figure 3(b) is a PFET embodiment 302 of the current mirror shown in Figure 3(a), demonstrating the applicability of p-type devices to the HOST technique as well.
  • lout is also intended to be greater than l re f.
  • FIG. 32 Another example of a practical circuit to which the HOST pairs are applicable is a constant transconductance (g m ) circuit employing FET technology.
  • An example of a conventional transconductance circuit 400 is illustrated in the schematic diagram of Figure 4.
  • the transconductance circuit 400 includes a current mirror portion comprising PFETs TP6 and TPl 5 configured for equalizing the currents h , h, flowing therethrough.
  • the gate of PFET TP7 is also coupled to the gates of TP6 and TPl 5 to provide a mirrored output of Ii and I2 at lout.
  • the current mirror portion provides NFETs TN6 and TN7 for adjusting the drain voltage thereof.
  • the group of NFETs represented by M2 on the left side of the transconductance circuit 400 are configured to source the same amount of current as the single NFET Ml on the right side of the circuit 400.
  • effective size of the M2 channel width is N times the effective channel width of Ml , with N representing the dumber of parallel NFETs used for M2.
  • g m is a value independent with respect to temperature, supply voltage and MOS device parameters, which is a very desirable feature for the circuit design.
  • the present HOST technique can be used in such a constant transconductance circuit.
  • the embodiment of Figure 5 illustrates a constant g m circuit 500 built using a single pair of NFET devices.
  • the Ml NFET coupled to RB is formed on the (100) substrate having the higher carrier mobility, while the M2 NFET device on the opposite side is formed on the (1 1 0) substrate having the lower carrier mobility.
  • a similar circuit analysis reveals that the current h is given by:
  • ⁇ n i and ⁇ n 2 are the mobility of the electrons on the (100) substrate and (1 10) substrate respectively.
  • a PFET version of the constant transconductance circuit using the HOST technique could also be implemented.
  • Still another practical application of a HOST device pair is in conjunction with applications where a precision fixed delay is desired. Since HOST pairs provide a fixed current offset when biased at the same voltage, and since the offset is defined by the mobility of the FET, the repeatability of this offset is excellent.
  • FIG. 6(a) schematically represents an inverter pair, in which the upper inverter is intended to pass a signal quicker than the lower inverter, thereby generating a fixed delay with respect to Out 1 and Out 2.
  • Figure 6(b) A HOST based realization of this inverter pair, in accordance with still a further embodiment of the invention, is shown in Figure 6(b).
  • both the PFET device and NFET device of the first inverter are formed on respective substrates that enhance carrier mobility for quickest response time (i.e., the PFET on (1 10) silicon and the NFET on (100) silicon).
  • the PFET and NFET device of the second inverter are formed on respective substrates that reduce carrier mobility for a slower response time with respect to the first inverter (i.e., the PFET on (100) silicon and the NFET on (1 10) silicon).
  • an inverter pair according to the present hybrid substrate approach can further be used to create additional circuit functions, such as a pair of ring oscillators with a fixed frequency difference as shown in Figure 7.
  • the oscillators 702, 704 are formed through a chain of individual inverter elements.
  • the ring oscillators are conventionally designed to provide two different frequencies by either biasing the inverters of each ring oscillator at different voltages or by using different device sizes.
  • HOST devices to build the two ring oscillators 702, 704, the same biasing voltage can be used for each inverter along with FETs of like geometry.
  • the fixed offset is achieved by increasing the carrier mobility of an FET of a given conductivity and decreasing the carrier mobility of the same conductivity device in the other inverter.
  • This architecture significantly improves the matching performance and, since the same biasing voltage is applied, the biasing circuit is much simpler to design.

Abstract

A method for implementing a desired offset in device characteristics of an integrated circuit includes forming a first device of a first conductivity type (Nl ) on a first portion of a substrate (1 10) having a first crystal lattice orientation, and forming a second device of the first conductivity type (N2) on a second portion of the substrate (100) having a second crystal lattice orientation. The carrier mobility of the first device (Nl ) formed on the first crystal lattice orientation (1 1 0) is greater than the carrier mobility of the second device (N2) formed on the second crystal lattice orientation (100).

Description

METHOD AND APPARATUS FOR IMPROVING INTEGRATED CIRCUIT DEVICE PERFORMANCE USING HYBRID CRYSTAL ORIENTATIONS
[Para l ] TECHNICAL FIELD
[Para 2] The present invention relates generally to integrated circuit devices, and, more particularly, to a method and apparatus for improving integrated circuit device performance using hybrid crystal orientations.
BACKGROUND ART
[Para 3] Complementary metal-oxide-semiconductor (CMOS) technology is the predominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Conventional CMOS technology generally employs silicon (Si) wafers as the starting material for volume production. These silicon wafers generally have a single crystal surface that is (100) oriented; i.e., the normal to the silicon wafer surface is in the [100] direction. Hence, conventional planar metal-oxide- semiconductor field-effect transistors (MOSFETs) formed on (100) silicon wafers have a gate dielectric-channel interface plane that is in the (100) plane of the silicon substrate. [Para 4] Electrons are known to have a relatively high mobility for a (100) Si surface orientation, whereas holes are known to have high mobility for a (1 10) surface orientation. More specifically, hole mobility values for (100) Si are roughly two to four times lower than the corresponding electron mobility values for this crystallographic orientation. As a result, n-type devices formed in (100) silicon have a higher carrier mobility than p- type devices (with comparable device geometry) formed in (100) silicon. Thus, in order to compensate for this discrepancy, PFET devices are typically designed with larger widths with respect to NFET devices in order to balance the PFET pull-up currents against the NFET pull-down currents and achieve uniform circuit switching.
[Para 5] On the other hand, hole mobilities for (1 10) Si are about twice as high than for (100) Si. Consequently, PFETs formed on a (1 10) Si surface will exhibit significantly higher drive currents than PFETs formed on a (100) surface. Unfortunately, electron mobilities for (1 10) Si surfaces are significantly degraded as compared to (100) Si surfaces. A comparison of electron and hole mobilities with respect to different crystal orientations is illustrated in Figure 1 . As will be noted from a speed perspective, a (1 10) Si surface is optimal for PFET devices because of the excellent hole mobility, while a (100) Si surface is optimal for NFET devices because of the excellent electron mobility.
[Para 6] In order to fully utilize the advantage of the carrier mobility dependence on substrate orientation, various technologies of fabricating CMOS on hybrid substrates with different crystal orientations have been developed, in which the NFETs are manufactured at (100) surface orientations within the hybrid substrates, while the PFETs are manufactured at (1 10) surface orientations within the hybrid substrate. Because both types of devices (NFETs and PFETs) are operating with their respective carriers at peak mobilities, the resulting CMOS has overall higher speed and transconductance (or gain) as compared with a traditional CMOS structure where both the NFET and PFET are located on the same (100) substrate. In this application, the main benefit is the optimization of device performance since the PFET devices, being located on (1 10) substrates, now have comparable carrier mobilities as the (100) NFET devices.
[Para 7] In other instances, however, maximization of carrier mobility is not the desired goal of certain semiconductor devices. Thus, it is also desirable to be able to fabricate semiconductor devices having, for example, offset characteristics with respect to one another, and in a manner that conserves device real estate. [Para 8] DISCLOSURE OF THE INVENTION [Para 9] The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for implementing a desired offset in device characteristics of an integrated circuit. In an exemplary embodiment, the method includes forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation, and forming a second device of the first conductivity type on a second portion of the substrate having a second crystal lattice orientation. The carrier mobility of the first device formed on the first crystal lattice orientation is greater than the carrier mobility of the second device formed on the second crystal lattice orientation.
[Para 10] In another embodiment, an apparatus method for implementing a desired offset in device characteristics of an integrated circuit includes a first device of a first conductivity type formed on a first portion of a substrate having a first crystal lattice orientation, and second device of the first conductivity type formed on a second portion of the substrate having a second crystal lattice orientation. The carrier mobility of the first device formed on the first crystal lattice orientation is greater than the carrier mobility of the second device formed on the second crystal lattice orientation.
[Para 1 1 ] BRIEF DESCRIPTION OF THE DRAWINGS
[Para 12] Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
[Para 1 3] Figure 1 is a pair of graphs illustrating a comparison of electron and hole mobilities with respect to different crystal orientations;
[Para 14] Figure 2 is a schematic diagram of an existing NFET current mirror device; [Para 1 5] Figure 3(a) is a schematic diagram of an NFET current mirror device in which one NFET is formed on a substrate of a first crystalline orientation, and another NFET is formed on a substrate of a second crystalline orientation, in accordance with an embodiment of the invention; [Para 16] Figure 3(b) is a schematic diagram of a PFET implementation of a current mirror device in accordance with another embodiment of the invention;
[Para 1 7] Figure 4 is a schematic diagram of an existing constant transconductance circuit;
[Para 18] Figure 5 is a schematic diagram of a constant transconductance circuit in which one NFET is formed on a substrate of a first crystalline orientation, and another NFET is formed on a substrate of a second crystalline orientation, in accordance with another embodiment of the invention; [Para 19] Figure 6(a) and 6(b) illustrate an inverter pair, representing an additional application for an embodiment of the invention, in which the NFET and PFET devices of a first inverter are formed on substrates that increase respective carrier mobilities and the NFET and PFET devices of a second inverter are formed on substrates that decrease respective carrier mobilities; and
[Para 20] Figure 7 is a schematic diagram of a pair of ring oscillator circuits, illustrating one possible use for inverter pair configured in accordance with Figure 6(b). [Para 21 ] BEST MODE FOR CARRYING OUT THE INVENTION [Para 22] Disclosed herein is a method and apparatus for improving integrated circuit device performance using hybrid crystal orientations. For certain integrated circuit applications, there is a benefit to having NFET (or PFET) pairs manufactured on hybrid substrates having different orientations. For example, an NFET (or PFET) pair formed with the same device geometry, but on substrates of different orientations, will primarily demonstrate the same electrical performance except for performance related to carrier mobility. Advantageously, such NFET (or PFET) pairs may be used in applications such as current/voltage generators, for example, or used to generate a repeatable offset in device characteristics, rather than for maximizing speed as previously used. In previous applications where a repeatable offset is designed, the existing approaches included, for example, varying the dimensions, operating conditions and/or process characteristics of the devices. The present invention embodiments introduce a new approach in producing repeatable offsets for device pairs. [Para 23] Briefly stated, the present invention embodiments provide for a pair of MOS devices of the same conductivity and geometry (e.g., an NFET pair or PFET pair), in which one of the devices is formed on a substrate of a first crystal orientation and the other device is formed on a substrate of a different crystal orientation. This pair of MOS devices may in turn be used to improve the matching performance of elements included within, for example, a current mirror, a constant-gm biasing circuit and/or any other device in which highly repeatable offset characteristics are desired.
[Para 24] As indicated above, various techniques have been developed for forming a single, hybrid substrate having multiple crystal orientations. For example, in U.S. Patent Application Publication 2004/01 51 91 7, incorporated herein by reference in its entirety, a hybrid silicon structure is provided by physically bonding a first substrate of a (100) crystallographic orientation with a second substrate of a (1 10) crystallographic orientation. Another possible approach to forming a pair of devices in different crystal orientations is to orient the two devices at 45- degree angles with respect to one another, as is described in M. Shima, et al., "<100> Channel Strained-SiGe p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance", IEEE 2002 Symposium on VLSI Technology Digest of Technical Papers, pp. 94-95, incorporated herein by reference in its entirety. Regardless of how the different crystal orientations are realized for each device pair, the present approach exploits the conventional wisdom of using identical device layout in order to achieve optional matching characteristics, but further utilizes the difference in carrier mobility to achieve desired controlled offsets in circuit behavior. [Para 25] Referring once again to Figure 1 , it will be seen from the electron mobility curves therein that the electron mobility varies from about 100 cm2/V ■ S on a (1 10) Si substrate to about 260 cm2/V ■ S on a (1 00) Si substrate when the inversion charge density is about 9 x 1012 cm-2. If a bias voltage Vcs is applied to a particular NFET device, then the current therethrough will be given by the expression:
1 W
[Para 26] for the biasing condition of VDS > VGS-VTH. Given the same bias voltage, an NFET formed on a (100) oriented substrate will pass about 2.6 times more current than an NFET with identical geometry but formed on a (1 10) oriented substrate. In the present disclosure, such a pair is an example of what will be also referred to hereinafter as a Hybrid Orientation Substrate Technique (HOST) device pair. The specific properties of a HOST pair (i.e., a first device of a given conductivity formed on a substrate of a first crystalline orientation and a second device of the same conductivity formed on a substrate of a second crystalline orientation) make such a pair useful in various exemplary circuit designs presented below. [Para 27] For example, a current mirror is a circuit device used to produce an output current that has a fixed relationship or ratio to a reference current. Current mirrors are one of the most popular circuit blocks used in integrated circuits. In a typical application, the fixed relationship of the generated output current is such that its value is usually either a multiple or a fraction of the value of reference current. A conventional NFET implementation of a current mirror 200 is illustrated in the schematic diagram of Figure 2. Since both NFETs Nl and N2 are biased at the same gate voltage (Vgs), the ratio of the output current to the reference current corresponds to the ratio of the device width of N2 to the device width of Nl (i.e., lout/ lref = WN2/WNI), assuming that the device length of the Nl and N2 are the same. If the circuit design calls for a larger output current with respect to the reference current, then the current mirror circuit 200 is configured such that the effective device width of N2 is larger than the effective device width of Nl . Conversely, if a smaller magnitude of output current is desired with respect to the reference current, then Nl will have a larger effective device width than N2. Regardless of whether lout is larger or smaller than Iref, an integral multiple relationship between lref and lout is typically used in the design.
[Para 28] For example, if it is desired to configure the current mirror 200 such that the value of lout is K times the value of lref (with K being an integer), then the device depicted by N2 in Figure 2 may actually be implemented by K individual NFETs connected in parallel with one another, with each of the K NFETs having the same geometry as NFET Nl . Such a configuration is commonly configured through "multi-finger" devices, and generally works well so long as Nl and each of the individual NFETs of N2 have the same electrical performance. As a practical matter, however, a multi-finger device (such as might be embodied by N2) may demonstrate different electrical performance with respect to the single finger device (Nl ) as a result of different device stresses during the formation thereof. [Para 29] Accordingly, a HOST pair as set forth in the present disclosure provides a novel way of implementing such a current mirror, because the variation in carrier mobility due to forming like conductivity devices on differently oriented substrate provides another design variable, in addition to device number and/or device size. Figure 3(a) is a schematic of a NFET type current mirror 300 configured in accordance with an embodiment of the invention. As is illustrated, the Nl is formed on a portion of a substrate having a (1 10) orientation, while N2 is formed on another portion of the substrate having a (100) orientation. Where the NFET pair is constructed with the same device geometry, the ratio of the output current to the reference current is dictated by the ratio of the carrier mobility (electron in this example) of N2 to the carrier mobility of Nl ; that is, lout/lref
[Para 30] Thus, for equal device geometries, the value of lout will be roughly 2.6 times that of lref since Nl is formed on the (1 10) orientation Si substrate, which has a lower electron mobility than
NFET N2 formed on the (100) orientation. It will be appreciated that where this specific current offset (due to just the difference in substrate mobilities) is a desired amount, then the need for creating the NFET pair at different geometries or adding additional devices in parallel is obviated. However, it is also contemplated that the HOST technique disclosed herein could also be combined with existing methods of establishing the ratio of lout/lref, if other ratios are so desired. [Para 31 ] Figure 3(b) is a PFET embodiment 302 of the current mirror shown in Figure 3(a), demonstrating the applicability of p-type devices to the HOST technique as well. In this example, lout is also intended to be greater than lref. Thus, for this implementation, it is noted that P2 is formed on the (1 10) orientation substrate and Pl is formed on the (100) orientation substrate since the hole mobility is larger for the (1 10) orientation.
[Para 32] Another example of a practical circuit to which the HOST pairs are applicable is a constant transconductance (gm) circuit employing FET technology. An example of a conventional transconductance circuit 400 is illustrated in the schematic diagram of Figure 4. The transconductance circuit 400 includes a current mirror portion comprising PFETs TP6 and TPl 5 configured for equalizing the currents h , h, flowing therethrough. The gate of PFET TP7 is also coupled to the gates of TP6 and TPl 5 to provide a mirrored output of Ii and I2 at lout.
In addition, the current mirror portion provides NFETs TN6 and TN7 for adjusting the drain voltage thereof. As a result of the resistor RB, the group of NFETs represented by M2 on the left side of the transconductance circuit 400 are configured to source the same amount of current as the single NFET Ml on the right side of the circuit 400. Where the M2 devices are of equal channel length with respect to the Ml device, then effective size of the M2 channel width is N times the effective channel width of Ml , with N representing the dumber of parallel NFETs used for M2. The device characteristics are given by: h = (Vgsl -Vgs2) IRB
[Para 33] Since I1 = I2,
Figure imgf000013_0001
[Para 34] Thus, the transconductance of the circuit will be:
Figure imgf000013_0002
[Para 35] It can be seen that gm is a value independent with respect to temperature, supply voltage and MOS device parameters, which is a very desirable feature for the circuit design.
[Para 36] As is the case with a current mirror circuit, the present HOST technique can be used in such a constant transconductance circuit. Instead of having N number of NFET devices in parallel on one side of the circuit, the embodiment of Figure 5 illustrates a constant gm circuit 500 built using a single pair of NFET devices. In this instance, the Ml NFET coupled to RB is formed on the (100) substrate having the higher carrier mobility, while the M2 NFET device on the opposite side is formed on the (1 1 0) substrate having the lower carrier mobility. A similar circuit analysis reveals that the current h is given by:
Figure imgf000014_0001
[Para 37] with the transconductance given by
Figure imgf000014_0002
[Para 38] wherein μni and μn2 are the mobility of the electrons on the (100) substrate and (1 10) substrate respectively. As should be appreciated, a PFET version of the constant transconductance circuit using the HOST technique could also be implemented. [Para 39] Still another practical application of a HOST device pair is in conjunction with applications where a precision fixed delay is desired. Since HOST pairs provide a fixed current offset when biased at the same voltage, and since the offset is defined by the mobility of the FET, the repeatability of this offset is excellent. For example, in a D flip-flop, inverter or a buffer, a signal delay therethrough is proportional to the biasing current; thus, a fixed signal delay can be generated when a HOST pair is used in such devices. Figure 6(a) schematically represents an inverter pair, in which the upper inverter is intended to pass a signal quicker than the lower inverter, thereby generating a fixed delay with respect to Out 1 and Out 2. A HOST based realization of this inverter pair, in accordance with still a further embodiment of the invention, is shown in Figure 6(b). As is shown, both the PFET device and NFET device of the first inverter are formed on respective substrates that enhance carrier mobility for quickest response time (i.e., the PFET on (1 10) silicon and the NFET on (100) silicon). In contrast, the PFET and NFET device of the second inverter are formed on respective substrates that reduce carrier mobility for a slower response time with respect to the first inverter (i.e., the PFET on (100) silicon and the NFET on (1 10) silicon). [Para 40] Thus configured, an inverter pair according to the present hybrid substrate approach can further be used to create additional circuit functions, such as a pair of ring oscillators with a fixed frequency difference as shown in Figure 7. The oscillators 702, 704, are formed through a chain of individual inverter elements. When used in a jitter test system for example, the ring oscillators are conventionally designed to provide two different frequencies by either biasing the inverters of each ring oscillator at different voltages or by using different device sizes. However, by using HOST devices to build the two ring oscillators 702, 704, the same biasing voltage can be used for each inverter along with FETs of like geometry. Again, the fixed offset is achieved by increasing the carrier mobility of an FET of a given conductivity and decreasing the carrier mobility of the same conductivity device in the other inverter. This architecture significantly improves the matching performance and, since the same biasing voltage is applied, the biasing circuit is much simpler to design.
[Para 41 ] While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

What is claimed is:
[Claim 1 ] 1 . A method for implementing a desired offset in device characteristics of an integrated circuit, the method comprising: forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation; and forming a second device of said first conductivity type on a second portion of said substrate having a second crystal lattice orientation; wherein the carrier mobility of said first device formed on said first crystal lattice orientation is greater than the carrier mobility of said second device formed on said second crystal lattice orientation.
[Claim 2] 2. The method of claim 1 , wherein said first and said second device are configured with the same geometry.
[Claim 3] 3. The method of claim 1 , wherein: said first conductivity type is n-type; said first crystal lattice orientation comprises (100) silicon; and said second crystal lattice orientation comprises (110) silicon.
[Claim 4] 4. The method of claim 1 , wherein: said first conductivity type is p-type; said first crystal lattice orientation comprises (110) silicon; and said second crystal lattice orientation comprises (100) silicon.
[Claim 5] 5. The method of claim 1 , wherein said substrate further comprises a hybrid substrate formed by bonding a substrate of said first crystal lattice orientation with a substrate of said second crystal lattice orientation.
[Claim 6] 6. The method of claim 1 , wherein said first and said second crystal lattice orientations are achieved by forming said first and second devices at a 45 degree orientation with respect to one another.
[Claim 7] 7. The method of claim 1 , wherein said first and second devices are formed within a common circuit.
[Claim 8] 8. The method of claim 7, wherein said common circuit is a current mirror device.
[Claim 9] 9. The method of claim 7, wherein said common circuit is a constant transconductance circuit.
[Claim 1 0] 10. The method of claim 7, wherein said common circuit is an inverter based delay element.
[Claim 1 I ] I l . An apparatus for implementing a desired offset in device characteristics of an integrated circuit, comprising: a first device of a first conductivity type formed on a first portion of a substrate having a first crystal lattice orientation; and a second device of said first conductivity type formed on a second portion of said substrate having a second crystal lattice orientation; wherein the carrier mobility of said first device formed on said first crystal lattice orientation is greater than the carrier mobility of said second device formed on said second crystal lattice orientation.
[Claim 1 2] 1 2. The apparatus of claim 1 1 , wherein said first and said second device are configured with the same geometry.
[Claim 1 3] 1 3. The apparatus of claim 1 1 , wherein: said first conductivity type is n-type; said first crystal lattice orientation comprises (100) silicon; and said second crystal lattice orientation comprises (110) silicon.
[Claim 1 4] 14. The apparatus of claim 1 1 , wherein: said first conductivity type is p-type; said first crystal lattice orientation comprises (110) silicon; and said second crystal lattice orientation comprises (100) silicon.
[Claim 1 5] 1 5. The apparatus of claim 1 1 , wherein said substrate further comprises a hybrid substrate formed by bonding a substrate of said first crystal lattice orientation with a substrate of said second crystal lattice orientation.
[Claim 1 6] 16. The apparatus of claim 1 1 , wherein said first and said second crystal lattice orientations are achieved by forming said first and second devices at a 45 degree orientation with respect to one another.
[Claim 1 7] 1 7. The apparatus of claim 1 1 , wherein said first and second devices are formed within a common circuit.
[Claim 1 8] 1 8. The apparatus of claim 1 7, wherein said common circuit is a current mirror device.
[Claim 1 9] 1 9. The apparatus of claim 1 7, wherein said common circuit is a constant transconductance circuit.
[Claim 20] 20. The apparatus of claim 1 7, wherein said common circuit is an inverter based delay element.
[Claim 21 ] 21 . A method for implementing a desired offset in device characteristics of an integrated circuit, the method comprising: forming a first FET of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation; and forming a second FET of said first conductivity type on a second portion of said substrate having a second crystal lattice orientation, said second FET having the same device geometry as said first FET; wherein the carrier mobility of said first device formed on said first crystal lattice orientation is greater than the carrier mobility of said second device formed on said second crystal lattice orientation.
[Claim 22] 22. The method of claim 21 , wherein: said first and second FETs are NFET type; said first crystal lattice orientation comprises (100) silicon; and said second crystal lattice orientation comprises (110) silicon.
[Claim 23] 23. The method of claim 21 , wherein: said first and second FETs are PFET type; said first crystal lattice orientation comprises (110) silicon; and said second crystal lattice orientation comprises (100) silicon.
[Claim 24] 24. The method of claim 21 , wherein said substrate further comprises a hybrid substrate formed by bonding a substrate of said first crystal lattice orientation with a substrate of said second crystal lattice orientation.
[Claim 25] 25. The method of claim 1 , wherein said first and said second crystal lattice orientations are achieved by forming said first and second devices at a 45 degree orientation with respect to one another.
[Claim 26] 26. The method of claim 21 , wherein said first and second FETs are formed within a common circuit, said common circuit further comprising one of: a current mirror device, a constant transconductance circuit, and an inverter based delay element.
[Claim 27] 27. An apparatus for implementing a desired offset in device characteristics of an integrated circuit, comprising: a first FET of a first conductivity type formed on a first portion of a substrate having a first crystal lattice orientation; and a second FET of said first conductivity type formed on a second portion of said substrate having a second crystal lattice orientation, said second FET having the same device geometry as said first FET; wherein the carrier mobility of said first device formed on said first crystal lattice orientation is greater than the carrier mobility of said second device formed on said second crystal lattice orientation.
[Claim 28] 28. The apparatus of claim 27, wherein: said first and second FETs are NFET type; said first crystal lattice orientation comprises (100) silicon; and said second crystal lattice orientation comprises (110) silicon.
[Claim 29] 29. The apparatus of claim 27, wherein: said first and second FETs are PFET type; said first crystal lattice orientation comprises (110) silicon; and said second crystal lattice orientation comprises (100) silicon.
[Claim 30] 30. The apparatus of claim 27, wherein said first and second FETs are formed within a common circuit, said common circuit further comprising one of: a current mirror device, a constant transconductance circuit, and an inverter based delay element.
PCT/US2006/026794 2006-07-07 2006-07-07 Method and apparatus for improving integrate circuit device performance using hydrid crystal orientations WO2008005026A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2006/026794 WO2008005026A1 (en) 2006-07-07 2006-07-07 Method and apparatus for improving integrate circuit device performance using hydrid crystal orientations

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2006/026794 WO2008005026A1 (en) 2006-07-07 2006-07-07 Method and apparatus for improving integrate circuit device performance using hydrid crystal orientations

Publications (1)

Publication Number Publication Date
WO2008005026A1 true WO2008005026A1 (en) 2008-01-10

Family

ID=38894870

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/026794 WO2008005026A1 (en) 2006-07-07 2006-07-07 Method and apparatus for improving integrate circuit device performance using hydrid crystal orientations

Country Status (1)

Country Link
WO (1) WO2008005026A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384473A (en) * 1991-10-01 1995-01-24 Kabushiki Kaisha Toshiba Semiconductor body having element formation surfaces with different orientations
US5714906A (en) * 1995-08-14 1998-02-03 Motamed; Ali Constant transductance input stage and integrated circuit implementations thereof
US6275079B1 (en) * 1999-02-25 2001-08-14 Hyundai Electronics Industries Co., Ltd. Analog delay locked loop circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384473A (en) * 1991-10-01 1995-01-24 Kabushiki Kaisha Toshiba Semiconductor body having element formation surfaces with different orientations
US5714906A (en) * 1995-08-14 1998-02-03 Motamed; Ali Constant transductance input stage and integrated circuit implementations thereof
US6275079B1 (en) * 1999-02-25 2001-08-14 Hyundai Electronics Industries Co., Ltd. Analog delay locked loop circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SHIMA M.: "<100> Channel Strained-SiGe p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance", 2002 SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS, pages 94 - 95 *

Similar Documents

Publication Publication Date Title
Shaikh et al. Drain-engineered TFET with fully suppressed ambipolarity for high-frequency application
US9219065B2 (en) Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETS
TWI225763B (en) Circuit including forward body bias from supply voltage and ground nodes
Bryant et al. Low-power CMOS at Vdd= 4kT/q
US6496056B1 (en) Process-tolerant integrated circuit design
US20040075149A1 (en) CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
Su et al. Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies
JP2004523103A (en) CMOS inverter circuit using strained silicon surface channel MOSFET
US20080185662A1 (en) Structure and method for forming asymmetrical overlap capacitance in field effect transistors
EP1340253A2 (en) Cmos fabrication process utilizing special transistor orientation
CN107731809B (en) Temperature effect compensation in semiconductor device structures
TW200539425A (en) Integrated circuit with strained and non-strained transistors, and method of forming thereof
US7666720B2 (en) Method and apparatus for improving integrated circuit device performance using hybrid crystal orientations
WO2008005026A1 (en) Method and apparatus for improving integrate circuit device performance using hydrid crystal orientations
JPS6170748A (en) Semiconductor device
Suddapalli et al. Analog/RF performance of graded channel gate stack triple material double gate strained-Si MOSFET with fixed charges
Bhattacharjee et al. VLSI Transistor and Interconnect Scaling Overview
Mathew et al. Characterization and profile optimization of SiGe pFETs on silicon-on-sapphire
US11011642B2 (en) Ambipolar field-effect device using engineered work-functions
US7784004B1 (en) Skew lots for IC oscillators and other analog circuits
JPH04370965A (en) Semiconductor device
KR20060042171A (en) High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof
Schram et al. Wafer scale integration of $\mathbf {MX} _ {2} $ based NMOS only ring oscillators on 300 mm wafers
JPS6235667A (en) Manufacture of semiconductor device
Shiho et al. Moderately doped channel multiple-finFET for logic applications

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 06786825

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: RU

122 Ep: pct application non-entry in european phase

Ref document number: 06786825

Country of ref document: EP

Kind code of ref document: A1