JPH04370965A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an accurate delay time in a delay-time forming circuit by installing a capacitor formed by connecting each parasitic capacitance of first and second MOS transistors in parallel to a semiconductor device and forming the semiconductor device so that the electrostatic capacitance of the capacitor reaches an approximately fixed value when parasitic capacitance depending upon voltage difference changes. CONSTITUTION:P channel and N channel MOS transistors 13, 14 are formed onto a P-type substrate 11 as a pair while holding a field oxide film 12. Both gates G of the P channel and N channel transistors 13, 14 are connected in common by aluminum electrodes, each source S and srain D of both transistors are also connected mutually while the mutually bonded sources S and drains D of each transistor 13, 14 are bonded in common, and a pair of terminals 22, 23 of the capacitance element are formed while being extended from the connected nodes 20, 21 in common of each transistor. The voltage characteristics of the whole synthesized capacitance element are flattened approximately, thus reducing the voltage dependency of a capacitance value.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a monolithic semiconductor integrated circuit device including a capacitive element.

In a monolithic semiconductor integrated circuit device, there is an example in which a capacitive element (capacitor) is constituted by a MOS transistor having a commonly connected source and drain. Such a capacitive element is generally composed of a depletion type MOS transistor,
A parasitic capacitance is formed between the commonly connected sources and drains and the gates of the MOS transistors, and the commonly connected sources and drains and the gates form both terminals of the capacitive element. .

0003

2. Description of the Related Art FIG. 6 shows an example of a delay time generating circuit that generates a delay time using a capacitive element composed of a conventional MOS transistor. In the figure, a signal from an input terminal 5 is transmitted as an in-phase signal via inverters 6 and 8, but a capacitive element 7 consisting of a MOS transistor is connected to a node between the input and output of both inverters 6 and 8. A and ground, and this capacitive element 7 provides a predetermined delay time (
t1-to) is provided. Capacitive element 7 is composed of an N-channel MOS transistor, and its source and drain are commonly connected, and the source, drain, and gate form a pair of terminals.

0004

[Problems to be Solved by the Invention] Generally, in a MOS transistor, a channel is formed according to the voltage applied between the source and gate, and the channel width changes.
In a capacitive element made of a MOS transistor, the capacitance (capacitance value) changes depending on the terminal voltage between the gate, source, and drain. Therefore, in the case of the delay time generation circuit that obtains a constant delay time using such a capacitive element, there is a problem that it is difficult to calculate and obtain an accurate delay time in advance.

FIG. 7 is a diagram illustrating the voltage dependence of a capacitive element made of this type of N-channel transistor. As shown in Figure 6, an N-channel transistor has an input voltage applied to its gate, and its source and drain are connected to GN.
Connected to the D terminal. FIG. 7 is a voltage characteristic diagram of the capacitance value when the voltage applied to the gate terminal changes quickly (for example, 100 Hz or more).
The input voltage (V) applied to the gate, that is, the gate-source-drain voltage is shown on the horizontal axis. As shown in the figure, the capacitance value of this capacitive element decreases as the terminal voltage decreases, and especially when the terminal voltage decreases below the threshold voltage, parasitic capacitance increases between the gate and source drain. This results in a capacitance between the capacitance and the substrate on which it is formed, and the capacitance value decreases significantly.

As shown in the voltage characteristic diagram above,
This is especially true when this capacitive element is used in a delay time generation circuit, etc., or in another circuit where the voltage between terminals changes in the positive and negative directions across the threshold voltage of the MOS transistor. However, there is a problem that a desired and accurate capacitance value cannot be obtained. However, focusing on this point, a capacitive element made of a MOS transistor that can obtain a capacitance value with flat voltage characteristics has not been known.

In view of the above problems, the present invention provides a semiconductor device including a capacitive element consisting of a MOS transistor.
To obtain a capacitive element whose capacitance value changes little with respect to changes in the voltage value applied between the terminals of the capacitive element and its polarity, and to obtain an accurate delay time in, for example, a delay time generation circuit. An object of the present invention is to provide a semiconductor device with the following features.

[0008]

[Means for Accomplishing the Object] FIG. 1 is a diagram showing the principle of the present invention. In the figure, 1 and 2 are the first and second M
OS transistors 3 and 4 are capacitor terminals, respectively.

In order to achieve the above object, the semiconductor device of the present invention has a source and a drain connected in common, as shown in FIG. The first and second MOS transistors each have a parasitic capacitance that changes depending on the voltage difference applied between the common connection terminal and the gate electrode, and the first and second MOS transistors (1 , 2) has a capacitor formed by connecting the parasitic capacitances in parallel, and when the parasitic capacitance of each of the first and second MOS transistors (1, 2) changes depending on the voltage difference, The capacitor is characterized in that it is formed so that the capacitance of the capacitor is approximately constant.

0010

[Operation] In the capacitor of the semiconductor device of the present invention, the parasitic capacitances consisting of the first and second MOS transistors 1 and 2 are connected in parallel to each other, and the electrostatic capacitance depending on the voltage change of each MOS transistor is By configuring the capacitor so that the capacitance of the capacitor becomes a substantially constant value when the capacitance changes, the capacitor can have a substantially constant capacitance value without depending on the terminal voltage.

[0011]

Embodiment Referring to FIG. 2, the structure of a capacitive element in a semiconductor device according to a first embodiment of the present invention will be described. FIG. 2 is a circuit diagram showing the configuration of this capacitive element. In the figure, this capacitive element is a P channel and an N channel M.
A configuration in which the OS transistors 1 and 2 are connected in parallel, that is, the gates of both are connected to each other to form one terminal 3, and the commonly connected sources and drains of both are connected to each other to form the other terminal. It is.

FIG. 5 schematically shows a cross section of the capacitive element shown in FIG. 2 and its wiring connection structure. In the figure, a field oxide film 12 is formed on a p-type substrate 11.
P-channel and N-channel MOS transistors 13 and 14 are formed as a pair with each other sandwiched therebetween. In the capacitive element portion consisting of the P-channel transistor 13, an N-well (n-region) for forming the P-channel transistor is formed.
15 is formed, and in order to set the threshold voltage Vth2 low in the channel 16 portion directly below the gate G,
Only a very small concentration of B (boron) is implanted.

A thin layer of polycrystalline silicon 18 forming a gate electrode is formed on the channel 16 via a silicon oxide 17, and a p+ layer forming a source S and a drain D is formed in the N-well 15. is formed by ion implantation.

In the capacitive element portion consisting of the N-channel transistor 14, the portion of the p-region of the substrate 11 separated by the field oxide film becomes a region where the N-channel transistor is formed, and a high threshold voltage Vth1 is applied to the channel 19 portion. A very small amount of P (
A gate G portion is formed on the channel 19 in the same manner as the gate portion of a P-channel transistor, and an n+
The layers are also formed by ion implantation.

P-channel and N-channel transistor 1
The gates G of both transistors 3 and 14 are commonly connected by an aluminum electrode, and the respective sources S and drains D of both transistors are also mutually connected, and the mutually connected sources S and drains D of the respective transistors 13 and 14 are connected to each other. are commonly connected, and a pair of terminals 22, 23 of this capacitive element are formed extending from the commonly connected nodes 20, 21, respectively.

The operation of the capacitive element of the semiconductor device of the above embodiment will be explained with reference to FIG. In FIG. 4, curves A, B, and C represent the capacitance characteristics of the capacitive element portion made of N-channel transistors, the capacitance characteristics of the capacitive element portion made of P-channel transistors, and the capacitance characteristics of the synthesized capacitive element of the present invention, respectively. This is an illustrative curve. Note that, as explained in the conventional diagram, the frequency of voltage change is 100H.
z or more and the voltage polarity is such that the voltage applied to the gate is in the positive direction.

As shown in FIG. 4, the capacitance characteristics A and B of each transistor depend on the voltage between the terminals, but since they are canceled out by the voltage characteristics of both transistors, the voltage of the entire capacitive element is the sum of these characteristics. The characteristic C becomes almost flat, and the voltage dependence of the capacitance value becomes small. Note that in order to flatten the capacitance value, the voltage dependence of the parasitic capacitance of each transistor is formed to have a desired characteristic so that the sum of the capacitance characteristics A and B of both transistors becomes a constant value. The threshold voltages Vth1 and Vth2 of both N-channel and P-channel transistors can be independently set and controlled with good reproducibility by appropriately setting process conditions and adjusting the concentration of the diffusion layer. Therefore, the protrusion m in the C curve shown in FIG. 2 is, for example, N
Channel transistor threshold voltage Vth
It is possible to make it even smaller by making 1 slightly higher than shown in the figure.

[0018] A capacitive element consisting of a MOS transistor is
This method has been increasingly used recently because it can be performed at the same time as the process of forming other transistor parts of the semiconductor device, and the number of manufacturing steps is reduced, which reduces the manufacturing cost of the semiconductor device. The range of applications of the capacitive element, which is composed of the P-channel and N-channel transistors and whose capacitance value is small in voltage dependence, is extremely wide.

FIG. 3 is a circuit diagram of a capacitive element in a semiconductor device according to a second embodiment of the present invention. As shown in the figure, in this embodiment, both the first and second MOS transistors are configured as N-channel MOS transistors. In this case, by connecting the gate, commonly connected source and drain of the first MOS transistor to the commonly connected source, drain and gate of the second MOS transistor, both transistors are connected in antiparallel. With this configuration, the capacitance values that vary depending on the terminal voltages in both transistors compensate each other, and the capacitance value of the capacitor element as a whole becomes constant.

Note that instead of the second embodiment, both the first and second MOS transistors are configured as P-channel transistors, and both transistors are connected in antiparallel as in the second embodiment. You can also. In the case of the second embodiment, regardless of whether a P-channel or an N-channel transistor is adopted, the capacitance characteristics of the parasitic capacitance of the transistor are determined by setting the concentration of the source/drain diffusion layer, and adjusting the gate length or gate width of the transistor, respectively. Various settings can be made by changing. That is, setting by gate width changes the threshold value of the MOS transistor by utilizing the short channel effect that causes the threshold value to depend on the gate width. In this case, since it is configured as a MOS capacitor, it does not operate as a normal switching element, and problems due to short channel effects do not occur.

[0021]

As explained above, according to the present invention, it is possible to provide a capacitor composed of a MOS transistor whose capacitance is small in voltage dependence, and it is remarkable that the design of a semiconductor device including a delay time generation circuit, etc. is facilitated. It has a great effect.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a circuit diagram of a capacitive element of the semiconductor device of the first embodiment.

FIG. 3 is a circuit diagram of a capacitive element of a semiconductor device according to a second embodiment.

FIG. 4 is an action explanatory diagram for explaining the capacitance characteristics of the capacitive element in FIG. 2;

5 is a schematic diagram showing a cross section and wiring configuration showing the structure of a capacitive element portion in FIG. 2; FIG.

FIG. 6 is a circuit diagram of a conventional delay time generation circuit.

FIG. 7 is an explanatory diagram of capacitance characteristics of a capacitive element of a conventional semiconductor device.

[Explanation of symbols]

1: First MOS transistor 2: Second MOS transistor 3, 4, 22, 23: terminal 7: Capacitive element (capacitor) 11: P type board 13: P channel transistor 14: N-channel transistor 15:N well 16, 19: Channel S: sauce D: Drain G: Gate

Claims (3)

[Claims] Claim 1: A source and a drain are each connected in common,
first and second MOS transistors in which a parasitic capacitance formed parasitically between the common connection end and the gate electrode changes depending on a voltage difference applied between the common connection end and the gate electrode; The first and second MOS transistors (1, 2) have a capacitor formed by connecting the parasitic capacitances of each of the first and second MOS transistors (1, 2) in parallel; 2.) A semiconductor device characterized in that the capacitor is formed so that the capacitance of the capacitor becomes a substantially constant value when the parasitic capacitance changes depending on the voltage difference. 2. The first and second MOS transistors are each composed of a P-channel transistor and an N-channel transistor, and the gate electrodes and the common connection terminals of both the P-channel and N-channel transistors are connected to each other, respectively. The semiconductor device according to claim 1, characterized in that: 3. The first and second MOS transistors are configured as transistors of the same conductivity type, and the gate electrode and the common connection end of the first MOS transistor are respectively connected to the second MOS transistor. 2. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the common connection end and the gate electrode.