CN100521542C - Pll电路的∑△调制器 - Google Patents
Pll电路的∑△调制器 Download PDFInfo
- Publication number
- CN100521542C CN100521542C CNB028295587A CN02829558A CN100521542C CN 100521542 C CN100521542 C CN 100521542C CN B028295587 A CNB028295587 A CN B028295587A CN 02829558 A CN02829558 A CN 02829558A CN 100521542 C CN100521542 C CN 100521542C
- Authority
- CN
- China
- Prior art keywords
- signal
- adder
- delta modulator
- spill over
- differentiator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3006—Compensating for, or preventing of, undesired influence of physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
- H03M7/3026—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
- H03M7/3033—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs
- H03M7/304—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims (14)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2002/013701 WO2004062107A1 (ja) | 2002-12-26 | 2002-12-26 | Pll回路のσδ変調器 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1669223A CN1669223A (zh) | 2005-09-14 |
CN100521542C true CN100521542C (zh) | 2009-07-29 |
Family
ID=32697318
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB028295587A Expired - Fee Related CN100521542C (zh) | 2002-12-26 | 2002-12-26 | Pll电路的∑△调制器 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7388438B2 (zh) |
JP (1) | JP3792706B2 (zh) |
CN (1) | CN100521542C (zh) |
WO (1) | WO2004062107A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE60314020T2 (de) * | 2003-11-28 | 2007-09-13 | Fujitsu Ltd., Kawasaki | Sd-modulator einer pll-schaltung |
KR100666479B1 (ko) * | 2004-08-30 | 2007-01-09 | 삼성전자주식회사 | 시그마 델타 변조기를 공유하는 수신 및 송신 채널 분수분주 위상 고정 루프를 포함한 주파수 합성기 및 그 동작방법 |
KR100684053B1 (ko) * | 2005-02-14 | 2007-02-16 | 삼성전자주식회사 | 시그마 델타 변조 장치, 이를 이용한 주파수 합성기 및 분수 분주 주파수 합성 방법 |
US8594770B2 (en) * | 2006-06-29 | 2013-11-26 | Accuvein, Inc. | Multispectral detection and presentation of an object's characteristics |
US8587352B2 (en) * | 2011-09-16 | 2013-11-19 | Infineon Technologies Austria Ag | Fractional-N phase locked loop |
JP6882094B2 (ja) * | 2017-06-23 | 2021-06-02 | 日本無線株式会社 | Pll回路 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5305362A (en) * | 1992-12-10 | 1994-04-19 | Hewlett-Packard Company | Spur reduction for multiple modulator based synthesis |
JP3536073B2 (ja) | 1995-05-24 | 2004-06-07 | アジレント・テクノロジーズ・インク | 分周器 |
US5986512A (en) | 1997-12-12 | 1999-11-16 | Telefonaktiebolaget L M Ericsson (Publ) | Σ-Δ modulator-controlled phase-locked-loop circuit |
JP2003023351A (ja) * | 2001-07-09 | 2003-01-24 | Nec Corp | 非整数分周器、およびフラクショナルn周波数シンセサイザ |
JP4155406B2 (ja) * | 2004-04-01 | 2008-09-24 | ソニー・エリクソン・モバイルコミュニケーションズ株式会社 | デルタシグマ変調型分数分周pll周波数シンセサイザ、及び、無線通信装置 |
-
2002
- 2002-12-26 JP JP2004564432A patent/JP3792706B2/ja not_active Expired - Fee Related
- 2002-12-26 CN CNB028295587A patent/CN100521542C/zh not_active Expired - Fee Related
- 2002-12-26 WO PCT/JP2002/013701 patent/WO2004062107A1/ja active Application Filing
-
2005
- 2005-01-26 US US11/042,136 patent/US7388438B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO2004062107A1 (ja) | 2004-07-22 |
JPWO2004062107A1 (ja) | 2006-05-18 |
US20050153662A1 (en) | 2005-07-14 |
JP3792706B2 (ja) | 2006-07-05 |
US7388438B2 (en) | 2008-06-17 |
CN1669223A (zh) | 2005-09-14 |
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Legal Events
Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081017 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20081017 Address after: Tokyo, Japan, Japan Applicant after: Fujitsu Microelectronics Ltd. Address before: Kawasaki, Kanagawa, Japan Applicant before: Fujitsu Ltd. |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee |
Owner name: FUJITSU SEMICONDUCTOR CO., LTD. Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD. |
|
CP03 | Change of name, title or address |
Address after: Kanagawa Patentee after: Fujitsu Semiconductor Co., Ltd. Address before: Tokyo, Japan Patentee before: Fujitsu Microelectronics Ltd. |
|
ASS | Succession or assignment of patent right |
Owner name: SPANSION LLC N. D. GES D. STAATES Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20140107 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20140107 Address after: American California Patentee after: Spansion LLC N. D. Ges D. Staates Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20160701 Address after: American California Patentee after: Cypress Semiconductor Corp. Address before: California Patentee before: Spansion LLC N. D. Ges D. Staates |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090729 Termination date: 20191226 |
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CF01 | Termination of patent right due to non-payment of annual fee |