CN100521194C - 晶粒的封装结构及其制造方法 - Google Patents

晶粒的封装结构及其制造方法 Download PDF

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CN100521194C
CN100521194C CN 200610082831 CN200610082831A CN100521194C CN 100521194 C CN100521194 C CN 100521194C CN 200610082831 CN200610082831 CN 200610082831 CN 200610082831 A CN200610082831 A CN 200610082831A CN 100521194 C CN100521194 C CN 100521194C
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chip
chipset
projection
substrate
flat
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CN101090107A (zh
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戴惟璋
李政颖
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开了一种芯片的封装结构及其制造方法，本发明的制造方法包括以下步骤：提供平板，平板具有第一表面和第二表面；形成多个第一芯片在平板的第一表面上，第一芯片具有第一表面和第二表面；形成多个第一凸块在第一芯片的第一表面上；及切割平板，以形成多个芯片组，每一个芯片组具有平板单元、第一芯片及多个第一凸块，第一芯片位于平板单元的第一表面上。由此，使单颗芯片能够容易植上凸块。

Description

芯片的封装结构及其制造方法
技术领域
本发明涉及一种芯片的封装方法，特别是一种芯片的封装结构及其制造方法。
背景技术
请参考图1A至图1C，其表示了现有芯片的制造方法示意图。首先，请参考图1A，提供晶圆11，晶圆11中界定多个芯片111(如虚线所示)，晶圆11具有第一表面112。请参考图1B，接着，形成多个凸块12在晶圆11的第一表面112上，其中凸块12的较佳材料为金。请参考图1C，接着，切割晶圆11，以形成多个芯片111。
现有技术的芯片封装方法是在整片晶圆11上形成凸块12，再切割晶圆11为芯片111。若要在单一芯片上植凸块，将会很困难并且耗费大量的时间。因此，现有技术的芯片封装方法将无法满足单一芯片上植凸块的需求。
因此，有必要提供一种创新且具有进步性的芯片封装结构及其制造方法，以解决上述问题。
发明内容
本发明的目的在于提供一种芯片的封装结构及其制造方法，以使单颗芯片容易植上凸块，进而使芯片应用于堆叠式的封装结构中。
为达上述目的，本发明芯片的制造方法，包括以下步骤：(a)提供平板，平板具有第一表面及第二表面；(b)形成多个第一芯片在平板的第一表面上，第一芯片具有第一表面和第二表面；(c)形成多个凸块在第一芯片的第一表面上；及(d)切割平板，以形成多个芯片组，每一个芯片组具有平板单元、第一芯片及多个凸块，第一芯片位于平板单元的第一表面上。
本发明具有芯片组的封装结构，包括芯片组及基板。芯片组包括平板单元、第一芯片及多个凸块。平板单元具有第一表面及第二表面。第一芯片设置在平板单元的第一表面上，第一芯片具有第一表面及第二表面。凸块形成于第一芯片的第一表面上。基板具有第一表面及第二表面，芯片组倒置在基板的第一表面上，以使凸块直接与基板电性连接。
综上所述，采用本发明具有如下的优点：本发明可在单一芯片上形成凸块，进而应用在堆叠式的芯片封装结构中，不须再经过复杂的程序来完成，可大量节省植入凸块的时程。
附图说明
图1A至图1C表示了现有芯片的制造方法的示意图；
图2A至2C表示了本发明芯片上植凸块的方法示意图；
图2D表示了本发明具有芯片组的封装结构示意图；及
图2E表示了本发明具有芯片的堆叠式封装结构示意图。
其中，附图标记说明如下：
11：晶圆                     111：芯片
112：第一表面                12：凸块
2：本发明的芯片组
20：平板                     201：第一表面
202：第二表面                21：芯片
211：第一表面                212：第二表面
22：凸块                     23：平板单元
231：第一表面
3：本发明具有芯片组的封装结构
30：本发明的芯片组           31：芯片
32：凸块                     33：平板单元
34：底胶                     35：基板
351：第一表面
4：本发明具有芯片组的封装结构
40：第一芯片组               41：第一芯片
42：凸块                     43：平板单元
432：第二表面                44：底胶
45：基板                451：第一表面
46：第二芯片            47：导线
48：封胶
具体实施方式
请参考图2A至图2C，其表示了依照本发明的芯片的制造方法的示意图。请参考图2A，首先，提供平板20，平板20具有第一表面201及第二表面202，第二表面202是相对于第一表面201而言，其中在实施例中，第一表面201是线路面，在其他应用上，第二表面202也可以是线路面。接着，形成多个芯片21在平板20的第一表面201上，芯片21具有第一表面211及第二表面212，第二表面212是相对于第一表面211而言，其中芯片21以阵列式排列并利用树脂贴附在平板20的第一表面201上。
请参考图2B，形成多个凸块22在芯片21的第一表面211上，其中凸块22的较佳材料为金。
请参考图2C，切割平板20以形成多个芯片组2，每一个芯片组2包括平板单元23、芯片21及多个凸块22。平板单元23具有第一表面231。芯片21的第二表面212贴附在平板单元23的第一表面231上。凸块23形成在芯片21的第一表面211上。
请参考图2D，其表示了本发明的具有芯片组的封装结构3的示意图。具有芯片组的封装结构3包括基板35、芯片组30及底胶34。基板35具有第一表面351。芯片组30与上述图2C的芯片组2结构相同，芯片组30倒置在基板35的第一表面351上，使凸块32直接与基板35的第一表面351电性连接。底胶34用以使芯片组30与基板35得到良好的结合，并保护凸块32与基板35的结合处。
请参考图2E，其表示了本发明具有单芯片组的堆叠式封装结构4的示意图。具有单芯片组的堆叠式封装结构4包含第一芯片组40、基板45、第二芯片组46及封胶48。第一芯片组40的结构与上述图2D的芯片组3的结构相同。第一芯片组40包括平板单元43、第一芯片41及多个凸块42。第一芯片组40倒置在基板45的第一表面451上，使凸块42直接与基板45的第一表面451电性连接，并利用底胶44使第一芯片组40与基板45得到良好的结合，并保护凸块42与基板45的结合处。
第二芯片46利用底胶贴置在平板单元43的第二表面432上。第二芯片组46通过导线47与基板45的第一表面451电性连接。封胶48用以封装第一芯片组40及第二芯片组46以及导线47，以形成堆叠式封装结构4。
因此，利用本发明的在单芯片上植凸块的方法，可以于单芯片上容易植上凸块，因此，可以改善现有技术不易于单芯片上植凸块的缺点，并大量减少在单芯片上植凸块的时间。
上述实施例仅为说明本发明的原理及其功效，而非用于限制本发明。因此，熟知此技术的人员可在不违背本发明精神的基础上对上述实施例进行修改与变化。本发明的权利保护范围应当以后述的权利要求为准。

Claims (5)

1、一种具有芯片组封装结构的封装方法，其特征在于，包括以下步骤：
提供一平板，该平板具有一第一表面及一第二表面；
形成多个相互分离的第一芯片在该平板的第一表面上，该第一芯片具有一第一表面及一第二表面；
形成多个凸块在该第一芯片的该第一表面上；及
切割该平板，以形成多个芯片组，每一个芯片组具有一平板单元、一第一芯片及多个凸块。
2、根据权利要求1所述的方法，其特征在于，在所述形成多个第一芯片在该平板的第一表面上的步骤中该第一芯片以树脂贴附在该平板上。
3、根据权利要求1所述的方法，其特征在于，该凸块的材料为金。
4、根据权利要求1所述的方法，其特征在于，在所述切割该平板，以形成多个芯片组的步骤之后还包括：
将该芯片组倒置在一基板的一第一表面上，其中该凸块直接与该基板的该第一表面电性连接。
5、根据权利要求4所述的方法，其特征在于，在所述将该芯片组倒置在一基板的一第一表面上的步骤之后还包括：
形成一第二芯片在该平板单元的一第二表面上，该第二芯片与该基板的第一表面电性连接。
CN 200610082831 2006-06-13 2006-06-13 晶粒的封装结构及其制造方法 Active CN100521194C (zh)

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