CN100505163C - 制造应变绝缘体上硅半导体衬底的方法 - Google Patents

制造应变绝缘体上硅半导体衬底的方法 Download PDF

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Publication number
CN100505163C
CN100505163C CNB2004800359038A CN200480035903A CN100505163C CN 100505163 C CN100505163 C CN 100505163C CN B2004800359038 A CNB2004800359038 A CN B2004800359038A CN 200480035903 A CN200480035903 A CN 200480035903A CN 100505163 C CN100505163 C CN 100505163C
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China
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semiconductor layer
crystalline semiconductor
ion
layer
carry out
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Chinese (zh)
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CN1890781A (zh
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斯蒂芬·贝戴尔
盖伊·科恩
陈华杰
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
CNB2004800359038A 2003-12-05 2004-12-01 制造应变绝缘体上硅半导体衬底的方法 Expired - Fee Related CN100505163C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/728,519 2003-12-05
US10/728,519 US6972247B2 (en) 2003-12-05 2003-12-05 Method of fabricating strained Si SOI wafers

Publications (2)

Publication Number Publication Date
CN1890781A CN1890781A (zh) 2007-01-03
CN100505163C true CN100505163C (zh) 2009-06-24

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CNB2004800359038A Expired - Fee Related CN100505163C (zh) 2003-12-05 2004-12-01 制造应变绝缘体上硅半导体衬底的方法

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Country Link
US (1) US6972247B2 (enExample)
EP (1) EP1695377A2 (enExample)
JP (1) JP4939224B2 (enExample)
KR (1) KR100940748B1 (enExample)
CN (1) CN100505163C (enExample)
TW (1) TWI313511B (enExample)
WO (1) WO2005055290A2 (enExample)

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EP3678168B1 (fr) * 2019-01-07 2022-08-31 Commissariat à l'énergie atomique et aux énergies alternatives Procédé de guérison avant transfert d'une couche semi-conductrice

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WO2005112129A1 (ja) * 2004-05-13 2005-11-24 Fujitsu Limited 半導体装置およびその製造方法、半導体基板の製造方法
US7488670B2 (en) * 2005-07-13 2009-02-10 Infineon Technologies Ag Direct channel stress
FR2890489B1 (fr) * 2005-09-08 2008-03-07 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
US8319285B2 (en) 2005-12-22 2012-11-27 Infineon Technologies Ag Silicon-on-insulator chip having multiple crystal orientations
US7560318B2 (en) * 2006-03-13 2009-07-14 Freescale Semiconductor, Inc. Process for forming an electronic device including semiconductor layers having different stresses
CN100431132C (zh) * 2006-03-30 2008-11-05 上海理工大学 一种采用相变方法实现绝缘体上应变硅的制作方法
DE102006030257B4 (de) * 2006-06-30 2010-04-08 Advanced Micro Devices, Inc., Sunnyvale Teststruktur zum Bestimmen der Eigenschaften von Halbleiterlegierungen in SOI-Transistoren mittels Röntgenbeugung
JP4943820B2 (ja) * 2006-11-10 2012-05-30 信越化学工業株式会社 ＧＯＩ（ＧｅｏｎＩｎｓｕｌａｔｏｒ）基板の製造方法
US8227020B1 (en) * 2007-03-29 2012-07-24 Npl Associates, Inc. Dislocation site formation techniques
US8603405B2 (en) 2007-03-29 2013-12-10 Npl Associates, Inc. Power units based on dislocation site techniques
CN101681843B (zh) * 2007-06-20 2012-05-09 株式会社半导体能源研究所 半导体装置的制造方法
KR100868643B1 (ko) * 2007-07-20 2008-11-12 주식회사 동부하이텍 이미지센서 및 그 제조방법
US8329260B2 (en) 2008-03-11 2012-12-11 Varian Semiconductor Equipment Associates, Inc. Cooled cleaving implant
FR2931293B1 (fr) 2008-05-15 2010-09-03 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante
US8138066B2 (en) 2008-10-01 2012-03-20 International Business Machines Corporation Dislocation engineering using a scanned laser
JP2011254051A (ja) * 2010-06-04 2011-12-15 Sumitomo Electric Ind Ltd 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置
US8486776B2 (en) 2010-09-21 2013-07-16 International Business Machines Corporation Strained devices, methods of manufacture and design structures
TW201227828A (en) * 2010-12-31 2012-07-01 Bo-Ying Chen Wafers for nanometer process and manufacturing method thereof
US8809168B2 (en) 2011-02-14 2014-08-19 International Business Machines Corporation Growing compressively strained silicon directly on silicon at low temperatures
GB201114365D0 (en) 2011-08-22 2011-10-05 Univ Surrey Method of manufacture of an optoelectronic device and an optoelectronic device manufactured using the method
FR3003686B1 (fr) * 2013-03-20 2016-11-04 St Microelectronics Crolles 2 Sas Procede de formation d'une couche de silicium contraint
FR3006438B1 (fr) * 2013-06-04 2015-06-26 Commissariat Energie Atomique Capteur de temperature
FR3014244B1 (fr) 2013-11-29 2018-05-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede ameliore de realisation d'un substrat semi-conducteur contraint sur isolant
FR3041146B1 (fr) * 2015-09-11 2018-03-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de mise en tension d'un film semi-conducteur
FR3050569B1 (fr) * 2016-04-26 2018-04-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Fabrication amelioree de silicium contraint en tension sur isolant par amorphisation puis recristallisation
CN116092923B (zh) * 2023-01-16 2025-11-04 湖北九峰山实验室 一种基于碳膜的碳化硅欧姆接触结构及其制备方法

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CN1348210A (zh) * 2000-07-26 2002-05-08 国际商业机器公司 用选择性外延淀积制造应变硅cmos结构的方法

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US6855649B2 (en) * 2001-06-12 2005-02-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US20030077882A1 (en) * 2001-07-26 2003-04-24 Taiwan Semiconductor Manfacturing Company Method of forming strained-silicon wafer for mobility-enhanced MOSFET device
JP2003158250A (ja) * 2001-10-30 2003-05-30 Sharp Corp ＳｉＧｅ／ＳＯＩのＣＭＯＳおよびその製造方法
US6812114B2 (en) * 2002-04-10 2004-11-02 International Business Machines Corporation Patterned SOI by formation and annihilation of buried oxide regions during processing
US6774015B1 (en) * 2002-12-19 2004-08-10 International Business Machines Corporation Strained silicon-on-insulator (SSOI) and method to form the same
US6825102B1 (en) * 2003-09-18 2004-11-30 International Business Machines Corporation Method of improving the quality of defective semiconductor material

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CN1348210A (zh) * 2000-07-26 2002-05-08 国际商业机器公司 用选择性外延淀积制造应变硅cmos结构的方法

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Effect of helium ion implantation and annealing on therelaxation behavior of pseudomorphic Si1-xGex buffer layerson Si (100) substrates. M. Luysberg, D. Kirch, H. Trinkaus.J. Appl. Phys.,Vol.92 No.8. 2002
Effect of helium ion implantation and annealing on therelaxation behavior of pseudomorphic Si1-xGex buffer layerson Si(100)substrates. M.Luysberg,D.Kirch, H.Trinkaus.J. Appl. Phys.,Vol.92 No.8. 2002 *
Preparation of novel SiGe-free strained Si oninsulatorsubstrates. Langdo, T.A., Lochtefeld, A., Currie, M.T.SOI Conference, IEEE International 2002. 2002

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3678168B1 (fr) * 2019-01-07 2022-08-31 Commissariat à l'énergie atomique et aux énergies alternatives Procédé de guérison avant transfert d'une couche semi-conductrice

Also Published As

Publication number Publication date
KR100940748B1 (ko) 2010-02-11
WO2005055290A3 (en) 2005-09-09
TW200529422A (en) 2005-09-01
WO2005055290A2 (en) 2005-06-16
CN1890781A (zh) 2007-01-03
US6972247B2 (en) 2005-12-06
JP2007513511A (ja) 2007-05-24
EP1695377A2 (en) 2006-08-30
JP4939224B2 (ja) 2012-05-23
US20050124146A1 (en) 2005-06-09
TWI313511B (en) 2009-08-11
KR20060123255A (ko) 2006-12-01

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