CN100480420C - Vapor deposition method of low dielectric insulating film, thin film transistor using the same and preparation method thereof - Google Patents

Vapor deposition method of low dielectric insulating film, thin film transistor using the same and preparation method thereof Download PDF

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CN100480420C
CN100480420C CN 03808847 CN03808847A CN100480420C CN 100480420 C CN100480420 C CN 100480420C CN 03808847 CN03808847 CN 03808847 CN 03808847 A CN03808847 A CN 03808847A CN 100480420 C CN100480420 C CN 100480420C
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insulating layer
thin film
chemical formula
film transistor
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CN1646726A (en
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梁成勋
洪完植
郑宽旭
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三星电子株式会社
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Abstract

本发明涉及一种用于汽相淀积低介电绝缘层的方法、利用该绝缘层的薄膜晶体管及其制造方法,更具体地涉及一种可显著地改善汽相淀积速度同时保持低介电绝缘层性能的用于汽相淀积低介电绝缘的方法,从而解决了寄生电容问题以获得高开口率结构,并且当通过CVD法或PECVD法汽相淀积绝缘层以形成用于半导体装置的保护层时,通过使用硅烷气体可以降低工序时间。 The present invention relates to a method for vapor deposition of a low dielectric insulating layer by the insulating layer is a thin film transistor and a manufacturing method, and more particularly, to a significantly improved vapor deposition rate while maintaining a low dielectric a method for the electrically insulating layer properties vapor deposition of low dielectric insulation, thereby solving the problem of the parasitic capacitance to obtain a high aperture ratio structure, and when the insulating layer deposited by a CVD method or a PECVD method to form a semiconductor vapor when the protective layer of the device, the process time can be reduced by using a silane gas. 本发明还涉及一种利用该工序的薄膜晶体管及其制造方法。 The present invention further relates to a thin film transistor and a manufacturing method utilizing the step.

Description

低介电绝缘层的汽相淀积方法、利用该低介电绝缘层的薄膜晶体管及其制造方法 A vapor deposition method of the low dielectric insulating layer, using a thin film transistor and a manufacturing method of the low dielectric insulating layer

技术领域 FIELD

本发明涉及一种用于汽相淀积低介电绝缘层的方法,更具体地涉及一种通过加入硅烷气体(SiH 4 )以CVD法或PECVD法用于形成半导体装置的保护层可显著地提高低介电绝缘层的汽相淀积速度的用于汽相淀积低介电绝缘层的方法。 The present invention relates to a method for vapor deposition of a low dielectric insulating layer, and more particularly, to the protective layer of one (SiH 4) by a CVD method or a PECVD method for forming a semiconductor device by adding the silane gas may be significantly improve the low dielectric insulating layer vapor deposition rate method for vapor deposition of a low dielectric insulating layer.

背景技术 Background technique

薄膜晶体管基片在液晶显示器或有机EL(电致发光)显示器等作为独立驱动每个像素的电路基片使用。 The thin film transistor substrate in a liquid crystal display or an organic EL (Electro Luminescence) display or the like as an independent drive each pixel circuit substrate used. 薄膜晶体管基片上形成传送扫描信号的扫描信号布线或栅极布线和传送图像信号的图像信号线或数据布线,由与栅极布线及数据布线连接的薄膜晶体管、与薄膜晶体管连接的像素电极、遮盖栅极布线的栅极绝缘层及遮盖薄膜晶体管和数据布线的保护层等组成。 Image signal line or the pixel electrode scan signal wiring or the data wiring and the gate wiring transmitting the image signal is formed on the scanning signal transmitting thin film transistor substrate, a thin film transistor connected to the gate wirings and data wirings, connected to the thin film transistor, covering a gate insulating layer covering the gate line and the data wiring and a thin film transistor and other components of the protective layer. 薄膜晶体管由栅极布线一部分的栅极和形成通道的半导体层、数据布线一部分的源极和漏极及栅极绝缘层和保护层组成。 The thin film transistor semiconductor channel layer by the gate portion of the gate wiring and is formed, the data source and the drain wirings and the gate insulating layer and constitute a part of the protective layer. 薄膜晶体管是一种传输或截止通过图像信号的开关装置,根据由栅极布线传输的扫描信号通过数据布线将该图像信号传输到像素电极。 The thin film transistor is a transmission by the switching means is turned off or the image signal, in accordance with the gate wiring by a scan signal transmitted through the data transmission of the image signal line to the pixel electrode.

在液晶显示器中薄膜晶体管基片是最常用的。 In the thin film transistor liquid crystal display is the most common substrate. 随着液晶显示器逐渐大型化、高精细化,应要尽快解决寄生电容增加引起的信号扭曲问题。 With the gradual size liquid crystal display, high definition, the problem should be solved signal distortion caused by parasitic capacitance increases as soon as possible. 而且,为了减少个人计算机的功率消耗和增加TV中液晶显示器的有效视听距离,需要提高亮度,这样势必要增大开口率。 Further, in order to reduce the power consumption of the personal computer and increase the effective viewing distance of the liquid crystal TV display, it is necessary to improve the brightness, which is bound to increase the aperture ratio. 为了增大开口率,有必要使像素电极重叠到数据布线之上,但此时会增加像素电极和数据线之间的寄生电容。 In order to increase the aperture ratio, it is necessary that the pixel electrode overlap the data onto the wiring, but this time may increase the parasitic capacitance between the pixel electrode and the data line.

为了解决寄生电容增加的问题,要充分保证像素电极和数据线之间的垂直间隔。 In order to solve the problem of increased parasitic capacitance, sufficient to ensure that the vertical spacing between the pixel electrode and the data line. 为了确保间隔,传统技术上主要用有机绝缘层形成保护层。 In order to ensure spaces with conventional technology mainly forming a protective layer of an organic insulating layer. 然而,利用有机绝缘层的工序有以下弊端。 However, the following drawbacks step using the organic insulating layer. 首先是,材料费高。 The first is the high cost of materials. 特别是在旋转涂布是会浪费很多,它增加了材料成本。 Especially in the spin coating will waste a lot, it increases the cost of materials. 其次,有机绝缘层缺乏耐热性,所以后续工序受到很多限制。 Next, the organic insulating layer is poor in heat resistance, so that the subsequent step subject to many restrictions. 而且,材料的结块等具有较高的产生杂质颗粒的可能性。 Further, blocking materials, etc. having a high possibility of generating foreign particles. 上部层及下部层的粘合力脆弱。 The upper layer and the lower adhesive strength of the fragile layer. 在保护层上形成像素电极时,蚀刻误差会很大。 When the pixel electrode is formed on the protective layer, an etching error would be great.

通常,将SiO 2及SiN的介电薄膜用于制造多种形态的电气元件上。 Typically, the SiO 2 and SiN dielectric films used for manufacturing electrical components on a variety of forms. 正在进行用于从硅氧烷IC's制造用于平板显示器的光波导向装置的研究。 It is used to study the optical waveguide to a flat panel display apparatus for manufacturing IC's from silicone.

该物质提供所有装置的需求及强电和机械特性。 This material provides a strong demand for electrical and mechanical characteristics and all devices. 最近,提高装置性能的方法是,使导电层更接近或紧贴在一起。 Recently, a method to improve the performance of the device is closer to the conductive layer or close together. 特别是,目前使用的装置,作为携带用,比起常见的AC结合更重视在电池中流动所需的更低的功率消耗。 In particular, devices are currently used as a portable, compared to common AC power combined with a more emphasis on lower desired flow in the battery consumption. 因此,为了减少引起更高功率消耗及更慢启动速度的电容量结合,需要开发一种具有低介电常数的新物质。 Accordingly, in order to reduce power consumption and results in a higher starting speed slower binding capacity, development of a new substance having a low dielectric constant.

为了解决这些问题,除了增设附加的功能器之外,使用以低密度的Si-C结合为主的物质。 To solve these problems, in addition to adding additional functionality is outside the used low-density Si-C based binding substance. 上述物质显示低密度具有低介电常数。 Display density thereof has a low dielectric constant. 这些物质是a-SiCOH或硅碳氧化物,且具有2.7至3.5的低介电常数,所以可以大为提高半导体装置的性能。 These materials are a-SiCOH or silicon oxycarbide, and having a low dielectric constant of 2.7 to 3.5, it is possible to greatly improve the performance of the semiconductor device.

因此,作为TFT-LCD面板的层间绝缘层及保护层,若使用a-SiCOH,a-Si:O:F等CVD方法淀积的低介电率绝缘层,可以降低数据布线和像素电极之间的耦合电容量,可以减少RC时间延迟及串话干扰。 Therefore, TFT-LCD panel interlayer insulating layer and a protective layer, the use of a-SiCOH, a-Si: O: F, etc. The method of CVD deposited low dielectric insulating layer, can reduce the data wiring and the pixel electrodes coupling capacitance between, can reduce the RC time delay and crosstalk. 特别是,为了实现超开口率结构,应该将像素电极重叠数据电极。 In particular, the opening ratio in order to achieve ultra-structure, the pixel electrode overlap should the data electrodes. 然而,传统保护层之一的SiNx保护层,因为负载电容量变得很大,所以很难显示图像。 However, SiNx protective layer of one of the traditional protective layer, since the load capacitance becomes large, it is difficult to display an image. 因此,绝缘保护层的介电常数尽量要低,需要增加保护层的厚度,在垂直方向要充分隔开。 Thus, the dielectric constant of the insulating protective layer is lower as much as possible, necessary to increase the thickness of the protective layer, to be sufficiently spaced apart in a vertical direction. 为此,主要使用上述CVD方法淀积的保护层。 For this purpose, the main protective layer of the CVD deposition method.

在CVD方法淀积的低介电率层间绝缘层a-SiCOH层中根据其用途,为了减少耦合电容量需要数微米的厚度。 Between the low dielectric layer CVD method of depositing an insulating layer a-SiCOH layer depending on its use, the need to reduce coupling capacitance of several microns thickness. 一般半导体工序中的绝缘薄膜只不过是数千微米而已,为了补偿这种增加厚度导致的产量的下降,需要有很快的淀积速度。 A general semiconductor process, an insulating film is only thousands of micrometers only, in order to compensate for this increase in thickness due to decreased production, it requires a fast deposition rate.

通常a-SiCOH薄膜向主源气体SiH(CH 3 ) 3 (下面称为Z3MS TM )添加氧化剂N 2 O或O 2 、及改善均匀性及稳定特性的Ar或He等惰性气体,用PECVD(等离子体增强化学电极)方法淀积而成。 Typically a-SiCOH film to the main source gas SiH (CH 3) 3 (hereinafter referred to Z3MS TM) adding an oxidizing agent N 2 O or O 2, and improving the like Ar or He inert gas uniformity and stability characteristics, with a PECVD (Plasma enhanced chemical electrode) deposited by the method. 众所周知,在上述a-SiCOH薄膜中,若增加源气体(例如,三甲基硅烷)的流量,其淀积速度也变快。 It is well known, in the a-SiCOH films, if the increase in the source gas (e.g., trimethylsilyl) flow rate, which is the deposition speed becomes fast.

然而,在上述方法中,随着增加源气体的流量机械强度变小,产生的薄膜很柔软,极易在后续工序中受到损伤,还存在增加高价的源气体消耗量,随之出现造价增加的问题。 However, in the above method, the mechanical strength with increasing flow of source gases becomes small, the film produced is very soft and vulnerable to damage in the subsequent step, there is also increasing the consumption of expensive gas source, appears increased cost problem. 而且,为了使其具有最低介电常数而改变最佳的CVD淀积工序的全部参数,那么介电常数会很快增加,进而出现更要增加厚度的问题。 Further, in order to have the lowest dielectric constant of all the parameters vary best CVD deposition step, the dielectric constant increases quickly, and thus a problem to increase the thickness more. 如图1所示,随着总源气体流量[Z3MS+N 2 O]的增加,介电常数几乎呈直线增加。 1, the source gas flow rate as the total [Z3MS + N 2 O] is increased, the dielectric constant increases almost linearly.

发明内容 SUMMARY

为了解决现有技术的问题,本发明的目的在于提供一种汽相淀积用于半导体装置的低介电绝缘层的方法,其可以降低加工时间且显著改善汽相淀积速度同时保持低的介电常数及其它物理性能,以解决寄生电容的问题,从而获得高开口率的结构。 In order to solve the problems of the prior art, an object of the present invention is to provide a method of vapor deposition of low dielectric insulating layer for a semiconductor device, which can reduce processing time and significantly improve the vapor deposition rate while maintaining a low dielectric constant and other physical properties, in order to solve the problem of the parasitic capacitance, thereby obtaining a high aperture ratio structure.

本发明另一目的在于提供一种按上述方法淀积的绝缘层作为保护层使用制造的半导体装置及其制造方法。 Another object of the present invention is to provide an insulating layer as described above for depositing a semiconductor device and a manufacturing method manufactured using the protective layer.

为了实现上述目的,本发明提供一种汽相淀积用于半导体装置的低介电绝缘层的方法,包括通过将包括主气相源、硅烷(SiH 4 )、和氧化剂的反应气体混合物提供给包括基片的汽相淀积室用CVD法或PECVD法以汽相淀积a-SiCOH薄膜的工序。 To achieve the above object, the present invention provides a vapor deposition method for a semiconductor device of a low dielectric insulating layer, comprising providing a main gas source by comprising silane (SiH 4), and an oxidizing agent to the reaction gas mixture comprises vapor deposition chamber of the substrate by a CVD method or a PECVD method to a vapor deposition step a-SiCOH film.

本发明还提供了一种半导体装置,该半导体装置包括:在绝缘基片上的第一绝缘层、第二绝缘层、缓冲层、栅极绝缘层、和保护层图案中至少一层,其中第一绝缘层、第二绝缘层、缓冲层、栅极绝缘层、和保护层图案中至少一层是通过加入硅烷(SiH 4 )气体用CVD或PECVD法进行汽相淀积的低介电绝缘层。 The present invention further provides a semiconductor device, the semiconductor device comprising: a first insulating layer on the insulating substrate, a second insulating layer, a buffer layer, a gate insulating layer, and the protective layer is at least one pattern, wherein the first insulating layer, a second insulating layer, a buffer layer, a gate insulating layer, and the protective layer pattern is at least one of (SiH 4) gas for the low dielectric insulating layer of vapor-deposited by the CVD or PECVD process by adding a silane.

本发明还提供了一种半导体装置,该半导体装置包括绝缘基片、第一绝缘层、薄膜晶体管、第二绝缘层、及像素电极,其中第一绝缘层及第二绝缘层中至少一层是通过加入硅烷(SiH 4 )气体用CVD或PECVD法进行汽相淀积的低介电绝缘层。 The present invention further provides a semiconductor device, the semiconductor device includes an insulating substrate, a first insulating layer, a thin film transistor, a second insulating layer, and a pixel electrode, wherein the first insulating layer and the second insulating layer is at least one (SiH 4) gas for the low dielectric insulating layer of vapor-deposited by the CVD or PECVD process by adding a silane.

本发明还提供了一种半导体装置,该半导体装置包括:绝缘基片、数据布线、滤色器、缓冲层、栅极布线、栅极绝缘层、半导体层、及像素布线,其中缓冲层和栅极绝缘层中至少一层是通过加入硅烷(SiH 4 )气体用CVD或PECVD法进行汽相淀积的低介电绝缘层。 The present invention further provides a semiconductor device, the semiconductor device comprising: an insulating substrate, a data wiring, a color filter, a buffer layer, a gate wiring, a gate insulating layer, a semiconductor layer, and a pixel line, wherein the buffer layer and the gate at least one gate insulating layer is (SiH 4) gas for the low dielectric insulating layer of vapor-deposited by the CVD or PECVD process by adding a silane.

本发明还提供了一种薄膜晶体管基片,该薄膜晶体管基片包括:绝缘基片;第一信号线,形成在绝缘基片上;第一绝缘层,形成在第一信号线上;第二信号线,形成在第一绝缘层上且与第一信号线交叉;薄膜晶体管,与第一信号线及第二信号线连接;第二绝缘层,是低介电绝缘层,第二绝缘层形成在薄膜晶体管上且具有用于露出薄膜晶体管的规定电极的第一接触孔;以及第一像素电极,形成在第二绝缘层上且通过第一接触孔与薄膜晶体管的规定电极连接。 The present invention also provides a thin film transistor substrate, the thin film transistor substrate comprising: an insulating substrate; a first signal line formed on an insulating substrate; a first insulating layer formed on a first signal line; and a second signal line formed on the first insulating layer and intersecting the first signal line; a thin film transistor connected to the first signal line and second signal line; and a second insulating layer, a low dielectric insulating layer, a second insulating layer is formed a first thin film transistor and having a contact hole for exposing a predetermined electrode of the thin film transistor; and a first pixel electrode formed on the second electrode connected to a predetermined first insulating layer and a contact hole through the thin film transistor.

第一绝缘层可以包括由低介电绝缘层组成的下部层以及由氮化硅组成的上部层。 The first insulating layer may comprise a lower layer made of a low dielectric insulating layers and an upper layer composed of silicon nitride. 而且,像素电极由反射光的不透明导电物质或透明导电物质组成。 Further, the pixel electrode is formed of a transparent or opaque conductive material conductive substance composed of the reflected light.

本发明还提供了一种薄膜晶体管基片,该薄膜晶体管基片包括:数据布线,包括形成在绝缘基片上的数据线;红、绿、和蓝滤色器,形成在绝缘基片上;缓冲层,是低介电绝缘层,该缓冲层形成在数据布线和滤色器上,且具有用于露出数据布线的规定部分的第一接触孔;栅极布线,在缓冲层上形成且包括与数据线交叉以限定像素的栅极线、及与栅极线连接的栅极;栅极绝缘层,形成在栅极布线上且具有用于至少露出第一接触孔一部分的第二接触孔;半导体层,形成在栅极绝缘层的区域上,栅极绝缘层形成在栅极上;以及像素布线,包括通过第一接触孔及第二接触孔与数据线连接且至少一部分与半导体层连接的源极、在半导体层上与源极相对形成的漏极、及与漏极连接的像素电极。 The present invention also provides a thin film transistor substrate, the thin film transistor substrate comprising: a data wiring includes a data line on an insulating substrate; red, green, and blue color filters formed on the insulating substrate; a buffer layer , a low dielectric insulating layer, the buffer layer is formed on the data wiring and the color filter, and having a first contact hole for exposing a predetermined portion of the data wiring; gate wiring, formed on the buffer layer and comprising a data the gate lines crossing the gate line to define a pixel, and connected to the gate line; a gate insulating layer, forming a second contact hole on the gate wiring and having a first contact hole exposing at least a portion of; the semiconductor layer is formed on a region of the gate insulating layer, a gate insulating layer formed on the gate; and a pixel line, comprising a connection via a first contact hole and the second contact hole and the data line connected to at least a portion of the semiconductor layer, a source , on the semiconductor layer and a drain electrode formed opposite the source and the drain connected to the pixel electrode.

本发明还提供了一种用于液晶显示器的薄膜晶体管基片,其包括:绝缘基片;栅极布线,形成在基片上且包括栅极线、栅极、及栅极衬垫;栅极绝缘层,形成在栅极布线上且具有用于至少露出栅极衬垫的接触孔;半导体层图案,形成在栅极绝缘层上;接触层图案,形成在半导体层图案上;数据布线,形成在接触层图案上,数据布线具有与接触层图案基本相同的形态且包括源极、漏极、数据线、和数据衬垫;保护层图案,形成在数据布线上,保护层具有用于露出栅极衬垫、数据衬垫、及漏极的接触孔,且由低介电绝缘层组成;以及透明电极层图案,与露出的栅极衬垫、数据衬垫、及漏极电连接。 The present invention further provides a thin film transistor substrate for a liquid crystal display, comprising: an insulating substrate; a gate wiring formed on the substrate and including a gate line, a gate, and a gate pad; a gate insulating layer, a contact hole is formed on the gate wiring and having at least for exposing the gate pad; semiconductor layer pattern is formed on the gate insulating layer; contact layer pattern is formed on the semiconductor layer pattern; data wiring, is formed in the patterned on the contact layer, the contact layer data wiring pattern having substantially the same shape and includes a source, a drain, a data line and a data pad; protective layer pattern is formed on the data wiring, a protective layer for exposing the gate having pad, data pad, a contact hole and a drain, and a low dielectric insulating layers; and a transparent electrode layer pattern, and the exposed gate pad, data pad, and electrically connected to the drain.

本发明还提供了一种用于制造薄膜晶体管基片的方法,包括以下工序:在绝缘基片上形成包括栅极线、与栅极线连接的栅极、及与栅极线连接的栅极衬垫的栅极布线;形成栅极绝缘层;形成半导体层;堆垛并对导电物质制作布线图案以形成数据布线,数据布线包括与栅极线交叉的数据线、与数据线连接的数据衬垫、与数据线连接且邻接栅极的源极、及位于在栅极周围的源极的相对侧的漏极;堆垛低介电绝缘层以形成保护层;对保护层和栅极绝缘层一起制作布线图案,以形成分别露出栅极衬垫、数据衬垫、及漏极的接触孔;以及通过接触孔堆垛并对透明导电层制作布线图案以形成分别与栅极衬垫、数据衬垫、及漏极连接的辅助栅极衬垫、辅助数据衬垫、及像素电极。 The present invention further provides a method for manufacturing a thin film transistor substrate, comprising the steps of: forming a gate line, a gate connected to the gate line and a gate pad connected to the gate line on an insulating substrate gate wiring pad; forming a gate insulating layer; forming a semiconductor layer; stacking and patterning a conductive material to form a data wiring, data wiring includes a data line intersecting the gate pad and a data line, the data line connected to , electrode, and the drain side of the source opposite the gate electrode is connected to the surrounding and adjacent gate line and the data source; stacking low dielectric insulating layer to form a protective layer; together with the protective layer and the gate insulating layer patterning is performed to form contact holes are exposed gate pad, data pad, and the drain electrode; and a contact hole through the stack and the transparent conductive layer is patterned to form a gate pad, respectively, the data pad and an auxiliary gate pad connected to the drain, and the auxiliary data pad, and a pixel electrode.

本发明还提供了一种用于制造薄膜晶体管基片的方法,包括以下工序:第一工序,在绝缘基片上形成包含数据线的数据布线;第二工序,在基片上形成红、绿、和蓝滤色器;第三工序,用低介电绝缘层形成覆盖数据布线及滤色器的缓冲层;第四工序,在绝缘层上形成包含栅极线及栅极的栅极布线;第五工序,形成覆盖栅极布线的栅极绝缘层;第六工序,在栅极绝缘层上形成欧姆接触层和半导体层图案的同时在栅极绝缘层和缓冲层形成露出数据线一部分的第一接触孔;第七工序,形成彼此分离且在同一层上形成的源极及漏极,并且在欧姆接触层图案上形成包括与漏极连接的像素电极的像素布线;以及第八工序,除去位于源极和漏极之间欧姆接触层图案的露出部分以将欧姆接触层图案分成两部分。 The present invention further provides a method for manufacturing a thin film transistor substrate, comprising the steps of: a first step of forming a data line comprising a data wiring on an insulating substrate; a second step, the formation of red, green on the substrate, and blue color filter; a third step, a buffer layer covering the data wiring and the color filter by forming a low dielectric insulating layer; and a fourth step of forming a gate line including a gate line and a gate electrode on the insulating layer; fifth step of forming a gate insulating layer covering the gate wiring; while a sixth step, an ohmic contact layer and the semiconductor layer pattern is formed on the gate insulating layer is formed in contact with a first portion of the data line is exposed on the gate insulating layer and the buffer layer aperture; a seventh step, and separated from each other are formed in the source and drain are formed on the same layer, a wiring and a pixel comprising a pixel electrode connected to the drain of the ohmic contact layer pattern; and an eighth step of removing source located patterning the exposed portions of the ohmic contact layer between the drain electrode and to the ohmic contact layer pattern is divided into two portions.

在薄膜晶体管基片上的低介电绝缘层是通过上述汽相淀积方法制造的a-SiCOH薄膜。 Low dielectric insulating layer on the thin film transistor substrate is a-SiCOH film produced by the above vapor deposition method.

附图说明 BRIEF DESCRIPTION

图1图示CVD工序中根据总源气体流量的介电常数(k)的变化; FIG 1 illustrates a CVD process in accordance with the dielectric constant of the total gas flow source (k) changes;

图2图示加入硅烷(SiH 4 )气体后的a-SiCOH薄膜汽相淀积速度的提高效果; 2 illustrates addition of silane (SiH 4) the effect of improving a-SiCOH film vapor deposition rate of the gas;

图3图示加入硅烷(SiH 4 )气体后a-SiCOH薄膜介电常数的变化; FIG 3 illustrates a variation added a-SiCOH dielectric constant film after the silane gas (SiH 4);

图4图示根据加入硅烷(SiH 4 )气体及N 2 O流量的a-SiCOH薄膜淀积速度的变化; Figure 4 illustrates changes in accordance with added silane (SiH 4) gas flow rate of N 2 O and a-SiCOH film deposition rate;

图5图示根据总源气体流量[Z3MS+N 2 O+SiH 4 ]的淀积速度的变化; Figure 5 illustrates the total gas flow source [Z3MS + N 2 O + SiH 4] deposition rate of change;

图6图示根据加入硅烷(SiH 4 )气体及N 2 O流量的a-SiCOH薄膜介电常数的变化; FIG 6 illustrates a change in dielectric constant film according to a-SiCOH was added silane (SiH 4) gas and the flow rate of N 2 O;

图7图示根据本发明第十实施例的用于液晶显示器的薄膜晶体管基片; The thin film transistor substrate for a liquid crystal display of FIG. 7 illustrates a tenth embodiment of the present invention;

图8是沿着图7的II-II线的截面图; 8 is a sectional view taken along II-II of FIG. 7 lines;

图9a、10a、11a及12a是将根据本发明第十实施例制造用于液晶显示器的薄膜晶体管的中间过程按其工序顺序图示的薄膜晶体管基片布局图; FIG. 9a, 10a, 11a and 12a is a layout view of a thin film transistor substrate according to an intermediate process for manufacturing a thin film transistor liquid crystal display according to their order of steps illustrating a tenth embodiment of the present invention in;

图9b是沿着图9a的IIIb-IIIb'线的截面图; Figure 9b is a sectional view taken along line IIIb-IIIb 9a of FIG;

图10b是沿着图10a的IVb-IVb'线的截面图,是图9b的下一工序截面图; 10b is a cross-sectional view IVb-IVb 'of Figure 10a along the line, the next step is a cross-sectional view of Figure 9b;

图11b是沿着图11a的Vb-Vb'线的截面图,是图10b的下一工序截面图; FIG 11b is a cross-sectional view Vb-Vb 'of Figure 11a along the line, the next step is a cross-sectional view of FIG 10b;

图12b是沿着图12a的VIb-VIb'线的截面图,是图12的下一工序截面图; Figure 12b is a sectional view VIb-VIb 'of Figure 12a along the line, the next step is a cross-sectional view of Figure 12;

图13是根据本发明第十一实施例的用于液晶显示器的薄膜晶体管基片的布局图; FIG 13 is a layout view of a thin film transistor substrate for a liquid crystal display according to an eleventh embodiment of the present invention;

图14及图15是分别沿着图13的VII-VII'线及IX-IX'线的截面图; 14 and FIG. 15 is a sectional view along VII-VII 'and Line IX-IX' 13 lines, respectively;

图16a是根据本发明第十一实施例制造的第一工序薄膜晶体管基片布局图; 16a is a thin film transistor substrate of the first step of a layout view of an eleventh embodiment according to the present embodiment manufactured by the invention;

图16b及16c是分别沿着图16a的Xb-Xb'线及Xc-Xc'线的截面图; Figure 16b and 16c are respectively along the Xb-Xb sectional view of FIG. 16a 'and the line Xc-Xc' line;

图17a及图17b是分别沿着图16a的Xb-Xb'线及Xc-Xc'线的截面图,是图16b及图16c下一工序的截面图; FIG. 17a and FIG. 17b respectively of Figure 16a along the Xb-Xb sectional view ', and the line Xc-Xc' line in FIG. 16b and Fig. 16c is a sectional view of a next step;

图18a是图17a及17b下一工序中的薄膜晶体管基片布局图; FIG 18a is a layout view of a thin film transistor substrate of FIG. 17a and 17b in the next step;

图18b及18c是分别沿着图18a的XIIb-XIIb'线及XIIc-XIIc'线的截面图; FIGS. 18b and 18c, respectively, is XIIb-XIIb of Figure 18a cross-sectional view along the 'line and XIIc-XIIc' line;

图19a、20a、21a和图19b、20b、21b是分别沿着图18a的XIIb-XIIb'线及XIIc-XIIc'线的截面图,是图18b及18c的下一工序按工序顺序图示的; FIG. 19a, 20a, 21a and 19b, 20b, 21b 18a is a sectional view taken along the XIIb-XIIb 'and the line XIIc-XIIc' line, respectively, is the next step in FIG. 18b and 18c in the order of steps illustrated ;

图22a及图22b是图21a及图21b下以工序的薄膜晶体管基片的截面图; FIG. 22a and FIG. 22b is a thin film transistor substrate of the step section view FIG. 21a and FIG. 21b;

图23a是图22a及图22b的下一工序的薄膜晶体管基片的布局图; Figure 23a is a thin film transistor substrate of FIG. 22a and FIG layout view of a next step 22b;

图23b及图23c是分别沿着图23a的XVIIb-XVIIb'线及XVIIb-XVIIb'线的截面图; FIGS. 23b and 23c, Figure 23a along the XVIIb-XVIIb 'and the line XVIIb-XVIIb' line cross-sectional view, respectively;

图24是根据本发明第十二实施例的具有滤色器的薄膜晶体管基片的布局图; FIG 24 is a layout view of a thin film transistor substrate having a color filter according to the twelfth embodiment of the present invention;

图25是沿着图2的XIX-XIX'线的薄膜晶体管基片截面图; FIG 25 is a sectional view of a thin film transistor substrate taken along line XIX-XIX 2 of FIG;

图26a是根据本发明第十二实施例的制造薄膜晶体管基片的第一制造工序中基片布局图; A first manufacturing step of the substrate 26a is a layout view of a thin film transistor substrate according to a twelfth embodiment of the present invention;

图26b是沿着图26a的XXb-XXb线的截面图; Figure 26b is a sectional view of the line XXb-XXb in FIG. 26a along;

图27a是图26a下一工序基片布局图; Figure 27a Figure 26a is a layout view of a step subsequent to the substrate;

图27b是沿着图26a的XXb-XXb线的截面图; Figure 27b is a sectional view of the line XXb-XXb in FIG. 26a along;

图28a是图28a下一工序基片布局图; Figure 28a is a next step of FIG. 28a layout view of the substrate;

图28b是沿着图28a的XXIIb-XXIIb'线的截面图; Figure 28b is a sectional view taken along line XXIIb-XXIIb 28a of FIG;

图29是图28b下一工序基片截面图; FIG 29 is a next step of FIG. 28b sectional view of the substrate;

图30a是图29下一工序基片布局图; FIG 29 FIG. 30a is a layout view of a step subsequent to the substrate;

图30b是沿着图30a的XXIVb-XXIVb'线的截面图; Figure 30b is a sectional view taken along XXIVb-XXIVb 30a 'of the line;

图31至图32是在图29和图30b之间进行的制造工序的截面; 31 to 32 are cross-sectional manufacturing process is carried out between 29 and FIG. 30b;

图33a是图30a下一工序基片布局图; Figure 33a Figure 30a is a layout view of a step subsequent to the substrate;

图33b是沿着图33a的XXVIIb-XXVIIb'线的截面图; FIG 33b is a sectional view taken along XXVIIb-XXVIIb 33a 'of the line;

图34是根据本发明第十三实施例的用于液晶显示器的薄膜晶体管基片布局图; FIG 34 is a layout view of a thin film transistor substrate for a liquid crystal display according to a thirteenth embodiment of the present invention;

图35是沿着图34的XXIX-XXIX'线的薄膜晶体管基片截面图; FIG 35 is a sectional view of a thin film transistor substrate taken along XXIX-XXIX 'line 34;

图36a是根据本发明第十三实施例的制造的第一工序薄膜晶体管基片布局图; FIG 36a is a thin film transistor substrate of the first step of producing a layout diagram of the embodiment according to a thirteenth embodiment of the present invention;

图35b是沿着图36a的XXXb-XXXb'线的截面图; FIG 35b is a sectional view taken along XXXb-XXXb 36a 'of the line;

图37a是根据本发明第十三实施例的制造的第二工序薄膜晶体管基片布局图; FIG 37a is a second step of thin film transistor substrate producing a layout diagram of the embodiment according to a thirteenth embodiment of the present invention;

图37b是沿着图37a的XXXIb-XXXIb'线的截面图; FIG 37b is a sectional view taken along XXXIb-XXXIb 37a 'of the line;

图38a是根据本发明第十三实施例制造的第三工序薄膜晶体管基片布局图; A third step of FIG. 38a is a layout view of a thin film transistor substrate according to the thirteenth embodiment manufactured embodiment of the present invention;

图38b是沿着图38a的XXIIb-XXXIIb'线的截面图; FIG 38b is a sectional view taken along XXIIb-XXXIIb 38a 'of the line;

图39a是根据本发明第十三实施例的制造的第四工序薄膜晶体管基片布局图; A fourth step of FIG. 39a is a layout view of a thin film transistor substrate manufactured according to a thirteenth embodiment of the present invention;

图39b是沿着图39a的XXXIIIb-XXXIIIb'线的截面图; FIG 39b is a sectional view taken along XXXIIIb-XXXIIIb 39a 'of the line;

图40a是根据本发明第十三实施例的制造的第五工序薄膜晶体管基片布局图; A fifth step of FIG. 40a is a layout view of a thin film transistor substrate manufactured according to a thirteenth embodiment of the present invention;

图40b是沿着图40a的XXXIVb-XXXIVb'线的截面图; Figure 40b is a sectional view taken along line XXXIVb-XXXIVb 40a of FIG;

图41是根据本发明第十四实施例的用于液晶显示器的薄膜晶体管基片布局图;以及 FIG 41 is a layout view of a thin film transistor substrate for a liquid crystal display according to a fourteenth embodiment of the present invention; and

图42和图43分别是沿着图41的XXXVI-XXXVI'线及XXXVII-XXXVII'线的薄膜晶体管基片截面图。 42 and 43 are respectively a sectional view of a thin film transistor substrate taken along line XXXVI-XXXVI of Figure 41 'and the line XXXVII-XXXVII'.

具体实施方式 Detailed ways

现将本发明进行详细说明。 The invention will now be described in detail.

本发明具有,当形成TFT-LCD等半导体装置的保护层时,通过向源气体添加硅烷气体,在提高淀积速度的同时保留其它物理性质的特征。 The present invention has, when the protective layer is formed TFT-LCD and the like of the semiconductor device, by adding silane gas to the source gas retention features other physical properties while improving the deposition speed.

因此,本发明解决了寄生电容问题,可以获得高开口率结构,且可以缩短工序时间。 Accordingly, the present invention solves the problem of the parasitic capacitance, a high aperture ratio structure, and can shorten the process time.

a-SiCOH薄膜(低介电绝缘层)可通过将包括主气相源、硅烷(SiH 4 )、和氧化剂的反应气体混合物提供给包括基片的汽相淀积室用CVD法或PECVD法获得。 a-SiCOH film (low-dielectric insulating layer) can be obtained by including a main gas source, silane (SiH 4), and the reaction gas mixture supplied to the oxidant vapor deposition chamber comprising a substrate obtained by a CVD method or a PECVD method. 为了改善均匀性及稳定特性可以包括Ar或He等惰性气体。 In order to improve the uniformity and stability characteristics may comprise an inert gas like Ar or He.

优选地,选择在功率密度为0.2至1.5mW/cm 2 、压力为1至10,000Torr、温度为25至300℃状态下向等离子体注入反应气体混合物进行的PECVD(等离子体增强化学汽相淀积)方法淀积。 Preferably, the selection power density of 0.2 to 1.5mW / cm 2, a pressure of 1 to 10,000Torr, PECVD at a temperature of 25 to 300 deg.] C state gas is injected into the reaction mixture of plasma (plasma enhanced chemical vapor deposition ) deposition method. 为了制造介电常数在3.6以下、波长范围为400至800nm、具有95%以上光透射比的a-SiCOH薄膜(低介电绝缘层),在反应过程中调节好硅烷及氧化剂的量是很重要的。 In order to manufacture a dielectric constant of 3.6 or less in the wavelength range of 400 to 800 nm, the light transmittance of 95% or more a-SiCOH film (low-dielectric insulating layer) ratio, a good amount of silane and the oxygen is adjusted during the reaction is important of.

因此,优选地,硅烷(SiH 4 )气体与主源气体具有1∶0.5至1的比率。 Thus, preferably, silane (SiH 4) gas and a gas having a ratio of the primary source is 0.5 to 1. 如果超出上述范围会增加介电常数,则不能得到淀积速度的改善。 If the dielectric constant increases beyond the above range, the deposition speed can not be improved.

优选地,这种低介电绝缘层的介电常数为2至3。 Preferably, the dielectric constant of such low dielectric insulating layer is 2 to 3. 而且,优选地,保护层的厚度为1.5μm或更大,更优选地,保护层厚度为1.5至4.0μm。 Also, preferably, the thickness of the protective layer is 1.5μm or more, more preferably, the protective layer having a thickness of 1.5 to 4.0μm. 优选地,基片选自由液晶显示装置、发光二极管显示装置、及有机发光二极管显示装置组成的组,更优选地,是液晶显示装置。 Preferably, the substrate selected from the group consisting of a liquid crystal display device, light emitting diode display device of the group consisting of the means, and an organic light emitting diode display, and more preferably, a liquid crystal display device.

优选地,主源气体选自由用以下化学式1、化学式2、和化学式3表示的有机硅化合物组成的组中一种或多种: Preferably, the main gas source selected from the group consisting of the following Chemical Formula 1, group, and an organosilicon compound represented by Chemical Formula 3 Formula 2 consisting of one or more of:

[化学式1] [Chemical Formula 1]

SiH x (CH 3 ) 4-x SiH x (CH 3) 4- x

其中,x为整数,即0、1、2、或4; Wherein, x is an integer, i.e. 1, 2, or 4;

[化学式2] [Chemical Formula 2]

Si(OR 1 ) x R 2 4-x Si (OR 1) x R 2 4-x

其中,R 1及R 2独立地或同时是被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基,并且优选地R 1及R 2独立地或同时是甲基、乙基、丙基、或乙烯基,而x为0-4的整数; Wherein, R 1 and R 2 are independently or simultaneously substituted by C1-5 alkyl or alkenyl group substituted or unsubstituted straight or branched C1-10 alkyl or alkenyl group, and preferably R 1 and R 2 simultaneously or independently methyl, ethyl, propyl, or vinyl, and x is an integer from 0 to 4;

[化学式3] [Chemical Formula 3]

环-(SiR 1 R 2 -O) n Ring - (SiR 1 R 2 -O) n

R 1及R 2独立地或同时是被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基,并且优选地R 1及R 2独立地或同时是氢、甲基、乙基、丙基、或乙烯基。 R 1 and R 2 are independently or simultaneously substituted by C1-5 alkyl or alkenyl group substituted or unsubstituted C1-10 alkyl or alkenyl group, linear or branched, and preferably R 1 and R 2 are independently or simultaneously hydrogen, methyl, ethyl, propyl, or vinyl.

氧化剂选自由O 2 、N 2 O、NO、CO 2 、CO、臭氧、及其混合物组成的组。 Oxidizing agent is selected from the group consisting of O 2, N 2 O, NO , CO 2, CO, ozone, and mixtures thereof.

用这种本发明的方法淀积的a-SiCOH薄膜当做半导体装置使用,优选在液晶显示器的制造工序中当做绝缘层使用,覆盖液晶显示装置的半导体层,可以有效保护它。 a-SiCOH film in this manner the present invention deposited as a semiconductor device used as an insulating layer is preferably used in a manufacturing process of a liquid crystal display, the cover layer of the semiconductor crystal display device, it can be effectively protected.

就这样,根据本发明的方法最佳组合每个气体的混合比,淀积低介电绝缘层,由此大为改善淀积速度,无机械性强度及后续工序的损伤就能生产传统SiNx薄膜厚度增加10倍的产品,可以补偿随之引起的生产量的下降,可以降低高价的传统源气体的消耗量引起的高造价。 In this way, the method according to the present invention, the mixing ratio of the best combination of each gas, a low dielectric insulating layer is deposited, thereby greatly improving the deposition rate, without damage and the mechanical strength of the subsequent step can produce conventional film SiNx 10-fold increase in thickness of the product, can be compensated consequent decrease in production can be reduced consumption of high cost conventional source gas caused expensive.

下面,说明本发明的实施例及比较例,但应当理解,下面实施例只是用于说明本发明,它不局限于下面的实施例。 Next, Examples and Comparative Examples of the present invention, it should be understood that the following examples merely illustrate the present invention, it is not limited to the following embodiments.

[实施例1至9] [Example 1-9]

使用电容性连接的平行阳极PECVD反应器,用三甲基硅烷(3MS)、硅烷(SiH 4 )、氮氧化物(N 2 O)及氩(Ar)的反应气体混合物和基片在空白硅片或玻璃上淀积低介电绝缘层。 PECVD reactor is a parallel anode capacitively connected with trimethylsilane (3MS), silane (SiH 4), nitrogen oxide (N 2 O) and argon (Ar) and reactive gas mixture in a blank silicon wafer substrate depositing a low dielectric insulating layer or a glass. 汽相淀积温度为270℃,在表1中表示了实施例PECVD的另外参数-介电常数及生长速度。 The vapor deposition temperature was 270 ℃, showing another embodiment of PECVD parameters in Table 1 - Growth rate and dielectric constant.

测量形成在玻璃基片的绝缘层光透射比,其结果都在400至800nm范围内,且具有95%以上的透射比。 Measuring the insulating layer is formed of a glass substrate the light transmittance, and the results are within the range of 400 to 800nm, and has a transmittance of 95% or more.

表1 Table 1

电功率 Electric power 压力(Torr) Pressure (Torr) 3MS(sccm) 3MS (sccm) N<sub>2</sub>O(sccm) N <sub> 2 </ sub> O (sccm) Ar(sccm) Ar (sccm) SiH<sub>4</sub>(sccm) SiH <sub> 4 </ sub> (sccm) 总流速(sccm) The total flow rate (sccm) 汽相淀积速度(nm.min) A vapor deposition rate (nm.min) K<sub>avg</sub> K <sub> avg </ sub> 实施例1 Example 1 1500 1500 2.5 2.5 375 375 1688 1688 750 750 187.5 187.5 3000 3000 1.006 1.006 3.119 3.119 实施例2 Example 2 1500 1500 2.5 2.5 375 375 2813 2813 1100 1100 187.5 187.5 4475 4475 1.08 1.08 3.375 3.375 实施例3 Example 3 1500 1500 2.5 2.5 375 375 3938 3938 1500 1500 187.5 187.5 6000 6000 1.04 1.04 3.520 3.520 实施例4 Example 4 1500 1500 2.5 2.5 375 375 2250 2250 1000 1000 375 375 4000 4000 1.248 1.248 3.216 3.216 实施例5 Example 5 1500 1500 2.5 2.5 375 375 3750 3750 1500 1500 375 375 6000 6000 1.296 1.296 3.621 3.621 实施例6 Example 6 1500 1500 2.5 2.5 375 375 5250 5250 2000 2000 375 375 8000 8000 1.266 1.266 3.897 3.897 实施例7 Example 7 1500 1500 2.5 2.5 375 375 1125 1125 500 500 0 0 2000 2000 0.506 0.506 3.043 3.043 实施例8 Example 8 1500 1500 2.5 2.5 375 375 1875 1875 800 800 0 0 3050 3050 0.644 0.644 3.121 3.121 实施例9 Example 9 1500 1500 2.5 2.5 375 375 2625 2625 1000 1000 0 0 4000 4000 0.728 0.728 3.173 3.173

如图2中所示,本发明中通过向源气体添加硅烷气体,a-SiCOH的淀积速度约增加了60%。 As shown in Figure 2, the present invention is by adding silane gas to the source gas, a-SiCOH deposition rate increased by about 60%. 这时,假如调节好其它汽相淀积参数,即使增加SiH 4添加量,可以保持一定的介电常数(k)值(图3)。 In this case, if the further regulate the vapor deposition parameters, the increase in the amount of SiH 4 is added, can be maintained constant dielectric constant (k) value (FIG. 3).

图4图示为根据添加SiH 4情况(记号:蓝色钻石)、添加相当于主源气体1/2的SiH 4情况(记号:红色长方形)、添加与源气体一样量的SiH 4情况(记号:绿色三角形)的SiH 4添加及氧化剂的流量分别表示a-SiCOH薄膜汽相淀积速度变化。 Figure 4 illustrates a case where SiH 4 is added according to (symbol: blue diamonds), was added corresponding to the main source gas SiH 4 in the case of 1/2 (symbol: red rectangle), and add the same amount of SiH 4 gas source case (symbol : green triangle) and the flow rate of SiH 4 was added oxidant represent a-SiCOH film vapor deposition rate of change. 垂直轴(y)表示氧化剂的N 2 O气体和含Si气体[Z3MS+SiH 4 ]之间的比率。 The vertical axis (y) represented by the oxidizing agent gas and the N 2 O [Z3MS SiH 4 +] ratio between the Si-containing gas.

如图4所示,淀积速度也与N 2 O的流量有关,未添加SiH 4时,随着氧化剂/源气体(例如,N 2 O/Z3MS)比率的增加淀积速度也跟着增加,但添加SiH 4时,虽然增加氧化剂(例如,N 2 O)的流量,但淀积速度几乎不变。 Shown in Figure 4, the deposition rate and the flow rate of N 2 O is also relevant, 4:00 SiH was not added as an oxidizing agent / gas source (e.g., N 2 O / Z3MS) to increase the deposition rate ratio will also increase, but Add 4:00 of SiH, although the increase in the oxidizer flow (e.g., N 2 O), but the deposition speed is almost constant. 因此,淀积速度的改善效果比起调节氧化剂流量,更依赖于添加SiH 4 Thus, the effect of improving the deposition rate of the oxidizer flow adjustment than more dependent on adding SiH 4.

图5图示在SiH 4的添加量分别不同的情况下,将总流量[源气体+氧化剂+SiH 4 ]分别增加到1.5倍及2倍时的淀积速度的变化量。 Figure 5 illustrates the addition amount of the SiH 4 are different, the total flow [+ oxidant source gas SiH 4 +] are increased when the amount of change of the deposition rate of 1.5-fold and 2-fold. 在图4中,未添加SiH 4时,若将[源气体+氧化剂]的流量增加到1.5倍(2000sccm→3000sccm),那么淀积速度只增加约25%,然而,若用SiH 4替代源气体添加且总流量增加到3000sccm,那么淀积速度几乎增加约100%。 In FIG. 4, SiH 4 is not added, if the [+ oxidizer gas source] to 1.5 times the flow rate (2000sccm → 3000sccm), then increasing the deposition rate of only about 25%, however, if the source gas SiH 4 was replaced with was added and the total flow increases 3000sccm, then the deposition rate of almost about 100%. 而且,添加SiH 4时,随着总流量的变化淀积速度几乎不变化,可以确认添加SiH 4效果更良好。 Furthermore, the addition of SiH 4:00, with changes in the deposition rate hardly changes in total flow, it was confirmed that the effect of adding SiH 4 better.

图6图示根据添加硅烷及N 2 O流量的a-SiCOH薄膜介电常数变化。 Figure 6 illustrates a variation in accordance with a silane flow rate of N 2 O and a-SiCOH dielectric constant film. 它分别显示未添加SiH 4情况,添加相当于基本源气体1/2的SiH 4情况、添加与源气体一样量的SiH 4情况。 It shows the case where SiH 4 is not added, adding substantially equivalent to 1/2 of the SiH 4 source gas, the amount is added as the source gas of SiH 4 cases. 水平轴(x)显示氧化剂N 2 O和(源气体+SiH 4 )气体的比率。 The horizontal axis (x) of the oxidizing agent N 2 O (source gas + SiH 4) gas and a ratio.

如图6所示,氧化剂和含Si的气体比率[N 2 O/(Z3MS+SiH 4 )]为3时,根据添加SiH 4的介电常数变化在实验误差范围内微不足道地显示,但若增加[N 2 O/(Z3MS+SiH 4 )]比率,那么随着添加SiH 4介电常数也一起增加。 6, the ratio of oxidant and gas containing Si [N 2 O / (Z3MS + SiH 4)] 3, the addition of SiH 4 varies depending on the dielectric constant displayed negligible within experimental error, but if increased [N 2 O / (Z3MS + SiH 4)] ratio of SiH 4 is added so as to increase the dielectric constant together. 因此,若将[N 2 O/(Z3MS+SiH 4 )]比率调节到3以内,根据SiH 4的添加,介电常数可以保持低水平的同时可以大为改善淀积速度。 Thus, if [N 2 O / (Z3MS + SiH 4)] was adjusted to a ratio of less than 3, added as SiH 4, while the dielectric constant can be kept low deposition rate can be greatly improved.

[实施例10至14] [Examples 10 to 14]

为了使本领域技术人员能够实施本发明,现参照附图详细说明,将上述低介电绝缘层作为保护层使用的根据本发明适用低电阻布线结构的薄膜晶体管基片及其制造方法。 In order that those skilled in the art to practice the invention, reference is now described in detail with reference to the above-described low dielectric insulating layer as a thin film transistor substrate and a method for producing low-resistance wiring structure according to the present invention is suitable for use in the protective layer.

首先参照图7及图8详细说明,根据本发明第十实施例的用于液晶显示器的薄膜晶体管基片结构。 Referring first to FIG. 7 and FIG. 8 described in detail, the structure of the substrate for a thin film transistor liquid crystal display according to a tenth embodiment of the present invention.

图7是根据本发明第十实施例的用于液晶显示器的薄膜晶体管基片,图8是沿着图7的II-II线的截面图。 FIG 7 is a thin film transistor substrate for the liquid crystal display device of the tenth embodiment of the present invention, FIG 8 is a sectional view taken along line II-II of FIG. 7.

在绝缘基片10上形成由铬或钼合金等组成的第一栅极布线层221、241、261和由铝或银合金等组成的第二栅极布线层222、242、262双层组成的栅极布线。 Forming a first gate wiring layer of chromium or molybdenum alloy composed of 221,241,261 and 222,242,262 bilayer second gate wiring layer of aluminum or silver alloy is formed on the insulating substrate 10 consisting of gate wiring. 栅极布线包括横向延伸的栅极线22、连接在栅极线22末端并接收来自外部的栅极信号,再向栅极线传送的栅极衬垫24及连接在栅极线22的薄膜晶体管的栅极26。 The gate wiring including the gate lines 22 extending transversely, and connected to receive a gate signal from the outside at the end of the gate line 22, again a thin film transistor gate pad 24 and the transfer gate line connected to the gate line 22 the gate 26.

在基片10上由氮化硅类组成的栅极绝缘层30覆盖栅极布线22、24、26。 A gate insulating layer on the substrate 10 made of silicon nitride covering the class consisting of the gate wiring 22, 24, 30.

在栅极24的栅极绝缘层30上形成由非晶硅等半导体组成的岛状半导体层40。 An island-shaped semiconductor layer 40 made of amorphous silicon semiconductor is formed on the gate insulating layer 30 of gate 24. 而且,在半导体层40上分别形成掺杂硅化物或n型杂质的n+氢氧化非晶硅类组成的欧姆接触层54、56。 Further, each forming a doped silicide or n-type impurity semiconductor layer 40 on the n + amorphous silicon hydroxide ohmic contact layers 54, 56 thereof.

在欧姆接触层54、56及栅极绝缘层30上形成由Cr或Mo合金等组成的第一数据布线层621、651、661、681和由Al或Ag合金组成的第二数据布线层622、652、652、682双层组成的数据布线62、65、66、68。 Forming a first wiring layer 621,651,661,681 data and the second data wiring layer 622 made of Al or an Ag alloy composed of Cr or Mo alloy is formed on the ohmic contact layer and the gate insulating layer 54, 56, 30, data wirings 652,652,682 bilayers 62,65,66,68. 数据布线62、65、66、68包括横向形成与栅极线22交叉限定像素的数据线62、数据线62的分支且延长到欧姆接触层54上部的源极65、连接在数据线62一末端并接收来自外部图像信号的数据衬垫68、与源极65分离且以栅极26为准形成在源极65对面欧姆接触层56上部的漏极66。 22 includes a data wiring 62,65,66,68 defining pixels formed transversely intersecting the gate line 62 data lines, the data lines and the branches extend to the upper portion of the source electrode 54 ohmic contact layer 6562 is connected to an end of the data line 62 and receive data from an external image signal pad 68, the source electrode 65 and the gate 26 are separated and the drain 66 is formed in an upper portion of whichever of the ohmic contact layer 56 opposite the source 65.

数据布线62、65、66、68及未被它们遮盖的半导体层40上部形成保护层70。 Data wiring protective layer 70 thereof are not covered 62,65,66,68 and 40 forming the upper semiconductor layer. 在这里,保护层70由所述方法淀积的a-SiCOH层(低介电绝缘层)组成,其介电常数为2.0-3.0,为低介电。 Here, the protective layer 70 a-SiCOH layer (low dielectric insulating layer) deposited by said method, whose dielectric constant is from 2.0 to 3.0, a low dielectric. 因此,虽然厚度薄也不会发生寄生电容问题。 Thus, although thickness is not a parasitic capacitance problems. 此外,与其它层的粘合性及步进覆盖性良好。 Further, the adhesion with other layers and good step coverage. 而且,因为是无机绝缘层,所以耐热性比有机绝缘层好。 Moreover, because the inorganic insulating layer, so that heat resistance than the organic insulating layer. 总之,用上述PECVD方法淀积的a-SiCOH层(低介电绝缘层)无论是淀积速度还是蚀刻速度都比氮化硅层快4-10倍,所以也非常有利于工序时间方面。 In summary, by the above deposition method PECVD a-SiCOH layer (low dielectric insulating layer) either deposition rate or etching rate of 4-10 times faster than the silicon nitride layer, it is also very beneficial aspect of the process time.

在保护层70上形成分别露出漏极66及数据衬垫68的接触孔76、78,并与栅极绝缘层30一起形成露出栅极衬垫的接触孔74。 Forming contact holes 76 and 78 are exposed drain electrode 66 and the data pad 68 on the protective layer 70, and the gate pad contact hole 74 is formed together with the gate insulating layer 30 is exposed. 这时,露出衬垫24、68的接触孔74、78可以具有角的或圆形等多种形态,其面积不超过2mm×60μm,优选为0.5mm×15μm。 At this time, a contact hole exposing the pads 74, 78, 24,68 may have various shapes and the like or rounded corners, the area is not more than 2mm × 60μm, preferably 0.5mm × 15μm.

保护层70上形成通过接触孔76与漏极66电连接并且位于像素的像素电极82。 The protective layer 70 is formed on the connection and the pixel electrode of the pixel 82 through the contact hole 76 with the drain electrode 66. 还有,在保护层70上形成通过接触孔74、78分别与栅极衬垫24及数据衬垫68连接的辅助栅极衬垫86及辅助数据衬垫88。 There, an auxiliary gate pad 86 and the auxiliary data pad 74, 78, 88 are respectively connected to the gate pad and the data pad 24 through the contact hole 68 on the protective layer 70. 在这里,像素电极82和辅助栅极及数据衬垫86、88由ITO(氧化铟锡)或IZO(氧化铟锌)组成。 Here, the pixel electrode 82 and the auxiliary data pad 86, and a gate made of ITO (indium tin oxide) or IZO (indium zinc oxide) composition.

如图7及图8所示,像素电极82与栅极线22重叠以形成电容器。 7 and 8, the pixel electrode 82 overlaps the gate line 22 to form a capacitor. 当存储电容不足时,在栅极布线22、24、26相同层可以追加存储电容(sustain capacity)布线。 If memory capacitor, the gate wiring in the same layer as the storage capacitor 22, 24 may be added (sustain capacity) wiring.

此外,像素电极82与数据线62也重叠形成,使开口率变得最大。 Further, the pixel electrode 82 and data line 62 is also formed to overlap, the aperture ratio becomes maximum. 就这样,为了使开口率变得最大,即使将像素电极82与数据线62重叠形成,但因保护层70的介电常数低,所以形成在其间的小寄生电容根本不成问题。 In this way, in order to make the opening ratio becomes maximum, even if the pixel electrode 82 is formed to overlap the data line 62, but the protective layer 70 of low dielectric constant, the parasitic capacitance formed therebetween is small is not a problem.

参照图7及图8和图9a至12a,说明根据本发明第十实施例的用于液晶显示器的薄膜晶体管基片的制造方法。 Referring to FIGS. 7 and 8 and 9a to 12a, illustrate the method of manufacturing a thin film transistor substrate for a liquid crystal display, a tenth embodiment of the present invention.

首先,如图9a及9b所示,通过在基片10上汽相淀积物理、化学特性良好的Cr或Mo合金,堆垛第一栅极布线层221、241、261,再通过淀积低电阻AL或Ag或包括它们的合金等,堆垛第二栅极布线层222、242、262,然后制作布线图案形成包括栅极线22、栅极26及栅极衬垫24的横向延伸的栅极布线。 First, as shown in Figures 9a and 9b, the substrate 10 by physical vapor phase deposition, good chemical properties of Cr or Mo alloy, stacking a first gate wiring layers 221,241,261, and then by depositing the low-resistance AL or Ag, or an alloy thereof comprising, stacking a second gate wiring layers 222,242,262, and then patterning form 22, 26 and the gate of the gate pad 24 comprises laterally extending gate lines wiring.

当用Mo合金形成第一栅极布线层221、241、261,用Ag合金形成第二栅极布线层222、242、262时,其两层都通过Ag合金蚀刻剂的磷酸、硝酸、醋酸、及去离子水混合物蚀刻。 When the first gate wiring layer is formed with 221,241,261 Mo alloy, forming a second gate wiring layers 222,242,262 Ag alloy, the layers through which an Ag alloy etchant of phosphoric acid, nitric acid, acetic acid, etching and deionized water mixture. 因此,用一次蚀刻工序可以形成双层的栅极布线22、24、26。 Thus, the etching step may be formed with a double layer gate wiring 22, 24. 而且,对磷酸、硝酸、醋酸、及去离子水混合物的Ag合金和Mo合金的蚀刻比,对Ag合金的蚀刻比更大,所以栅极布线可以形成锥形结构。 Further, the etching ratio of Ag alloy and Mo alloy phosphoric acid, nitric acid, acetic acid, and deionized water mixture, the etching is greater than an Ag alloy, the gate wirings may be formed in a tapered configuration.

然后,如图10a及图10b所示,连续堆垛(叠层)由氮化硅组成的栅极绝缘层30、由非晶硅组成的半导体层40、掺杂的非晶硅层50组成的三层膜,光学蚀刻半导体层40和掺杂的非晶硅层50,在栅极24上的栅极绝缘层30上形成半导体层40和欧姆接触层50。 Then, as shown in FIGS. 10a and 10b, the continuous stack (stack) a gate insulating layer 30 composed of silicon nitride, a semiconductor layer 40 composed of amorphous silicon, doped amorphous silicon layer 50 is composed of three-layer film, the optical etching the semiconductor layer 40 and the doped amorphous silicon layer 50, semiconductor layer 40 and the ohmic contact layer 50 is formed on the gate insulating layer 30 on the gate 24.

然后,如图11a至图11b所示,淀积Cr或Mo合金等堆垛(叠层)第一数据布线层651、661、681,淀积Al或Ag合金等,堆垛第二数据布线层652、662、682后,通过光学蚀刻形成包括与栅极线22交叉的数据线62、与数据线62连接并延长到栅极26上部的源极65、一末端连接数据线62的数据衬垫68及与源极64分离且以栅极26为准与源极65面对的漏极66的数据布线。 Then, as shown in Figure 11a to Figure 11b, Cr or Mo alloy is deposited stack (stack) a first data wiring layer 651,661,681, Al or Ag alloy is deposited, a second data wiring layer stack after 652,662,682, comprising forming 62, 62 connected to the data line crossing the gate line 22 and data lines 26 extend to the upper portion of the gate source 65, a data pad connected to the end of the data line 62 by an optical etching 68 and 64 separated from the source and the gate electrode 65 and the source 26 subject to data wiring facing the drain 66.

接着,蚀刻未被数据布线62、65、66、68遮挡的掺杂的非晶硅层图案50,以栅极26为中心向两侧分离,同时露出两侧掺杂的非晶硅层55、56之间的半导体层图案40。 Next, etching is not blocked data wiring 62,65,66,68 doped amorphous silicon layer pattern 50, the gate 26 is separated from the center to both sides, while exposing both sides of the doped amorphous silicon layer 55, between the semiconductor layer pattern 5640. 接着,为了稳定露出的半导体层40表面优选进行氧等离子处理。 Next, in order to stabilize the exposed surface 40 of the semiconductor layer is preferably subjected to oxygen plasma treatment.

然后,如图12a及12b所示,用CVD或PECVD方法制造a-SiCOH层(低介电CVD层)形成保护层70。 Then, as shown in Figures 12a and 12b, for producing a-SiCOH layer (a low dielectric CVD layer) by the CVD or PECVD method, the protective layer 70 is formed. 这时,形成上述保护层的工序是将气体状态的上述化学式1至3的化合物中至少一个作为主源使用,添加与上述氧化剂和Ar或He等气体一起混合SiH 4的反应气体混合物,用CVD或PECVD方法淀积的工序。 In this case, the step of forming the protective layer is a compound of the above Chemical Formulas 1 to 3 in gaseous state at least one as a main source used, was added and mixed reaction gas mixture SiH 4 together with the above and other oxidant and Ar or He gas, by CVD the method or PECVD deposition process. 这时,更优选地,作为上述主源使用SiH(CH 3 ) 3 、SiO 2 (CH 3 ) 4 、(SiH) 4 O 4 (CH 3 ) 4及Si(C 2 H 5 O) 4中至少一个,氧化剂使用N 2 O或O 2 In this case, more preferably, SiH (CH 3) 3, SiO 2 (CH 3) 4, (SiH) as the main source 4 O 4 (CH 3) 4 and Si (C 2 H 5 O) 4 at least one oxidizing agent or N 2 O O 2.

接着,用光学蚀刻工序与栅极绝缘层30一起对保护层70制作布线图案,形成露出栅极衬垫24、漏极66及数据衬垫68的接触孔74、76、78。 Subsequently, an etching step and an optical layer 30 with the gate insulating protective layer 70 is patterned, 24, the drain contact hole 66 and the data pad 68 exposed gate pad 76, 78 is formed. 在这里,接触孔74、76、78可以具有角状或圆形,露出衬垫24、68的接触孔74、78的面积不超过2mm×60μm,优选在0.5mm×15μm以上。 Here, the contact holes 76, 78 may have an angular or circular, the exposed area of ​​the contact pads 24,68 of the holes 74,78 is not more than 2mm × 60μm, preferably at least 0.5mm × 15μm.

接着,最后如图7及8所示,淀积ITO或IZO层并进行光学蚀刻,形成通过第一接触孔与漏极66连接的像素电极82和通过第二及第三接触孔74、78分别与栅极衬垫24及数据衬垫68连接的辅助栅极衬垫86及辅助数据衬垫88。 Next, 7 and 8 Finally, ITO or IZO layer is deposited and etched optics, forming a pixel electrode connected to the drain electrode through the first contact hole 6682 and the second and the third contact holes 74 and 78 respectively an auxiliary gate pad 86 and the auxiliary data pad 24 connected to the gate pad and a data pad 68 to 88. 在叠层ITO或IZO之前的预热工序中使用的气体是优选利用氮气。 Gas used in the preheating step before the lamination of ITO or IZO is preferable to use nitrogen. 这是为了防止,在通过接触孔74、76、78露出的金属层24、66、68上形成金属氧化层。 This is to prevent the metal oxide layer is formed through a contact hole 76, 78 on the exposed metal layers 24,66,68.

如上所述,将本发明方法淀积的低介电绝缘层使用为保护层70,从而解决了寄生电容问题,开口率也可以变得最大。 As described above, the present invention is a method of depositing a low dielectric insulating layer is formed using a protective layer 70, thereby solving the problem of the parasitic capacitance, the opening ratio can be maximized. 而且,淀积及蚀刻速度变快,可以缩短工序时间。 Further, the deposition and the etching speed is increased, process time can be shortened.

如上所述,这种方法可以适用在用5枚掩模的制造方法中,同样也可以适用在用4枚掩模的用于液晶显示器的薄膜晶体管基片的制造方法中。 As described above, this method can be applied in the method of manufacturing the mask 5, the same may also be applied in the method of manufacturing a thin film transistor substrate 4 with a mask for a liquid crystal display. 对此将参照附图详细说明。 As will be described in detail with reference to the accompanying drawings.

首先,参照图13至图15详细说明根据本发明实施例的用4枚掩模完成用于液晶显示器的薄膜晶体管基片的单位像素结构。 First, referring to FIGS. 13 to 15 described in detail to complete the structure of the unit pixel thin film transistor substrate for the liquid crystal display according to the present embodiment of the invention using four masks.

图13是根据本发明第十一实施例的用于液晶显示器的薄膜晶体管基片的布局图,图14及图15是分别沿着图13的VII-VII'线及IX-IX'线的截面图。 FIG 13 is a layout view of a thin film transistor substrate for the liquid crystal display device of the eleventh embodiment of the present invention, FIG. 14 and FIG. 15 is a section taken along respective lines VII-VII 13 'of line and IX-IX' Fig.

首先如第十实施例相同,在绝缘基片10上形成由铬或钼合金等组成的第一栅极布线层221、241、261和由铝或银合金等组成的第二栅极布线层222、242、262的双层组成的栅极布线。 First, as same as the tenth embodiment, a first gate wiring layer is formed of chromium or molybdenum alloy composed of 221,241,261 and a second gate wiring layer 222 made of aluminum or silver alloy is formed on the insulating substrate 10 , the gate wiring 242, 262 of the bilayer composition. 栅极布线包括栅极线22、栅极衬垫24及栅极26。 The gate wiring including the gate line 22, gate pad 24 and the gate 26.

在基片10上与栅极线22平行形成存储(maintenance)电极线28。 Forming a storage (Maintenance) parallel to the gate electrode line 28 and the line 22 on the substrate 10. 存储电极线28也由第一栅极布线层281和第二栅极布线层282的双层组成。 Storage electrode line 28 is also composed of a double layer of the first gate wiring layer 281 and the second gate wiring layer 282. 存储电极线28与连接于将要后述的像素电极82的存储电容器导电体图案68重叠形成提高像素电荷保持能力的存储电容器,但将要上述的像素电极82和栅极线22重叠所引起的存储电容充足时可以不形成。 Storage electrode line 28 connected to the pixel electrode to be described later, the storage capacitor conductor 82 of the pattern 68 formed by superimposing improved pixel charge retention storage capacitor capacity, it will be above the pixel electrode 82 and the storage capacitance of the gate line 22 overlaps caused by forming may not be sufficient. 一般在存储电极线28上施加与上部基片共同电极相同的电压。 Usually applied to the upper substrate and the common electrode voltage in the same storage electrode line 28.

在栅极布线22、24、26及存储电极线28上形成由氮化硅类组成的栅极绝缘层30,以此覆盖栅极布线。 Forming a gate insulating layer 30 composed of silicon nitride based on the gate wiring lines 22, 24 and the storage electrode 28, thus covering the gate wiring.

栅极绝缘层30上形成由氢化非晶硅类半导体组成的半导体图案42、48,在半导体图案42、48上形成由掺杂诸如磷这样的n型杂质重掺杂的非晶硅类组成的欧姆接触层图案或中间层55、56、58。 Forming a semiconductor pattern composed of hydrogenated amorphous silicon-based semiconductor on the gate insulating layer 42, 48 30, 42, 48 are formed on the semiconductor pattern, such as a phosphorus doped n-type impurity such as heavily doped amorphous silicon composition the ohmic contact layer pattern or the intermediate layer 55,56,58.

在欧姆接触层图案55、56、58上形成由Cr或Mo合金组成的第一数据布线层621、641、651、661、681和由Al或Ag合金等组成的第二数据布线层622、642、652、662、682的双层组成的数据布线62、64、65、66、68。 Forming a first wiring layer 621,641,651,661,681 data and the second data wiring layer 622, 642 made of Al or Ag alloy consisting of Cr or Mo alloy is formed on the ohmic contact layer pattern 55,56,58 , double data composed of a wiring 62,64,65,66,68 652,662,682. 数据布线包括纵向形成的数据线62、连接在数据线62一末端接收来自外部像素信号的数据衬垫68、由数据线62分支的薄膜晶体管源极65组成的数据线部62、68、65,还包括与数据线部62、68、65分离且对于栅极26或薄膜晶体管的通道部C为准位于源极65对面的薄膜晶体管漏极66和位于存储电极线28上的存储电容器的导电体图案64。 The data wiring includes a data line 62 formed in the longitudinal direction, the pad 68 is connected to receive data from outside the pixel signal at the end of a data line 62, data line unit 62 by the data lines 62,68,65 branch source of the thin film transistor 65 consisting of, 62,68,65 separation unit further includes a data line and a gate electrode 26 to the channel portion C of the thin film transistor or thin film transistor is the drain on the source subject 66 opposite electrode 65 located on the storage capacitor storage electrode line 28 conductor pattern 64.

数据布线62、64、65、66、68如同第十实施例,可以由Al或Ag的单一层组成。 62,64,65,66,68 data wiring as the tenth embodiment, may consist of a single layer of Al or Ag.

接触层图案55、56、58起到降低其下部半导体图案42、48和其上部数据布线62、64、65、66、68接触电阻的作用,并且与数据布线62、64、65、66、68完全相同的形态。 A pattern 55,56,58 contact layer serves to reduce its lower and its upper semiconductor pattern data wiring 42, 48, 62,64,65,66,68 contact resistance, and with the data wiring 62,64,65,66,68 exactly the same form. 即,数据线部中间层图案55与数据线部62、68、65相同,漏极中间层图案56与漏极66相同,存储电容器中间层图案58与存储电容器导电体图案64相同。 That is, the same as the data line portion of the intermediate layer 55 and the data line pattern portion 62,68,65, the same intermediate layer pattern of the drain 56 and the drain 66, the same intermediate layer pattern of the storage capacitor 58 and the storage capacitor conductor pattern 64.

另外,半导体图案42、48除了薄膜晶体管通道部C之外与数据布线62、64、65、66、68及欧姆接触层图案55、56、58具有相同形态。 Further, the semiconductor pattern the thin film transistors 42 and 48 in addition to the channel portion C and 62,64,65,66,68 data wiring patterns 55,56,58 and the ohmic contact layer have the same shape. 具体而言,存储电容器半导体图案48和存储电容器导电体图案64及存储电容器接触层图案58具有相同形态,但薄膜晶体管的半导体图案42与数据布线及接触层图案剩余部分稍微不同。 Specifically, the semiconductor pattern storage capacitor 48 and the storage capacitor conductor pattern 64 and the storage capacitor contact layer pattern 58 having the same shape, but the thin film transistor semiconductor pattern 42 and the remaining portion of the data wiring and the contact layer pattern is slightly different. 即,在薄膜晶体管通道部C数据线部62、68、65,特别是源极65和漏极66相互分离,数据线部中间层55和漏极接触层图案55相互分离,但薄膜晶体管半导体图案42在这里并没有中断而连续产生薄膜晶体管的通道。 That is, the channel portion of the thin film transistor section C data line 62,68,65, in particular the source 65 and drain 66 are separated, the data line portion of the intermediate layer 55 and the drain electrode contact layer pattern 55 separated from each other, but the thin film transistor semiconductor pattern 42 and here continuously without interruption generating channel thin film transistor.

在数据布线62、64、65、66、68上形成由用上述方式淀积的a-SiCOH层(低介电绝缘层)组成的保护层70。 The protective layer 70 is formed of a-SiCOH layer (a low dielectric insulating layer) was deposited as described above is formed on the data wiring 62,64,65,66,68. 因此,虽然厚度薄也不会发生寄生电容的问题。 Therefore, the problem does not occur although the thickness of the parasitic capacitance. 而且与其它层的接触性及步进覆盖性良好。 And contact with other layers and good step coverage. 而且,是无机绝缘层,所以耐热性比有机绝缘层优秀。 Further, an inorganic insulating layer, so that excellent heat resistance than the organic insulating layer. 此时上述低介电绝缘层介电常数在2-3之间。 At this time, the low dielectric insulating layer between the dielectric constant of 2-3.

保护层70具有露出漏极66、数据衬垫68、及存储电容器导电体图案64的接触孔76、78、72,而且与栅极绝缘层30一起具有露出栅极图案24的接触孔74。 The protective layer 70 having a drain 66 is exposed, the data pad contact hole 68, and the storage capacitor conductor pattern (64) 76,78,72, and together with the gate insulating layer having a contact hole exposing the gate pattern 24 7430.

在保护层70上形成从薄膜晶体管接收像素信号且与上部基片的电极一起产生电场的像素电极82。 It is formed on the protective layer 70 and generates an electric field with the pixel electrode of the upper substrate together with the pixel signal received from the thin film transistor 82. 像素电极82由ITO或IZO类透明导电物质组成,并且通过接触孔76与漏极66物理-电连接、接收像素信号。 The pixel electrode 82 of ITO or IZO composition based transparent conductive substance, and by 66 in physical contact with the drain hole 76 - is electrically connected to receive the pixel signal. 像素电极82与相邻的栅极线22及数据线62重叠提高开口率,但也可以不重叠。 The pixel electrode 82 and the adjacent gate lines 22 and the data line 62 overlap increase the aperture ratio, but may not overlap. 而且像素电极82通过接触孔72也可以与存储电容器导电体图案64连接,向导电体图案64传送像素信号。 The pixel electrode 82 and 72 may be a storage capacitor 64 connected to the conductor pattern via the contact hole 64 transmits the signals to the pixel electrode pattern. 另外,栅极衬垫24及数据衬垫68上通过接触孔74、78形成分别与它们连接的辅助栅极衬垫86及辅助数据衬垫88,它们起到增加衬垫24、68和外部电路装置的接触性并保护衬垫的作用,但并非必需,使用与否具有选择性。 Further, through the contact hole on the gate pad 24 and 74, 78 form an auxiliary data pad 68 are respectively connected to the gate pad 86 and their auxiliary data pad 88, which serves to increase the external circuit pads 24,68 the contact pad and the protective effect of the device, but not necessarily, used or not selective.

参照图13至图15和图16a至图23c,详细说明用4枚掩模制造具有图13至图15结构的用于液晶显示器的薄膜晶体管基片。 Referring to FIGS. 13 to 15 and 16a to 23c, detail a substrate having a thin film transistor structure of FIG. 13 to FIG. 15 for a liquid crystal display with four mask fabrication.

首先,如图16a至16c所示,如同第十实施例汽相淀积物理化学特性良好的Cr或Mo合金等叠层(堆垛)第一栅极布线层221、241、261、181,汽相淀积低电阻Al或Ag合金等叠层(堆垛)第二栅极布线层222、242、262、282,然后,光学蚀刻形成包括栅极线22、栅极衬垫24、栅极26的栅极布线和存储电极线28。 First, as shown in FIG. 16a to 16c, as in the tenth embodiment of the vapor deposition good physicochemical properties Cr or Mo alloy laminate (stack) a first gate wiring layers 221,241,261,181, steam a second gate wiring layer deposited low resistivity Al or Ag alloy laminate (stack) 222,242,262,282, and then, the optical etching comprises a gate line 22, gate pad 24, a gate 26 is formed the gate wiring lines 28 and the storage electrode.

然后,如图17a及17b所示,用化学汽相淀积法分别以 Then, as shown by a chemical vapor deposition 17a and 17b, respectively, in FIG. 厚度连续汽相淀积栅极绝缘层30、半导体层40、中间层50,接着,用溅射等方法汽相淀积由Cr或Mo合金等组成的第一导电层601和由Al或Ag合金等组成的第二导电层602组成导电层60之后,在其上以1-2μm厚度涂布感光层110。 The thickness of the continuous vapor-deposited gate insulating layer 30, semiconductor layer 40, intermediate layer 50, then a method such as sputtering vapor deposition of a Cr or Mo alloy is composed of the first conductive layer 601 made of Al or an Ag alloy, and after the second conductive layer and the like composed of the conductive layer 60 consisting of 602, 110 on which the photosensitive layer was coated to a thickness of 1-2μm.

然后,通过掩模向感光层110照射光之后并显像,如同图18b及18c形成感光层图案112、114。 Then, through a mask and then developing the photosensitive layer is irradiated with light 110, as in FIG. 18b and 18c photosensitive layer pattern 112 is formed. 这时,使感光层图案112、114中位于薄膜晶体管的通道部C,即位于源极65和漏极66之间的第一部分114比数据布线部A,即比位于将要形成数据布线62、64、65、66、68的第二部分112厚度薄,去除其它部分B的所有感光层。 In this case, the photosensitive layer pattern 112, 114 located in the channel portion C of the thin film transistors, i.e. a first portion 114 located between the source electrode 65 and drain electrode 66 than the data wiring portion A, i.e., more than 62, 64 to be formed is located in the data wiring , 65,66,68 second portion 112 of the thin, photosensitive layers to remove all other parts of B. 使残留在通道部C的感光层114的厚度和残留在数据布线A的感光层112的厚度比根据蚀刻工序的工艺条件(以下进行描述)不同,优选地,使第一部分114的厚度在第二部分112厚度的1/2以下,例如, The residue remaining in the channel portion and the thickness C of the photosensitive layer thickness of the photosensitive layer 114 in the data wiring 112. A different process conditions than the etching step (described hereinafter), it is preferable that the thickness of the first portion 114 of the second 1/2 or less the thickness of the portion 112, e.g., 以下。 the following.

根据位置使感光层具有不同厚度的方法有多种,为了调节A区域的光透射比主要形成狭缝或直角形图案或使用半透明层。 There are many depending on the position of the photosensitive layers having different thicknesses of the method, in order to adjust the light transmittance of the region A is mainly formed slits or right angle-shaped pattern or a semitransparent layer.

优选地,位于狭缝图案的线幅宽或图案之间的间距,即狭缝的宽度比曝光时使用的曝光机的分解力(分辨率)小。 Decomposition force is preferably, located in the spacing between the slit pattern line width or pattern, i.e., an exposure machine using a slit width than the exposure (resolution) is small. 当利用半透明层时,制造掩模时为了调节透射比,可以利用具有不同透射比的薄膜或厚度不同的薄膜。 When utilizing a semi-transparent layer, the production of the mask in order to adjust the transmission ratio, may be utilized having different transmittance of film or a different thickness of the film.

通过这种掩模向感光层照射光,在直接暴露在光下的部分则完全分解聚合物。 Irradiating light to the photosensitive layer directly exposed to light of the partial polymer is completely decomposed by such a mask. 在狭缝或形成半透明的部分因光照射量少,故聚合物处在不完全分解的状态。 A slit formed in part translucent or less by light irradiation, so that the polymer is in a state of incomplete decomposition. 在被遮光层遮挡的部分聚合物几乎不分解。 Almost no decomposition portion of the polymer is blocked by a light shielding layer. 接着,对感光层显像,只剩下聚合物未分解的部分。 Next, the photosensitive imaging layer, portions of the polymer left undecomposed. 光照射少的中央部分剩下比完全未照射光的部分厚度薄的感光层。 A small central portion of the remaining light is irradiated photosensitive layer thickness than the portion not irradiated with light completely. 这时,若延长曝光时间,所有分子将会分解,所以应防止出现这种现象。 At this time, if longer exposure time, all the molecules will break down, it should prevent this phenomenon.

这种薄厚度的感光层114利用可以回流物质组成的感光层,并且用完全透射光部分和不完全透射光部分组成的一般掩模曝光后显像并回流,使感光层一部分流下形成感光层不残留部分。 Such a photosensitive layer using the photosensitive layer 114 may be thinner consisting of reflux, and complete with a light transmissive portion after developing and refluxed mask partially transmitting and generally light exposure part, the photosensitive portion of the photosensitive layer from laminar flow is formed the remaining part.

接着,蚀刻感光层图案114及其下部层,即蚀刻导电体层60、中间层50及半导体层40。 Next, the photosensitive layer pattern 114 is etched and a lower layer, i.e., etching the conductive layer 60, intermediate layer 50 and the semiconductor layer 40. 这时,在数据布线部A原本不动地残留数据布线及其下部的层,在通道部C应只剩下半导体层,在剩余部分B完全除去上述三个层60、50、40,以露出栅极绝缘层30。 At this time, the original data wiring portion A fixedly residual data wiring and a lower layer, the channel portion semiconductor layer C should only, to completely remove the remaining portions of the three B layers 60,50,40 to expose The gate insulating layer 30.

如图19a及图19b所示,除去其它部分B露出的导电体层60,露出其下部的中间层50。 FIG. 19a and FIG. 19b, Part B to remove other exposed conductive layer 60, intermediate layer 50 to expose a lower portion thereof. 在该过程中均可以使用干蚀刻或湿蚀刻方法,优选地,应在导电体层60被蚀刻,感光层图案112、114几乎不被蚀刻的条件下进行。 Can be dry etching or a wet etching method in the process, preferably, be carried out in the etching, the photosensitive layer pattern 112 is hardly etched in the layer 60 is a conductive condition. 然而,在干蚀刻时,很难找到只蚀刻导电体层60而不蚀刻感光层图案112、114的条件,所以可以在感光层图案112、114也一同蚀刻的条件下进行。 However, during the dry etching, the etching is difficult to find not only the photosensitive layer pattern 112, the etching conditions of the conductive layer 60, can be carried out in the photosensitive layer pattern 112 is also etched together. 此时,比湿蚀刻时更要加厚第一部分114的厚度,以防止在该过程中除去第一部分露出下部导电体层60。 At this time, the wet etching is more than a thickness of the first portion 114 to be thickened to prevent the first portion of the exposed lower conductive layer 60 is removed in the process.

因此,如图19a及图19b所示,只剩下通道部C及数据布线部B的导电体层,即源极/漏极导电体图案67和存储电容器导电体图案68,其它部分B的导电体层60全部被除去,露出其下部的中间层50。 Thus, as shown in FIGS. 19a and 19b, only the conductive layer and the channel portion C of the B data wiring portion, i.e., the source / drain conductor patterns 67 and the storage capacitor conductor pattern 68, the other conductive portion B layer 60 have been removed, the intermediate layer 50 to expose a lower portion thereof. 这时,剩下的导电体图案67、64除了源极及漏极65、66未分离而连接之外与数据布线62、64、65、66、68形态相同。 At this time, the remaining conductor patterns 67, 64 except than the source and drain 65 and 66 are connected to the same data unseparated 62,64,65,66,68 form a wiring. 而且,使用干蚀刻时,感光层图案112、114的厚度也有一定程度的蚀刻。 Further, when the dry etching, the thickness of the photosensitive layer pattern 112 is also etched to some extent.

接着,如图20a及20b所示,用干蚀刻方法同时除去其它部分B露出的中间层50及其下部的半导体层40与感光层第一部分114。 Next, as shown in FIG. 20a and 20b, is removed by dry etching method while the intermediate layer 50 and the lower portion of the other portions of the semiconductor layer B is exposed photosensitive layer 40 and the first portion 114. 优选地,应在同时蚀刻感光层图案112、114和中间层50及半导体层40(半导体层和中间层几乎没有蚀刻选择性)、不蚀刻栅极绝缘层30的条件下进行。 Preferably, the etching is carried out at the same time conditions and the photosensitive layer pattern 112, 114 (the semiconductor layer and the intermediate layer is almost no etch selectivity), the gate insulating layer 30 without etching the intermediate layer 50 and the semiconductor layer 40. 特别是应在感光层图案112、114和半导体层40的蚀刻比几乎相同的条件下进行蚀刻。 Particularly by the photosensitive layer pattern etched at substantially the same etching rate of 112, 114 and semiconductor layer 40 conditions. 例如,使用SF 6和HCl混合气体或SF 6和O 2的混合气体,可以几乎相同的厚度蚀刻两个层。 For example, using a mixed gas of SF 6 and HCl or a mixed gas of SF 6 and O 2 may be the same thickness of the two layers hardly etched. 对感光层图案112、114和半导体层40的蚀刻比相同时,第一部分厚度应等于半导体层40和中间层50厚度之和或比其厚度小。 Etching the photosensitive layer pattern 112 and the semiconductor layer 40 than the same, shall be equal to the thickness of the first portion of the semiconductor layer 40 and the thickness of the intermediate layer 50 and to or smaller than the thickness thereof.

因此,如图20a及20b所示,除去通道部C的第一部分114露出源极/漏极导电体图案67,除去其它部分B的中间层50及半导体层40,露出其下部的栅极绝缘层30。 Thus, as shown in FIG. 20a and 20b, the first portion 114 is removed to expose the channel portion C of the source / drain conductor patterns 67, Part B to remove the intermediate layer 50 and the other semiconductor layer 40, a gate insulating layer to expose a lower portion thereof 30. 另外,数据布线A的第二部分112也被蚀刻,其厚度变薄。 Further, data wiring A second portion 112 is also etched, the thickness thereof becomes thinner. 在该工序中完成半导体图案42、48。 Semiconductor pattern 42, 48 is completed in this step. 附图标号57和58分别表示源极/漏极导电体图案67下部的中间层图案和存储电容器导电体图案64下部的中间层图案。 Reference numerals 57 and 58 denote a lower intermediate layer intermediate layer pattern 64 and the storage capacitor conductor pattern 67 of the lower portion of the source / drain conductive pattern pattern.

接着,通过抛光除去残留在通道部C的源极/漏极电体图案67表面的感光层残渣。 Subsequently, by polishing to remove the remaining portion of the channel C in the source / drain electrode pattern 67, the surface of the photosensitive layer residue.

然后,如图21a及21b所示,蚀刻除去通道部C的源极/漏极导电体图案67及其下部的源极/漏极中间层图案57。 Then, the source, the source is removed by etching the channel portion C of the source / drain conductive pattern 21a and 21b in FIG. 67 and a lower portion of the source / drain patterning the intermediate layer 57. 对源极/漏极导电体图案67和中间层图案57均可以只用干蚀刻来进行,或源极/漏极导电体图案67用湿蚀刻、对中间层图案57可以用干蚀刻进行。 The source / drain conductor patterns 67 and the intermediate layer 57 can be patterned only by dry etching is performed, or source / drain conductive pattern 67 by wet etching, the intermediate layer 57 may be patterned by dry etching. 属于前者时,优选地,源极/漏极图案67和中间层图案57在蚀刻比大的条件下进行蚀刻,这是因为,若蚀刻选择比不大就很难找到蚀刻终点,所以不容易控制残留在通道部C的半导体图案42的厚度。 Belonging to the former, preferably, the source / drain pattern and the intermediate layer 67 is etched in a pattern 57 is larger than the etching conditions, it is because if the etching selection ratio of the etching end point is not difficult to find, it is not easy to control remaining in the thickness of the semiconductor channel portion C of the pattern 42. 当属于交替进行湿蚀刻和干蚀刻的后者时,湿蚀刻的源极/漏极导电体图案67侧面被蚀刻,但干蚀刻的中间层图案57几乎不被蚀刻,所以呈现出阶梯状。 When the latter belong alternately wet etching and dry etching, wet etching the source electrode / drain electrode side conductor pattern 67 is etched, but the dry etching of the intermediate layer pattern 57 is hardly etched, thus showing a stepped shape. 蚀刻中间层图案57及半导体图案42时可使用的蚀刻气体为CF 4和HCl混合气体或CF 4和O 2的混合气体,若用CF 4和O 2 ,可以均匀厚度剩下半导体图案42。 Etching gas of the intermediate layer 57 and the semiconductor pattern when the pattern 42 may be used as a mixed gas of CF 4 HCI or a mixed gas of CF 4 and O 2, and, if using CF 4 and O 2, the remaining thickness may be uniformly semiconductor pattern 42. 这时,如图15b所示,半导体图案42的一部分被除去,其厚度可能变薄,感光层图案的第二部分112厚度也有一定程度的蚀刻。 In this case, as shown in FIG. 15b, a portion of the semiconductor pattern 42 is removed, the thickness may be thinner, the thickness of the second portion 112 of the photosensitive layer pattern is also etched to some extent. 这时应在绝缘层30不被蚀刻的条件下进行蚀刻,优选地,感光层图案应足够厚,以防止蚀刻第二部分112,露出其下部数据布线62、64、65、66、68。 In this case should be done under conditions not etched insulating layer 30 is etched, preferably, the photosensitive layer pattern should be thick enough to prevent etching of the second portion 112, which is exposed 62,64,65,66,68 lower data wirings.

因此,分离源极65和漏极66的同时完成数据布线62、64、65、66、68和其下部的接触层图案55、56、58。 Thus, while the separation of the source 65 and drain contact layer pattern 66 is completed and the data wiring 62,64,65,66,68 its lower 55,56,58.

最后,除去残留在数据布线A的感光层第二部分112。 Finally, removing the second portion of the data wire remaining in the photosensitive layer A 112. 然而,除去第二部分的工序可以在除去通道部C的源极/漏极导电体图案67之后和除去其下面中间层图案57之前进行。 However, the step of removing the second portion may be the source / drain conductive pattern 67 and before, after removing the intermediate layer pattern 57 is removed beneath the channel portion C of the source.

如上所述,可以交替进行湿蚀刻和干蚀刻或可以只进行干蚀刻。 As described above, may alternatively wet etching and dry etching or dry etching may be performed only. 属于后者时,因为只用一种蚀刻,所以工序比较简单,但很难找到合适的蚀刻条件。 When the latter, because only one etching step it is relatively simple, but it is difficult to find suitable etching conditions. 相反,属于前者时,容易找到蚀刻条件,但比后者工序复杂。 Conversely, when the former are easy to find etching conditions, but more complex than the latter step.

接着,如图22a及图22b所示,用CVD方法或PECVD方法制造a-SiCOH(低介电绝缘层)层形成保护层70。 Next, as shown in FIG. 22a and FIG. 22b, for producing a-SiCOH (low-dielectric insulating layer) The protective layer 70 is formed by a CVD method or a PECVD method. 这时,形成上述保护层的工序是将上述气体状态的化学式1至3的化合物中至少一个作为主源使用,上述氧化剂和Ar或He等气体一起添加混合SiH 4的反应气体混合物,通过CVD或PECVD方法淀积的工序。 In this case, the step of forming the protective layer is a compound of formula the gas state 1 to 3 in which at least one as a main source used, adding the gas mixture the reaction mixture SiH 4 together with the other said oxidant and Ar or He gas, by CVD or the method of PECVD deposition step. 这时,优选地,作为上述主源使用SiH(CH 3 ) 3 、SiO 2 (CH 3 ) 4 、(SiH) 4 O 4 (CH 3 ) 4 、Si(C 2 H 5 O) 4中至少一个,氧化剂使用N 2 O或O 2 In this case, preferably, SiH (CH 3) 3, SiO 2 (CH 3) 4, (SiH) as the primary source 4 O 4 (CH 3) 4 , the Si (C 2 H 5 O) 4 at least one , oxidizing agent, or N 2 O O 2. 此时,上述低介电绝缘层的介电常数在2-3之间。 In this case, a low dielectric permittivity of the insulating layer is between 2-3.

接着,如图23a至图23c所示,保护层70与栅极绝缘层30一起光学蚀刻形成分别露出漏极66、栅极衬垫24、数据衬垫68及存储电容器导电体图案64的接触孔。 Next, as shown in FIGS. 23a to 23c, the protective layer 70 and the gate insulating layer 30 is formed with an optical etching a contact hole 64 exposing the drain electrode 66, respectively, gate pad 24, the pad 68 and the data storage capacitor conductor pattern . 这时露出衬垫24、68的接触孔74、78的面积不超过2mm×60μm,优选在0.5mm×15μm以上。 In this case the exposed area of ​​the contact hole 74, 78 gasket 24,68 is not more than 2mm × 60μm, preferably at least 0.5mm × 15μm.

最后,如图8至图10所示,汽相淀积厚度为 Finally, as shown in FIG. 8 to FIG. 10, the thickness of vapor-deposited 的ITO层或IZO层,光学蚀刻形成与漏极66及存储电容器导电体图案64连接的像素电极82、与栅极衬垫24连接的辅助栅极衬垫86及与数据衬垫68连接的辅助数据衬垫88。 ITO layer or IZO layer is etched to form the optical storage capacitor and the drain electrode 66 and the conductor pattern connected to the pixel electrode 6482, an auxiliary gate pad 86 connected to the gate pad 24 and the pad 68 is connected to an auxiliary data data pad 88.

这时,用IZO形成像素电极82、辅助栅极衬垫86、及辅助数据衬垫88时,作为蚀刻液可以使用铬蚀刻液,因此在形成它们的光学蚀刻过程中,可以防止通过接触孔露出的数据布线或栅极布线金属的腐蚀。 In this case, the pixel electrode 82 is formed from IZO, the auxiliary gate pad 86, and the auxiliary data pad 88, as the etching solution may be used chrome etch solution, so they are in optical etching process is formed, exposed through the contact holes can be prevented the data wiring or the gate wiring metal corrosion. 这种蚀刻液有(HNO 3 /(NH 4 ) 2 Ce(NO 3 ) 6 /H 2 O)等。 This etchant has (HNO 3 / (NH 4) 2 Ce (NO 3) 6 / H 2 O) and the like. 而且,为了接触部的接触电阻变得最小,优选地,在室温至200℃的范围内叠层(堆垛)IZO。 Further, to the contact resistance of the contact portion becomes the smallest, preferably within a range from room temperature to 200 ℃ stack (stack) IZO. 形成IZO薄膜使用的目标优选包括In 2 O 3及ZnO,优选地,ZnO的含量在15-20wt%范围内。 IZO film formed using the target and preferably comprise 2 O 3, preferably, the In content of ZnO ZnO in the range 15-20wt%.

另外,优选地,在堆垛(stacking)ITO或IZO之前的预热工序中使用的气体为氮,这是为了防止在通过接触孔72、74、76、78露出的金属层24、64、66、68上形成金属氧化层。 In addition, preferably, the gas used in the preheating step before the stack (stacking) ITO or IZO as nitrogen, which is to prevent the metal layer exposed through the contact holes 72,74,76,78 24,64,66 a metal oxide layer, 68.

在本发明的第十一实施例中,不仅显示了第十实施例的效果,而且用一个掩模形成数据布线62、64、65、66、68和其下部的接触层图案55、56、58及半导体图案42、48,在该过程中分离源极65和漏极66,以可以简化制造工序。 In the eleventh embodiment of the present invention, not only it shows the effect of the tenth embodiment, the contact layer and the data wiring pattern 62,64,65,66,68 and 55,56,58 of the lower portion is formed with a mask 42, 48 and the semiconductor pattern, the source separation process 65 and the drain 66, to the manufacturing process can be simplified.

根据本发明的低介电绝缘层也适合在滤色器上形成薄膜晶体管阵列的AOC(滤色器上的阵列)结构中作为分离滤色器和薄膜晶体管的缓冲层使用。 As the buffer layer was separated using thin film transistor and a color filter (color filter on array) structure AOC also suitable for forming a thin film transistor array on the color filter according to the low dielectric insulating layer of the present invention.

图24是根据本发明第十二实施例的薄膜晶体管基片布局图,图25是沿着图24的XIX-XIX'线的薄膜晶体管基片截面图。 FIG 24 is a layout view of a thin film transistor substrate according to the twelfth embodiment of the present invention, FIG 25 is a sectional view of a thin film transistor substrate taken along line XIX-XIX 24 of FIG. 在图25中也图示了薄膜晶体管基片的下部基片和与它面对的上部基片。 In FIG 25 also illustrates the lower substrate and the thin film transistor substrate and the upper substrate facing it.

首先在下部基片,绝缘基片100上部形成包括由铜、铜合金、银、银合金、铝及铝合金等物质中某一个组成的下层201和由铬、钼、钼合金、氮化铬及氮化钼等物质中某一个组成的上部层202的数据布线。 First forming a lower layer comprising copper, copper alloy, silver, silver alloy, aluminum and aluminum alloy materials 201 and one composed of chromium, molybdenum, a molybdenum alloy, chromium nitride at the upper and lower substrate, an insulating substrate 100 a molybdenum nitride and other data wiring 202 consisting of an upper layer of material.

数据布线120、121、124包括纵向延伸的数据线120、连接在数据线120末端接收来自外部的信号并向数据线120传送的数据衬垫124及用数据线120的分支遮挡从基片100下部入射到将在以后形成的薄膜晶体管的半导体层170光的光遮挡部121。 120,121,124 data wiring includes a data line 120 extending in the longitudinal direction, a data pad 124 connected to the receiving signal transmitted from the outside to the data line 120 at the end of the data line 120 and a lower shield 100 from the substrate 120 with the branch cable the light incident to the light shielding portion 121 170 a semiconductor layer of a thin film transistor formed later on. 在这里,光遮挡部121还具有遮挡泄露光的黑阵的功能,它也可以与数据线120分离,以断开的布线形成。 Here, the light shielding portion 121 further includes a black matrix blocking light leakage function, it can be separated from the data line 120, to disconnect the wiring is formed.

数据布线120、121、124形成双层,但也可以由铜或铜合金、铝或铝合金、钼或钼-钨合金、铬、钽等导电物质组成的单一层形成。 120,121,124 double data wiring is formed, but may be made of copper or a copper alloy, aluminum or aluminum alloy, molybdenum or a molybdenum - a single layer of conductive material tungsten alloy, chromium, tantalum and other components.

在这里,考虑到将要形成的像素布线410、411、412及辅助衬垫413、414为ITO(氧化铟锡),数据布线120、121、124下层201由电阻小的物质-铝、铝合金、银、银合金、铜及铜合金等形成,上部层202由其它物质特别例举了与ITO接触性良好的物质-铬形成。 Wirings 410, 411 and the auxiliary pad pixel here, considered to be the 413, 414 is formed of ITO (indium tin oxide), a data wiring 201 120,121,124 underlayer material having a small resistance - aluminum alloy, silver, silver alloy, copper and copper alloy is formed, the upper layer 202 from other materials in contact with the ITO exemplified particularly good material - chromium formed. 具体实例为,下层201由Al-Nd形成,上部层202可以由CrNx形成。 Specific examples of the lower layer 201 is formed of Al-Nd, upper layer 202 may be formed of CrNx.

像素布线410、411、412及辅助衬垫413、414为IZO时,优选地,数据布线120、121、124由铝或铝合金的单一层制成,且铜与IZO及ITO的接触性良好,所以也可以由铜的单一层形成。 Pixel line 410, 411 and 413, 414 of the auxiliary pad IZO, preferably the data wiring 120,121,124 single layer made of aluminum or aluminum alloy, and copper in contact with the ITO and IZO good, They may be formed from a single layer of copper.

在下部绝缘层100上分别形成边缘部分与数据布线120、121的边缘部分重叠的红、绿、蓝的滤色器131、132、133。 Forming edge portion and the data wirings 120, 121 overlap the edge portions of the red, green, and blue color filters 131, 132, respectively, on the lower insulating layer 100. 在这里,滤色器131、132、133可以全部覆盖数据线120。 Here, the color filter 131, 132 may be entirely covered with the data line 120.

数据布线120、121、124及滤色器131、132、133上形成由a-SiCOH层组成的缓冲层140。 The buffer layer 140 is formed by a layer composed of a-SiCOH data wiring 131, 132, 120,121,124 and the color filter. 在这里,缓冲层140防止滤色器131、132、133的除气作用,还防止滤色器本身在后续工序当中由热及等离子能量引起的损伤。 Here, the buffer layer 140 prevents outgassing color filters 131, 132, the color itself but also to prevent damage caused by thermal and plasma energy which in a subsequent step. 而且,缓冲层140分离最下部的数据布线120、121、124和薄膜晶体管阵列,所以为了减少它们之间的寄生电容,应介电常数越低厚度越厚为好。 Further, the data wirings 120,121,124 buffer layer 140 and the thin film transistor array of the lowermost separation, so in order to reduce the parasitic capacitance between them, the dielectric constant should be thicker lower thickness as well. 考虑这一点,上述a-SiCOH层(低介电CVD层)最适合用于缓冲层140。 Considering that the a-SiCOH layer (a low dielectric CVD layer) most suitable for the buffer layer 140. 即,上述缓冲层的介电常数在较低的2-3之间,且汽相淀积速度很快,比BCB(二苯并环丁烯bisbenzocyclobutene)或PFCB(全氟环丁烯perfluorocyclobutene)等有机绝缘物质价格低廉。 That is, the dielectric constant of the buffer layer between the lower 2-3, vapor deposition and quickly than BCB (dibenzo cyclobutene bisbenzocyclobutene) or PFCB (perfluoro-cyclobutene perfluorocyclobutene), etc. The organic insulating material low prices. 而且,上述低介电绝缘薄膜在室温至400℃的宽温度范围内具有优秀的绝缘特性。 Further, the low dielectric insulating film in a wide temperature range of room temperature to 400 deg.] C having an excellent insulating property.

在缓冲层140上形成双层结构的栅极布线,它包括铜、铜合金、银、银合金、铝及铝合金等物质中某一个组成的下层501和铬、钼、钼合金、氮化铬、氮化钼等物质中的某一个组成的上部层502。 Two-layer structure of the gate wiring is formed on the buffer layer 140, 501 and a lower layer comprising chromium, molybdenum, a molybdenum alloy, chromium nitride, copper, copper alloy, silver, silver alloy, aluminum and aluminum alloys consisting of one material , one of the upper layer 502 composed of a molybdenum nitride material.

栅极布线包括横向延伸与数据线120交叉限定像素的栅极线150、连接在栅极线150末端接收来自外部的扫描信号并向栅极线150传送的栅极衬垫152及栅极线150一部分的薄膜晶体管的栅极151。 The gate wiring includes laterally extending gate lines crossing the data lines 120 defining pixels 150 connected to receive the scan signal from the outside at the end of the gate line 150 and gate pad 152 and the gate lines 150 transfer gate line 150 the gate portion of the thin film transistor 151.

栅极线150与后述的像素电极410重叠,形成提高电荷保存能力的存储电容器。 The gate line 150 and the pixel electrode 410 overlaps described later, a storage capacitor is formed to improve the charge retention ability. 当后述的像素电极410和栅极线150重叠发生的存储电容不充分时,也可以形成存储电容的共同电极。 When the storage capacitor of the pixel electrode 410 and the gate line 150 to be described later is not sufficient overlap, the common electrode may be formed on the storage capacitor.

这样,栅极布线形成双层时优选地,一层由低电阻物质形成,另一层由与其它物质接触性良好的物质形成,例如,Al(或Al合金)/Cr的双层或Cu/Cr的双层。 Thus, the gate wiring is formed bilayer Preferably, a layer formed of a low resistance material is formed from another layer in contact with other substances with good material, e.g., Al (or Al alloy) / Cr bilayer, or Cu / Cr bilayer.

栅极布线150、151、152可以由低电阻的铜或铝或铝合金等单一层形成。 150,151,152 gate wiring may be formed of a single layer such as copper or aluminum or aluminum alloy low resistance.

在栅极布线150、151、152及缓冲层140上形成栅极绝缘层160。 Forming a gate insulating layer on the gate wiring 160 and the buffer layer 140 150,151,152. 这时,低温汽相淀积栅极绝缘层160可以由有机绝缘层、低温非晶硅氧化物层、低温氮化硅层等形成。 In this case, low-temperature vapor deposition of the gate insulating layer 160 may be formed of an organic insulating layer, an amorphous silicon oxide layer is low, the low temperature silicon nitride layer is formed. 根据本发明的薄膜晶体管结构中,因滤色器形成在下部基片,所以栅极绝缘层没有使用高温下汽相淀积的普通绝缘层,而使用了在低温例如250℃以下低温条件下汽相淀积的低温淀积绝缘层。 The thin film transistor structure according to the present invention, since the color filter is formed in the lower substrate, the gate insulating layer insulating layer no ordinary vapor deposition at a high temperature of use, the steam is used at a low temperature below 250 ℃ low temperature e.g. low-temperature-deposited insulating layer is deposited.

此外,在栅极151的栅极绝缘层160上形成岛状的双层结构的半导体层171。 Further, a two-layer structure of the semiconductor layer 171 in an island shape gate electrode 160 on the gate insulating layer 151. 在双层结构的半导体层171中,下层半导体层701由带隙大的非晶硅组成,上部层半导体层702比起下层半导体层701由带隙小的普通非晶硅组成。 In the two-layer structure of the semiconductor layer 171, the lower semiconductor layer 701 by a large band gap amorphous silicon, the upper layer of the semiconductor layer 702 than the lower semiconductor layer 701 by a small band gap ordinary amorphous silicon. 例如,以下层半导体层701的带隙为1.9-2.1eV、上部层半导体层702的带隙为1.7-1.8eV形成。 For example, the band gap of the layer of the semiconductor layer 701 is 1.9-2.1eV, the upper layer of the band gap of the semiconductor layer 702 is formed 1.7-1.8eV. 在这里,下层半导体层701以 Here, the lower semiconductor layer 701 to 厚度形成,上部层半导体层702以 The thickness is formed, the upper layer of the semiconductor layer 702 to 厚度形成。 The thickness is formed.

在带隙互不相同的上部层半导体层702和下层半导体层701之间形成相当与两层带隙的频带剩余偏差。 Residual deviation band is formed with two relatively bandgap between a bandgap different from each other in an upper layer of the semiconductor layer 702 and the lower semiconductor layer 701. 当控制TFT以接通时,在位于两个半导体层701、702之间的频带剩余偏差区域形成通道。 When the control is turned on in a TFT channel is formed in the residual deviation band region located between the two semiconductor layers 701,702. 该频带剩余偏差区域基本上具有相同的原子结构,其缺陷少,可以认为它具有良好的TFT特性。 The residual deviation band region have substantially the same atomic structure, small defects, it is considered that it has excellent TFT characteristics.

半导体层171也可以有单一层形成。 The semiconductor layer 171 may have a single layer.

在半导体层171上,包含非晶硅的欧姆接触层182、183以分离状态形成,其中该非晶硅利用诸如磷这样的n型杂质、微晶硅、或金属硅化物以高浓度掺杂。 On the semiconductor layer 171, the ohmic contact layer of amorphous silicon 182 and 183 to form a separated state, wherein the amorphous silicon n-type impurities such as phosphorus using this, microcrystalline silicon, or a metal silicide doped with a high concentration.

在欧姆接触层182、183上形成包括ITO组成的源极及漏极412、411及像素电极410的像素布线元件410、411、412。 ITO composition comprising a source and a drain of 412,411 pixels and the pixel electrode 410 of the wiring elements 410, 411 formed on the ohmic contact layer 182, 183. 源极412通过栅极绝缘层160及缓冲层140上形成的接触孔161与数据线120连接。 The source contact holes 412 is formed on the gate insulating layer 160 and the buffer layer 140, 161 is connected to the data line 120. 漏极411与像素电极410连接,从薄膜晶体管接收图像信号向像素电极410传送。 The drain 411 is connected to the pixel electrode 410, receives an image signal transmitted to the pixel electrode 410 from the thin film transistor. 像素布线元件410、411、412由ITO或IZO类透明导电物质组成。 Pixel interconnection elements 410, 411 of ITO or IZO based transparent conductive substance.

而且,在像素布线元件410、411、412同一层上通过接触孔162、164形成分别与栅极衬垫152及数据衬垫124连接的辅助栅极衬垫413及辅助数据衬垫414。 Further, on the same layer as the pixel wiring member 410, 411 162, 164 forming an auxiliary gate pad 152 are respectively connected to the gate pad and a data pad 124 of the pad 413 and auxiliary data 414 through the contact hole. 在这里,辅助栅极衬垫413与栅极衬垫152的上部层502-铬层直接接触,辅助数据衬垫414又与数据衬垫124的上部层202-铬层直接接触。 Here, the auxiliary gate pad 413 in direct contact with the gate pad upper layer 502- chromium layer 152, the auxiliary data pad and the data pad 414 and an upper layer in direct contact with the chromium layer 124 202-. 这时优选地,当栅极衬垫152及数据衬垫124包含氮化铬层或氮化钼层时,辅助栅极衬垫413及辅助数据衬垫414与氮化铬层或氮化钼层接触。 Preferably this case, when the gate pad 152 and a data pad 124 comprises a layer of chromium nitride or molybdenum nitride layer, an auxiliary gate pad 413 and the auxiliary data pad 414 and the layer of chromium nitride or molybdenum nitride layer contact. 它们起增加衬垫152、124和外部电路装置之间的粘合性及保护衬垫的作用,但并非必需,适用与否具有选择性。 They act to increase adhesion between the protective liner and the liner and an external circuit arrangement 152,124, but not necessarily, suitable for selective or not. 像素电极410还与相邻的栅极线150及数据线120重叠,以增加开口率,但也可以不重叠。 And further the pixel electrode 410 adjacent gate lines 150 and data lines 120 overlap, in order to increase the aperture ratio, but may not overlap.

欧姆接触层182、183具有降低ITO源极及漏极412、411和半导体层171之间的接触电阻功能,可以包括形成微晶硅层或钼、镍、铬等金属硅化物,可以残留硅化物金属层。 The ohmic contact layer 182, 183 having a function of reducing the contact resistance between the source and drain 412,411 ITO and a semiconductor layer 171, a microcrystalline silicon layer may be formed or include molybdenum, nickel, chromium, metal silicides, silicide may remain metal layers.

在源极及漏极412、411上形成保护薄膜晶体管的保护层190,在其上部形成光吸收良好的具有深颜色的感光性有色有机层430。 Protective layer for protecting the thin film transistor formed on the source and drain 412,411 190, a photosensitive layer 430 having the organic colored light absorbing dark color is formed on an upper portion thereof good. 这时,有色有机层430起到遮挡入射到薄膜晶体管半导体层171的光的作用,调节有色有机层430的高度,作为保持下部绝缘基片100和与其面对的上部绝缘基片200之间间距的间隔手段。 At this time, the organic colored layer 430 functions to shield light incident on the thin film transistor including a semiconductor layer 171 of the role of regulating the height of the organic colored layer 430, a lower insulating substrate 100 to maintain the upper portion of the insulating substrate opposed thereto, and the spacing between the 200 the spacing means. 在这里,保护层190和有机层430可以沿着栅极线150和数据线120形成,有机层430也可以具有遮挡栅极布线和数据布线周围露出光的作用。 Here, the protective layer 190 and an organic layer 430 may be formed along the gate line 150 and data line 120, the organic layer 430 may also have a shielding effect around the gate wiring and the data wiring is exposed to light.

这时,有机层430如同后述的根据本发明第十三实施例的薄膜晶体管基片,全部遮盖像素电极及与各金属层的缝隙时,在上部基片上无需再设计遮挡光的单独黑阵。 At this time, the organic layer 430 as a thin film transistor substrate according to a thirteenth embodiment of the present invention to be described later, to cover all the slits of each pixel electrode and the metal layer on the upper substrate do not need to design a separate black matrix blocking light .

另外,在上部基片200上全面形成由ITO或IZO组成且与像素电极410一起形成电场的共同电极210。 Further, the common electrode 210 is formed on the entire ITO or IZO and is composed of an electric field together with the pixel electrode 410 is formed on the upper substrate 200.

参照图26a至33b和前面的图24及图25详细说明根据本发明实施例的薄膜晶体管基片的制造方法。 26a to 33b method of manufacturing a thin film transistor substrate according to embodiments of the present invention, the foregoing and FIG. 24 and FIG. 25 described in detail with reference to FIG.

首先,如图26a和图26b所示,用溅射类方法依次汽相淀积具有像铝或铝合金或铜或铜合金等低电阻导电物质和像铬或钼或钛或氮化铬或氮化钼等与ITO接触性良好的导电物质,用掩模的光学蚀刻工序进行干蚀刻或湿蚀刻,由此在下部绝缘基片100上形成包括下层201和上部层202的双层结构组成的数据线120、数据衬垫124及光遮挡部121的数据布线120、121、124。 First, as shown in FIG. 26a and FIG. 26b, successively by a sputtering vapor deposition method of the class of low resistance conductive material, or aluminum or aluminum alloy and copper or a copper alloy as chromium or molybdenum or titanium or chromium nitride or nitrogen as having contact with the ITO material of good electrical conductivity such as molybdenum, dry etching or wet etching, an etching step using an optical mask, thereby forming a lower layer 201 comprising data and two-layer structure consisting of an upper layer 202 on the lower insulating substrate 100 line 120, data pad 124 and the data wiring 121 of the light shielding portion 120,121,124.

如上所述,考虑到以后形成的像素布线410、411、412及辅助衬垫413、414是ITO,形成了由铝或铝合金或铜或铜合金的下层201和铬或钼或钛的上部层组成的数据布线,但当像素布线410、411、412及辅助衬垫413、414为IZO时,也可以由铝或铝合金的单一层形成,由铜或铜合金的单一层形成可以简化制造工序。 As described above, the pixel and the auxiliary wirings 410, 411 formed in pad 413, 414 is taken into account after the ITO, is formed by the lower aluminum or an aluminum alloy or copper or a copper alloy and an upper layer 201 of chromium or titanium or molybdenum composition data wiring, but when a pixel line 410, 411 and 413, 414 of the auxiliary pad when IZO, may be formed from a single layer of aluminum or aluminum alloy, formed by a single layer of copper or copper alloy can simplify the manufacturing process .

接着,如图27a及图27b所示,依次涂布包括红、绿、蓝颜料的感光性物质,用掩模的光学蚀刻工序制作布线图案依次形成红、绿、蓝的滤色器131、132、133。 Next, as shown in FIG. 27a and FIG. 27b, in turn comprising a coating of red, green, blue pigment photosensitive material, the formation of red, green, and blue color filters 131, 132 by optical etching mask patterning step of sequentially 133. 这时,红、绿、蓝的滤色器131、132、133虽然用三张掩模形成,但为了减少成本,可以用一个掩模移动形成。 In this case, the red, green, and blue color filters 131, 132, while a mask is formed by three, but in order to reduce costs and to be formed with a moving mask. 而且,若利用激光转写方法或打印方法,不用掩模也可以形成,因此成本可以降到最低。 Moreover, if the use of a laser transfer printing method or methods, no mask can also be formed, so the cost can be minimized. 这时,如图所示,优选地,红、绿、蓝滤色器131、132、133的边缘与数据线120重叠。 In this case, as shown, preferably red, green and blue color filters 131, 132 and the edge 120 overlaps the data line.

接着,图28a及图28b所示,用上述汽相淀积方法在绝缘基片100上制造a-SiCOH层(低介电绝缘层)形成缓冲层140。 Next, as shown in FIGS. 28a and FIG. 28b, the above-described vapor deposition method for producing a-SiCOH layer (low dielectric insulating layer) on the insulating substrate 100, buffer layer 140 is formed.

接着,用溅射类方法连续汽相淀积像铬或钼或钛或氮化铬或氮化钼等物理化学性稳定的物质和像铝或铝合金或铜或铜合金等具有低电阻的导电物质,用掩模的光学蚀刻工序制作布线图案,在缓冲层140上形成包括栅极线150、栅极151及栅极衬垫152的栅极布线150、151、152。 Subsequently, using a sputtering vapor deposition method for the continuous type as the conductive material physically chemically stable chromium or molybdenum or titanium or chromium nitride, molybdenum nitride, or the like, or alloy such as aluminum and copper or copper alloy, or the like having a low resistance material, with an etching step of patterning the optical mask including a gate line 150, gate 151 and the gate pad of the gate wiring 152 150,151,152 140 formed on the buffer layer.

这时,栅极布线元件150、151、152可以由单一层结构形成。 At this time, the gate wiring elements 150,151,152 may be formed of a single layer structure.

接着,如图29所示,在栅极布线元件150、151、152及有机绝缘层140上依次汽相淀积低温淀积栅极绝缘层160、第一非晶硅层701、第二非晶硅层702及掺杂的非晶硅层180。 Next, as shown in FIG. 29, on the gate wiring elements 150,151,152 and the organic insulating layer 140 are sequentially vapor-deposited low-temperature deposition of the gate insulating layer 160, a first amorphous silicon layer 701, a second amorphous amorphous silicon layer 702 and silicon layer 180 doped.

低温汽相淀积的栅极绝缘层160可以使用250℃以下汽相淀积温度中汽相淀积的有机绝缘层、低温非晶硅氧化物层、低温非晶硅氮化物层形成。 The gate insulating layer 160 of low temperature vapor deposition using an organic insulating layer may be below 250 ℃ vapor deposition in the vapor deposition temperature, low temperature amorphous oxide layer, an amorphous silicon nitride layer is formed low.

第一非晶硅层701由带隙大的非晶硅层,如具有1.9-2.1eV带隙的非晶硅层形成,第二非晶硅层702由带隙比第一非晶硅层701低的、如具有1.7-1.8eV带隙的一般非晶硅层形成。 First amorphous silicon layer 701 by the band gap of the amorphous silicon layer, such as an amorphous silicon layer having a 1.9-2.1eV bandgap is formed, a second amorphous silicon layer 702 having a band gap than the first amorphous silicon layer 701 low, as generally having a 1.7-1.8eV bandgap amorphous silicon layer is formed. 这时,第一非晶硅层701向非晶硅层原料气体SiH 4添加适量CH 4 、C 2 H 2 、或C 2 H 6等,并通过CVD方法汽相淀积。 At this time, the first amorphous silicon layer 701 is added to the amorphous silicon layer SiH 4 source gas amount CH 4, C 2 H 2, C 2 H 6 or the like, by a CVD method and a vapor deposition. 例如,若在CVD装置中投入1:9的SiH 4 :CH 4并进行汽相淀积工序,那么C含量大约有50%左右,可以汽相淀积具有2.0-2.3eV带隙的非晶硅层。 For example, when the input apparatus 1 in a CVD: SiH 9 to 4: CH 4 and the vapor deposition step, the C content is about 50%, it can be vapor deposition of amorphous silicon having a 2.0-2.3eV bandgap Floor. 这样,非晶硅层的带隙受工序条件的影响,根据碳化合物的添加量大约在1.7-2.5eV范围内可以容易调节带隙。 Thus, the band gap of the amorphous silicon layer is affected by process conditions, approximately in the range 1.7-2.5eV bandgap can be easily adjusted according to the amount of the carbon compound.

低温汽相淀积栅极绝缘层160、第一非晶硅层701及第二非晶硅层702、掺杂非晶硅层180在同一CVD装置中不破坏真空状态的情况下可以连续汽相淀积。 Low temperature vapor deposition of the gate insulating layer 160, the first amorphous silicon layer 701 and the second amorphous silicon layer 702, a doped amorphous silicon layer 180 may be continuously in the same vapor phase CVD apparatus without breaking the vacuum state deposition.

然后,如图30a及30b所示,用掩模光学蚀刻工序对第一非晶硅层701、第二非晶硅层702及掺杂非晶硅层180制作布线图案,形成岛状半导体层171及欧姆接触层181,同时在低温汽相淀积栅极绝缘层160和有机绝缘层140上形成分别露出数据线120、栅极衬垫152及数据衬垫124的接触孔161、162、164。 Then, as shown in FIG. 30a and 30b, the optical mask etching step of the first amorphous silicon layer 701, a second doped amorphous silicon layer 702 and patterning the amorphous silicon layer 180, island-shaped semiconductor layer 171 and the ohmic contact layer 181, while the gate insulating layer 160 deposited and an organic insulating layer 120 at a low temperature vapor, the gate pad contact hole 152 and the data lines are exposed data pad 124 is formed on 140 161,162,164.

在除了栅极151上部的其它部分中全部除去第一、第二非晶硅层701、702及掺杂非晶硅层180。 In addition to other portions of the upper portion of the first gate electrode 151 completely removed, and the second amorphous silicon layer doped amorphous silicon layer 701, 702, 180. 在栅极衬垫152的上部与第一、第二非晶硅层701、702及掺杂的非晶硅层180一起除去栅极绝缘层160。 The gate insulating layer 160 is removed together with the upper portion of the gate pad and the first and second amorphous silicon layer 701 and 702 and the doped amorphous silicon layer 152 180. 在数据线120及数据衬垫124上部与第一、第二非晶硅层701、702及掺杂的非晶硅层180及低温汽相淀积栅极绝缘层160一起除去有机绝缘层140。 The organic insulating layer 140 is removed together with the data line 120 and the data pad 124 and the upper portion of the first and second amorphous silicon layer 701 and 702 and the doped amorphous silicon layer 180 and the low temperature vapor-deposited gate insulating layer 160.

为了用一枚掩模的光学蚀刻工序形成,将部分具有不同厚度的感光层图案作为蚀刻掩模使用。 To form an optical mask with an etching step, the portion of the photosensitive layer pattern having different thicknesses is used as an etching mask. 对此参照图31和图32进行说明。 Referring to this FIG 31 and FIG 32 will be described.

首先,如图31所示,在掺杂的非晶硅层180上以1-2μm厚度涂布感光层后,通过用掩模的光学蚀刻工序向感光层照射光,显像形成感光层图案312、314。 First, as shown in FIG. 31, on the doped amorphous silicon layer 180 to a thickness of 1-2μm after coating the photosensitive layer, the photosensitive layer pattern 312 is formed to the photosensitive layer is irradiated with light, an imaging optical mask for an etching step 314.

这时,感光层图案312、314中位于栅极151上部的第一部分312比剩下的第二部分厚度厚,使数据线120、数据衬垫124及栅极衬垫152的部分之上不存在感光层。 In this case, the photosensitive layer pattern 312, 314, 312 located in the remaining second portion of the upper portion of the gate electrode 151 thicker than the first portion, the data line 120, over the portion of the data pad 124 and the gate pad 152 is not present photosensitive layer. 优选地,第二部分314的厚度在第一部分312厚度的1/2以下,例如,优选在 Preferably, the thickness of the second portion 314 of the first portion 312 of a thickness of 1/2 or less, for example, preferably 以下。 the following.

这样,根据位置使感光层具有不同厚度的方法可以有多种,但在这里只说明用正性感光层的情况。 Thus, according to the position of the photosensitive layers having different thicknesses can be a variety of ways, but here only described the case of a positive-working photosensitive layer.

比曝光机的分解力(分辨率)小的图案,例如在B区域形成狭缝或直角形态的图案或形成半透明层,通过可以调节光照射量的掩模1000向感光层照射光,则根据被照射的光量或强度聚合物分解的程度就不同。 Small patterns, for example, a exposure device than the resolving power (resolution) in the region B at right angles to form a slit pattern or a translucent layer or, may be adjusted by the amount of light irradiation to the mask is irradiated with light the photosensitive layer 1000, in accordance with the amount or degree of light intensity of the irradiated polymer decomposes is different. 这时,若在完全露在光下的C区域聚合物完全分解的时间中断曝光,比起完全露在光的部分,通过狭缝或半透明的B区域的光照射量少,因此B区域的感光层只分解一部分,剩余部分以未分解的状态剩下。 In this case, when fully exposed to light in the region C the polymer is completely decomposed interrupt the exposure time than light completely exposed portion by irradiating slit light or less translucent areas B, and therefore region B only a portion of the decomposition of the photosensitive layer, the remaining portion of the remaining undecomposed state. 若延长曝光时间,则会分解所有分子,所以应防止出现这种现象。 If the longer exposure time, it will break down all the molecules, so should prevent this phenomenon.

若显像这种感光层,分子未分解的第一部分312几乎原本不动地剩下,光照射少的第二部分314以比第一部分312剩下薄厚度的一部分,被光完全曝光的C区域的感光层几乎全被除去。 When developing this photosensitive layer, a first portion of molecules are not decomposed almost 312 otherwise remaining motionless, less than the light irradiation part 314 to the remaining first thin thickness portion 312, the light is completely exposed region of the second portion C the photosensitive layer was almost completely removed.

通过上述方法,制造根据位置厚度不同的感光层图案。 By the above method of manufacturing the thicknesses of the different position of the photosensitive layer pattern.

接着,如图32所示,把这种感光层图案312、314作为蚀刻掩模使用,对掺杂的非晶硅层180、第二非晶硅层702、第一非晶硅层701及低温汽相淀积栅极绝缘层160进行干蚀刻,完成露出栅极衬垫152的接触孔162,并露出C区域的缓冲层140。 Next, as shown in FIG. 32, the photosensitive layer pattern 312, such as an etching mask using a doped amorphous silicon layer 180, a second amorphous silicon layer 702, the first amorphous silicon layer 701 and the low vapor-deposited gate insulating layer 160 is dry etched to complete the contact holes 152 exposing the gate pads 162, and the exposed region of the buffer layer 140 C. 接着,将感光层图案312、314作为蚀刻掩模使用,干蚀刻C区域的缓冲层140,完成露出数据线120及数据衬垫124的接触孔161、164。 Subsequently, the photosensitive layer pattern 312 used as an etching mask, dry etching the buffer layer 140 of the region C, contact holes 161 and 164 exposing the completion of the data line 120 and the data pad 124.

接着,完全除去感光层第二部分314。 Next, to completely remove the photosensitive layer of the second portion 314. 在这里,为了完全除去第二部分314的感光层残渣,可以附带进行利用氧气的抛光工序。 Here, the photosensitive layer in order to completely remove the residue of the second portion 314, can be attached to the polishing step with oxygen.

因此,除去感光层图案的第二部分314,露出掺杂的非晶硅层180,感光层图案第一部分312也变薄,其减少的厚度正好是感光层图案第二部分314的厚度。 Thus, removing the second portion of the photosensitive layer pattern 314 is exposed doped amorphous silicon layer 180, a first portion of the photosensitive layer pattern 312 is also thin, which reduces the thickness of the photosensitive layer thickness is just the second portion 314 of the pattern.

然后,将剩下的感光层图案第一部分312作为蚀刻掩模使用,蚀刻除去掺杂的非晶硅层180及其下部的第一及第二非晶硅层701、702,在栅极151上部的低温汽相淀积栅极绝缘层160上形成岛状半导体层171和欧姆接触层181。 Then, the remaining portion of the first photosensitive layer pattern 312 used as an etching mask, etching the doped amorphous silicon layer 180 is removed and the lower portion of the first and second amorphous silicon layer 701 and 702, the upper portion of the gate 151 the low temperature vapor deposition island-shaped semiconductor layer 171 and the ohmic contact layer 181 on the gate insulating layer 160.

最后,除去剩余的感光层第一部分312。 Finally, remove the remaining portion of the first photosensitive layer 312. 在这里,为了完全除去第一部分312的感光层残渣,可以附带进行利用氧气的抛光工序。 Here, the photosensitive layer in order to completely remove the residue of the first portion 312, can be attached to the polishing step with oxygen.

然后,如图33a及图33b所示,汽相淀积ITO层,用掩模蚀刻工序制作布线图案形成像素电极410、源极412、漏极411、辅助栅极衬垫413及辅助数据衬垫414。 Then, as shown in FIGS. 33a and 33b, the vapor-deposited ITO layer, the pixel electrode 410 is formed by patterning step an etching mask, the source electrode 412, drain electrode 411, the auxiliary gate pad 413 and the auxiliary data pad 414. 这时可以用IZO替代ITO。 In this case IZO can replace ITO.

接着,将源极412和漏极411作为蚀刻掩模使用,蚀刻它们之间的欧姆接触层181,形成分离为两部分182、183的欧姆接触层图案,并在源极412和漏极411之间露出半导体层171。 Next, the source 412 and drain 411 used as an etching mask, the ohmic contact layer 181 is etched between them, forming an ohmic contact layer pattern is separated into two parts 182, 183, and 412 and the drain 411 of the source of between the semiconductor layer 171 is exposed.

最后,如图34及图35所示,在下部绝缘基片100上部依次淀积包括氮化硅或氧化硅等绝缘物质和包含黑色颜料的感光性有机物质等的绝缘物质,用掩模光学蚀刻工序曝光显像形成有色有机层430,将它作为蚀刻掩模使用,蚀刻其下部的绝缘物质形成保护层190。 Finally, as shown in FIG. 34 and 35, sequentially depositing insulating material comprises silicon nitride or silicon oxide, a photosensitive organic insulating substance and a black pigment substances contained in the lower portion of the upper insulating substrate 100, an optical etching mask the organic layer was exposed colored developing step 430 is formed, it will be used as an etching mask, etching the insulating material forming the protective layer of the lower portion 190. 这时,有色有机层430遮挡向薄膜晶体管入射的光,并可以位于栅极布线和数据布线上部,具有遮挡布线周围露出光的功能。 At this time, the organic colored layer 430 block the light incident on the thin film transistor, and may be located in the upper portion of the gate wiring and data wiring, a wiring having shielding ambient light is exposed functions. 而且,如同本发明的实施例,控制用作保持间隙的材料的有机层430的高度。 Further, as in the embodiment of the present invention, the control layer is used as the organic material to maintain a gap 430 height.

另外,在上部绝缘基片200上堆垛(叠层)ITO或IZO的透明物质以形成共同电极210。 Further, stacking a transparent material (laminate) the ITO or IZO on the upper insulating substrate 200 to form a common electrode 210.

在这种情况下,将有色有机层430设计成全部遮盖像素电极410及与每个金属层的缝隙时,在上部基片上就无需再设计遮挡光的单独黑阵。 In this case, the colored organic layer 430 is designed to cover the entire slot 410 and the metal layer of each pixel electrode, on the upper substrate will not have to design a separate black matrix blocking light.

当将栅极线150和像素电极410的间隔设计为一定间距时,需要遮挡像素电极410和栅极线150之间泄露光的部分。 When the spacer gate line 150 and the pixel electrode 410 is designed as a spacing, it is necessary to block light leaking portion of the pixel electrode 150 and the gate line 410. 为此,将形成在滤色器131、132、133下部的数据线120的一部分向栅极线150方向突出延长,使之可以遮挡栅极线150和像素电极410之间的缝隙。 For this purpose, the projection is formed to extend in the 150 direction of the gate line 131, a portion of the lower portion of the color filter 120 of the data lines, so that it can shield the gap between the gate lines 410 and the pixel electrode 150. 在不能被数据线120覆盖的区域,特别是,在相邻的数据线120之间的区域,形成色有机层430以覆盖间隙。 In a region not covered by the data line 120, in particular, in the region between the adjacent data lines 120, the organic layer 430 is formed to cover the color space.

虽然未在附图中示出,但是在与栅极布线150、151、152相同层形成黑阵的纵向部,它以形成栅极布线150、151、152的物质形成且在画面显示部的边缘周围遮挡泄露光。 Although not shown in the drawings, the longitudinal portions are formed in the same layer as the gate wirings 150,151,152 black matrix, which is to form a gate wiring is formed and the substance 150,151,152 edge of the display screen portion blocking ambient light leakage. 在数据布线120、121、124相同层形成黑阵的横向部,它以形成数据布线120、121、124的金属物质形成,在画面显示部的边缘周围遮挡泄露光。 Data wiring is formed in the same layer 120,121,124 lateral portion of the black matrix, it is formed of metal substance 120,121,124 data wiring is formed, a display peripheral edge portion blocking light leakage in the picture.

就这样,以形成栅极布线150、151、152及数据布线120、121、124的物质形成在画面显示部边缘周围遮挡泄露光的黑阵横向部及纵向部,用数据布线120、121、124遮挡栅极线150和像素电极410之间泄露光的区域。 In this way, the material to form the gate wiring and data wiring 120,121,124 150,151,152 formed in the screen of the display unit around the lateral edges of the black matrix portion and the blocking portion longitudinal light leakage, data wirings 120,121,124 the gate line 150 and the shielding area of ​​the light leakage between the pixel electrode 410. 并且用有色有机层430遮挡相邻的两个数据布线150之间的泄漏光时,数据布线、栅极布线及间距保持手段可以遮挡薄膜晶体管基片中光泄漏的全部区域,所以在上部基片无需形成单独黑阵。 When the colored layer 430 and the organic blocking two adjacent light leakage between the data wiring 150, a data wiring, the gate wiring and the spacer means can block the entire region of the thin film transistor substrate of the light leakage, so the upper substrate without forming a separate black matrix. 因此,不考虑上部基片和下部基片的整列误差也可以提高开口率。 Thus, irrespective of the upper substrate and the lower substrate aligned errors may also increase the aperture ratio. 而且,数据线120和像素电极410之间形成栅极绝缘层160和低介电的缓冲层140,因此可以使它们之间发生的寄生电容变得最小,可以提高显示器的特性,同时它们之间无需设置间距,所以可以保持最大开口率。 Further, the gate insulating layer 160 and a low dielectric buffer layer 140 is formed between the data line 410 and the pixel electrode 120, it is possible to make the parasitic capacitance between them is minimized, you can improve the characteristics of the display, while between them no need to set the pitch, the maximum aperture ratio can be maintained.

因此,本发明的实施例中,为了在滤色器上稳定显示形成薄膜晶体管的薄膜晶体管基片,在低温工序条件下制造TFT。 Thus, embodiments of the present invention, in order to stabilize the display on the color filter substrate forming a thin film transistor TFT, the TFT manufacturing process at a low temperature conditions. 即,为了防止在高温工序引起的滤色器的损伤,栅极绝缘层用低温汽相淀积绝缘层形成,为了防止与低温淀积栅极绝缘层接触引起的通道部的性能下降,通道部不在低温淀积栅极绝缘层和半导体层的界面上形成,而在半导体层的一侧形成。 That is, in order to prevent damage to the color filter at a high temperature caused by the step, the gate insulating layer with a low temperature vapor-deposited insulating layer is formed, in order to prevent the performance of the channel portion of the gate insulating layer in contact with the low temperature drop caused by the deposition, the channel portion low temperature is not deposited on the interface gate insulating layer and the semiconductor layer is formed, is formed at one side of the semiconductor layer.

根据本发明的低介电CVD层在薄膜晶体管阵列上形成滤色器的COA(阵列上的滤色器)结构中,可以作为在滤色器和像素电极之间形成的保护层使用。 According to the present invention a low dielectric CVD layer on the thin film transistor forming a color filter array COA (color filter on array) structure may be used in accordance with a protective layer between the color filter and the pixel electrode is formed. 对此,参照附图将详细说明。 In this regard, with reference to the drawings will be described in detail.

首先,参照图34至图35详细说明根据本发明第十实施例的用于液晶显示器的薄膜晶体管基片结构。 First, described in detail with reference to FIGS. 34 to 35 for a thin film transistor liquid crystal display substrate structure according to the tenth embodiment of the present invention.

图34是根据本发明第十三实施例的用于液晶显示器的薄膜晶体管基片布局图,儿图35是沿着图34的XXIX-XXIX'线的薄膜晶体管基片截面图。 The thin film transistor substrate for a liquid crystal display layout view of FIG. 34 is a thirteenth embodiment of the present invention, a child 35 is a sectional view of a thin film transistor substrate taken along line XXIX-XXIX 34 of FIG.

首先,在绝缘基片10上形成由铝、铝合金、钼、钼-钨合金、铬、钽等金属导电体组成的栅极布线。 First, formed of aluminum, aluminum alloy, molybdenum, a molybdenum on the insulating substrate 10 - a gate wiring conductive metal tungsten alloy, chromium, tantalum and other components. 栅极布线包括横向延伸的扫描信号线或栅极线22、连接在栅极线22末端、接收来自外部扫描信号向栅极线22传送的栅极衬垫24及栅极线22一部分的薄膜晶体管栅极26。 The gate wiring including the scanning signal lines or gate lines 22 extending transversely, connected to the end of the gate lines 22, thin film transistor gate pad receiving a scan signal from an external transmission line 22 to the gate 24 and the portion of the gate line 22 The gate 26. 栅极线22的突出部与后述的像素电极82连接的存储电容器导电体图案64重叠,以形成提高像素电荷保存能力的存储电容器。 The storage capacitor conductor patterns 22 of the protruding portion of the gate line and the pixel electrode 82 to be described later connection 64 overlap to form a storage capacitor to improve the charge retention ability of pixel.

栅极布线22、24、26可以由单一层组成,也可以由双层或三层组成。 The gate wirings 22, 24 may be composed of a single layer, double layer or may be composed of three layers. 当组成两层以上时,优选地,一层由电阻小的物质组成,另外层由与其它物质接触性良好的物质组成,例如,Cr/Al(或Al合金)的双层或Al/Mo的双层。 When the composition of two or more layers, preferably a layer of a low resistance material composition, the additional layer is in contact with other substances with good composition of matter, e.g., bilayer Cr / Al (or Al alloy) or Al / Mo of double. 在本发明的实施例中栅极布线22、24、26由铬组成的下部层和由铝-钕组成的上部层形成。 Examples 22, 24, a lower gate wiring layer consisting of chromium and aluminum in the embodiment of the present invention - an upper layer formed of neodymium.

栅极布线22、24、26及基片10上形成由氮化硅类组成的栅极绝缘层30,栅极24被栅极绝缘层30覆盖。 A gate wiring 30 is formed of a silicon nitride gate insulating layer on the classes 24, 26 and the substrate 10, gate electrode 24 is covered with the gate insulating layer 30.

在栅极绝缘层30上形成由氢化非晶硅类组成的半导体图案40,在半导体图案40上形成掺杂诸如磷这样的n型杂质的非晶硅组成的欧姆接触层55、56。 Forming a hydrogenated amorphous silicon based semiconductor pattern is formed on the gate insulating layer 3040, the ohmic contact layer 55, doped with n-type impurity such as phosphorous is formed on the amorphous silicon semiconductor pattern 40.

在欧姆接触层55、56上分别形成由钼或钼-钨合金、Cr、Al或Al合金、钽(Ta)类导电物质组成的数据布线一部分的薄膜晶体管源极65和漏极66。 Are formed from molybdenum or molybdenum on the ohmic contact layer 55 and 56 - the data wiring tungsten alloy, Cr, Al or an Al alloy, tantalum (Ta) based conductive thin film consisting of a portion of the source of the transistor 65 and the drain electrode 66. 数据布线包括横向形成且与源极65连接的数据线62、连接在数据线62的一末端并接收来自外部图像信号的数据衬垫68及与栅极线22突出部重叠的存储电容器导电体图案64。 Data wiring includes laterally formed and connected to the source electrode 65 of the data line 62, data line connected at one end 62 and receives data from the external image signal pad 68 and the gate line 22 overlapping the storage capacitor portion protruding conductor pattern 64.

数据布线62、64、65、66、68也如同栅极布线22、24、26,可以由单一层形成,也可以由双层或三层形成。 62,64,65,66,68 data wiring as the gate wiring 22, 24 also may be formed from a single layer, may be formed of a double or triple. 当然,形成两层以上时,优选地,一层由电阻小的物质形成,另外层由与其它物质接触性良好的物质组成。 Of course, two or more layers is formed, preferably formed by a layer of low resistance material, additional layers of other materials with good contact material composition.

欧姆接触层55、56起到降低其下部半导体图案40和其上部数据布线62、64、65、66、68接触电阻的作用。 Ohmic contact layers 55 and 56 serves to reduce data wiring 40 and an upper portion of its lower contact resistance 62,64,65,66,68 semiconductor pattern.

虽然未在图中示出,在数据布线62、64、65、66、68和未被数据布线遮挡的半导体图案40上部可以形成由氧化硅或氮化硅等绝缘物质组成的层间绝缘层。 Although not shown in the drawings, the upper portion of the semiconductor pattern data wiring 62,64,65,66,68 and 40 are not blocked data wiring can be formed the interlayer insulating layer is formed of silicon oxide or the like consisting of an insulating nitride.

在栅极绝缘层30上部像素区域以横向形成露出漏极65和存储电容器导电体图案64的具有开口部C1、C2的红、绿、蓝彩色滤色器R、G、B。 In the upper portion of the pixel region 30 of the gate insulating layer 65 exposing the drain electrode is formed transversely to the storage capacitor and the conductor pattern 64 having an opening portion C1, C2 of the red, green, and blue color filters R, G, B. 在数据线62上部一致示出了红、绿、蓝彩色滤色器R、G、B边界,但在数据线62上部相互重叠以遮挡在像素区域泄漏的光,在形成栅极及数据衬垫24、68的衬垫部则未形成。 In the upper portion of the same data line 62 shows the red, green, and blue color filters R, G, B border, but in the upper portion of the data line 62 overlap to shield light leaked each pixel region, forming a gate pad and a data 24,68 pad portion is not formed.

在红、绿、蓝的彩色滤色器81、82、83上部形成由上述方法淀积的a-SiCOH层(低介电绝缘层)组成的保护层70。 Red, green, and blue color filters 82, 83 a-SiCOH forming the upper layer (low dielectric insulating layer) 70 composed of a protective layer deposited by the method described above. 这种保护层70具有与栅极绝缘层30一起露出栅极衬垫24、数据衬垫68、漏极66及存储电容器导电体图案64的接触孔74、78、76、72。 Such a protective layer 70 having a 24, a data pad 68, the drain electrode 66 and the storage capacitor conductor pattern is exposed in the contact hole 64 with the gate pad of the gate insulating layer 30 74,78,76,72. 这时,露出漏极66及存储电容器导电体图案64的接触孔76、72位于彩色滤色器R、G、B开口部C1、C2的内侧,如上所述,在彩色滤色器R、G、B下部附带层间绝缘层时,与层间绝缘层具有相同的图案。 At this time, a contact hole exposing the drain electrode 66 and the storage capacitor conductor pattern (64) located between the color filters 76,72 R, G, B opening portion C1, C2 of the inside, as described above, in the color filters R, G the lower interlayer insulating layer B is included, and the interlayer insulating layer have the same pattern.

在保护层70上形成从薄膜晶体管接收图像信号并与上板电极一起产生电场的像素电极82。 It is formed on the protective layer 70 and the pixel electrodes generate an electric field together with the electrode 82 and the upper plate receives the image signal from the thin film transistor. 像素电极82由ITO或IZO类透明导电物质组成,通过接触孔76与漏极66物理-电连接并接收图像信号。 The pixel electrode 82 of ITO or IZO based transparent conductive substance composed of 66 physical contact with the drain hole 76 - connecting and receiving an image signal. 像素电极82与栅极线22及数据线62重叠提高开口率,但也可以不重叠。 The pixel electrode 82 and the gate line 22 and the data line 62 overlap increase the aperture ratio, but may not overlap. 而且像素电极82通过接触孔72与存储电容器导电体图案64也连接并向导电体图案64传送图像信号。 The pixel electrode 82 and the storage capacitor 72 and the conductor pattern 64 is also connected to the conductor pattern 64 through the contact hole image signal is transmitted. 另外,在栅极衬垫24及数据衬垫68之上通过接触孔74、78形成分别与它们连接的辅助栅极衬垫84及辅助数据衬垫88,它们具有增加衬垫24、68和外部电路装置的粘合性和保护衬垫的作用,但并非必需,适用与否具有选择性。 Further, an auxiliary gate pad 74, 78 and the auxiliary data pad 84 to which they are connected through a contact hole 88 over the gate pad 24 and the data pad 68, and which has an increased outer liner 24,68 the role of the protective liner adhesion and circuit device, but not necessarily, suitable for selective or not.

那么,参照图36a至40b和前面的图34及图35详细说明根据本发明第十实施例的用于液晶显示器的薄膜晶体管阵列基片的制造方法。 Then, referring to FIGS. 36a and 40b to the preceding figures 34 and 35 described in detail the method of manufacturing a thin film transistor array substrate for a liquid crystal display, a tenth embodiment of the present invention.

如图36a至36b所示,用溅射类方法叠层(堆垛)金属类导电体层,用第一掩模光学蚀刻工序进行干蚀刻或湿蚀刻,在基片10上形成包括栅极线22、栅极衬垫24及栅极26的栅极布线。 As shown in FIG. 36a-36b, by a sputtering method class stack (stack) conductive metal layer, dry etching or wet etching using a first optical mask etching step includes forming a gate line on the substrate 10 22, the gate wiring 24 and the gate pad of the gate 26.

然后,如图37a及图37b,利用化学汽相淀积方法分别以 Then, as shown in FIGS. 37a and 37b, using a chemical vapor deposition method, respectively 厚度连续叠层(堆垛)栅极绝缘层30、氢化非晶硅类半导体和掺杂磷类n型杂质的非晶硅,用掩模光学蚀刻工序制作布线图案,对非晶硅层和掺杂的非晶硅层制作布线图案,形成半导体图案40和欧姆接触层50。 Thickness of the continuous laminate (stack) a gate insulating layer 30, the doped hydrogenated amorphous silicon-based semiconductor and the n-type impurity phosphorus type amorphous silicon, an optical mask patterning etching step, a doped amorphous silicon layer and heteroaryl amorphous silicon layer is patterned to form a semiconductor pattern 40 and the ohmic contact layer 50.

接着,如图38a及图38b所示,用溅射等方法以 Next, as shown in Figure 38a and 38b, by sputtering or the like to 厚度淀积金属类导电体层,然后用掩模蚀刻工序制作布线图案,形成包括数据线62、源极65、漏极66、数据衬垫68及存储电容器导电体图案64的数据布线。 The thickness of the conductive metal layer is deposited and then etched with a mask patterning process, comprising forming a data line 62, source electrode 65, drain electrode 66, the pad 68 and the data storage capacitor wiring conductor pattern 64 of the data. 接着,蚀刻未被源极65和漏极66遮挡的欧姆接触层50,露出源极65和漏极66之间的半导体层40,将欧姆接触层55、56分离为两部分。 Next, etching is not a source 65 and a drain ohmic contact layer 66 of the shield 50, semiconductor layer 40 is exposed between the source electrode 65 and drain electrode 66, an ohmic contact layer 55 and 56 separated into two parts. 接着,堆垛(叠层)氮化硅或氧化硅形成层间绝缘层(未示出)。 Subsequently, an interlayer insulating layer (not shown) the stack (stack) silicon nitride or silicon oxide.

然后,形成数据布线62、64、65、66、68和层间绝缘层(未示出)后,如图39a至39b所示,依次涂布包括红、绿、蓝颜料的感光性有机物质,通过光学工序依次形成红、绿、蓝彩色滤色器R、G、B。 Then, the data wiring is formed 62,64,65,66,68 and the interlayer insulating layer (not shown), as shown in FIG. 39a to 39b, in turn comprising a coating of red, green, blue pigments photosensitive organic material, forming red, green, and blue color filters R, G, B successively by the optical step. 这时,在光学工序中形成红、绿、蓝彩色滤色器R、G、B时,也一同形成露出漏极66和存储电容器导电体图案64的开口部C1、C2。 In this case, the optical step is formed in the red, green, and blue color filters R, G, B, the drain electrode 66 is also exposed together form the storage capacitor and the conductor pattern of the opening portion C1 64, C2. 这是因为,以后在保护层70用漏极66和存储电容器导电体图案64形成接触孔时为了良好地形成侧面。 This is because, since in order to satisfactorily formed in the side surface of the protective layer 70 is formed with a drain contact hole 66 and the storage capacitor conductor pattern 64.

接着,如图40a及图40b所示,用基片的上述a-SiCOH层(低介电绝缘层)形成保护层70,用掩模的光学蚀刻工序与栅极绝缘层30一起制作布线图案形成接触孔72、74、76、78。 Next, as shown in FIG. 40a and FIG. 40b, the protective layer 70 is formed above a-SiCOH substrate layer (low-dielectric insulating layer), an optical mask for the etching step and the gate insulating layer 30 is formed is patterned together contact holes 72,74,76,78. 这时,露出漏极66和存储电容器导电体图案64的接触孔76、74位于滤色器R、G、B的开口部内侧。 In this case, the drain electrode 66 and the storage capacitor exposed conductive patterns 76, 74, a contact hole 64 is located filters R, G, B of the inside of the opening portion. 就这样,在本发明中,在滤色器上预先形成开口部C1、C2后,对保护层70制作布线图案形成露出漏极66和存储电容器导电体图案64的接触孔76、74,因此可以良好地形成接触孔76、74的侧面。 Thus, in the present invention, the color filter is formed in advance on the opening portion C1, the C2, protective layer 70 is patterned to expose a contact hole formed in the drain electrode 66 and the storage capacitor conductor patterns 76, 74, 64, can be good form sides 76, 74 of the contact hole.

最后,如图7至图9所示,以 Finally, as shown in FIG. 7 to FIG. 9, in order to 厚度汽相淀积ITO或IZO层,用掩模光学蚀刻工序蚀刻形成像素电极82、辅助栅极衬垫84及辅助数据衬垫88。 The thickness of vapor-deposited ITO or IZO layer, a pixel electrode 82, the auxiliary gate pad 84 and the auxiliary data pad 88 is formed by an optical etching step etching mask.

这种方法如上所述,可以用在5枚掩模的制造方法中,但也可以同样适用在用4枚掩模的用于液晶显示器的薄膜晶体管基片的制造方法上。 This method as described above, may be used in a method of manufacturing a mask 5, but may be equally applicable in the method of manufacturing a thin film transistor substrate 4 with a mask for a liquid crystal display. 对此,参照附图详细说明,但制造方法曾在第十一及第十三实施例中已说明,所以省略其说明。 In this regard, the detailed description with reference to the accompanying drawings, but the manufacturing method has been described in the eleventh and the thirteenth embodiment, description thereof is omitted.

首先,参照图41至图43详细说明根据本发明实施例的用于液晶显示器的薄膜晶体管阵列基片的结构。 First, the configuration of the thin film transistor array substrate for a liquid crystal display according to embodiments of the present invention is described in detail with FIGS. 41 to 43.

图41是根据本发明第十四实施例的用于液晶显示器的薄膜晶体管基片布局图,图42及图43是沿着图41的XXXVI-XXXVI'线及XXXVII-XXXVII'线的薄膜晶体管基片截面图。 FIG 41 is a layout view of a thin film transistor substrate for a liquid crystal display fourteenth embodiment of the present invention, FIG. 42 and FIG. 43 is a XXXVI-XXXVI of FIG. 41 along the thin film transistor group 'and the line XXXVII-XXXVII' line sheet cross-sectional view. 如图41至图42所示,大部分结构与第11实施例的结构相同。 Shown, most of the structure and configuration of the same embodiment 11 in FIG. 41 to FIG. 42.

然而,如同第十三实施例,在薄膜晶体管阵列上部形成露出漏极66及存储电容器导电体图案68的具有开口部C1、C2的红、绿、蓝彩色滤色器R、G、B,在其上部用化学汽相淀积方法形成由a-SiCOH层(低介电绝缘层)组成的保护层70。 However, as in the thirteenth embodiment, it is formed to expose the drain 66 and the storage capacitor conductor pattern 68 having an opening portion C1, C2 of the red, green, and blue color filters R, G, B in the upper portion of the thin film transistor array, in an upper protective layer 70 which is formed by the a-SiCOH layer (low dielectric insulating layer) consisting of chemical vapor deposition method.

本发明除了已提示的实施例之外,可以多种方式适用。 In addition to the embodiment of the present invention it has been suggested, may be applied in various ways. 例如,为了减少重量及提高耐冲击性发明的塑料液晶显示器一样,需要低温工序条件的显示时可以适用本发明。 For example, in order to reduce weight and improve impact resistant plastic liquid crystal display of the invention, as the present invention can be applied when necessary to display a low temperature process conditions. 而且,同样可以适用在利用外部光显示图像的用于反射型液晶显示器的薄膜晶体管基片上。 Further, the same can apply in the external thin film transistor substrate for a reflective type liquid crystal display image display light.

而且,栅极绝缘层考虑与非晶硅层组成的半导体层40的界面特性应保持致密的膜质。 Further, the gate insulating layer and the amorphous silicon layer interface characteristics to consider the composition of the semiconductor layer 40 should maintain a dense film quality. 然而,膜质越紧密汽相淀积速度越慢,导致工序的延长。 However, the closer the film quality slower vapor deposition, results in a prolonged process. 另外,从半导体40相邻的面约有 Further, adjacent the semiconductor surface is about 40 左右厚度为致密层,就不影响薄膜晶体管的工作。 A thickness of about dense layer, does not affect the thin film transistor. 因此,若在本发明的实施例中在栅极绝缘层下部形成汽相淀积速度快的本发明的低介电绝缘层,栅极绝缘层上部形成膜质致密的氮化硅层,那么可以不降低薄膜晶体管的功能的同时缩短工序时间。 Accordingly, if the formation of a low dielectric insulating layer according to the present invention has a high vapor deposition rate at the lower gate insulating layer in the embodiment of the present invention, the upper gate insulating layer forming a dense film quality of the silicon nitride layer, it can be a thin film transistor without decreasing function while shortening the process time.

如上所述,本发明中使用硅烷气体汽相淀积a-SiCOH层(低电容绝缘层)并形成保护层。 As described above, the present invention is a vapor deposition using a silane gas a-SiCOH layer (a low capacitance insulating layer) and a protective layer. 由此保持绝缘层物理性质的同时可以大为改善汽相淀积速度。 Thus while maintaining the physical properties of the insulating layer may be substantially improved vapor deposition speed. 因此,解决了寄生电容的问题,可以获得高开口率结构,并且可以缩短工序时间。 Thus, to solve the problem of the parasitic capacitance, a high aperture ratio structure, and can shorten the process time.

Claims (85)

1.一种半导体装置,所述半导体装置包括:在绝缘基片上的第一绝缘层、第二绝缘层、缓冲层、栅极绝缘层、和保护层图案中至少一层,其中所述第一绝缘层、所述第二绝缘层、所述缓冲层、所述栅极绝缘层、和所述保护层图案中至少一层是通过加入硅烷气体SiH 4到主源气体中用CVD或PECVD法进行汽相淀积的低介电绝缘层,其中所述低介电绝缘层是通过将包括主源气体、硅烷SiH 4 、和氧化剂的反应气体混合物提供给包括基片的汽相淀积室用CVD法或PECVD法汽相淀积的a-SiCOH薄膜。 1. A semiconductor device, said semiconductor device comprising: a first insulating layer on the insulating substrate, a second insulating layer, a buffer layer, a gate insulating layer, and the protective layer is at least one pattern, wherein the first insulating layer, the second insulating layer, the buffer layer, the gate insulating layer, and the protective layer pattern is at least one of SiH 4 by addition of silane gas to the main gas source CVD or PECVD method using low dielectric insulating layer of vapor-deposited, wherein the low-dielectric insulating layer is provided to the vapor deposition chamber includes a substrate by including a main source gas, a reaction gas mixture of silane SiH 4, and an oxidizing agent by CVD method or a PECVD method a-SiCOH film vapor-deposited.
2.根据权利要求1所述的半导体装置,其中所述a-SiCOH薄膜具有3.6以下的介电常数,并且在400-800nm的波长范围内具有95%以上的光透射比。 The semiconductor device according to claim 1, wherein said a-SiCOH film having a dielectric constant of 3.6 or less and 95% or more light transmittance in the wavelength range of 400-800nm.
3.根据权利要求1所述的半导体装置,其中所述基片选自由液晶显示器、发光二极管显示器、和有机发光二极管显示器组成的组。 The semiconductor device according to claim 1, wherein said substrate is selected from the group consisting of a liquid crystal display, the light-emitting diode display, and an organic light emitting diode display thereof.
4.根据权利要求1所述的半导体装置,其中所述硅烷气体SiH 4与主源气体的比率是1:0.5到1:1。 4. The semiconductor device according to claim 1, wherein the silane gas ratio of SiH 4 gas is the main source of 1: 0.5 to 1: 1.
5.根据权利要求1所述的半导体装置,其中所述主源气体选自由以下化学式1、化学式2、和化学式3表示的有机硅组成的组中的一种或多种: The semiconductor device according to claim 1, wherein said primary gas source selected from the group consisting of the following Chemical Formula 1, Chemical Formula 2, and a silicone group represented by Chemical Formula 3 consisting of one or more of:
[化学式1] [Chemical Formula 1]
SiH x (CH 3 ) 4-x SiH x (CH 3) 4- x
其中,x为整数,即0、1、2、或4; Wherein, x is an integer, i.e. 1, 2, or 4;
[化学式2] [Chemical Formula 2]
Si(OR 1 ) x R 2 4-x Si (OR 1) x R 2 4-x
其中,R 1及R 2独立地是被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基,而x为0-4的整数; Wherein, R 1 and R 2 are independently a C1-10 alkyl or alkenyl group C1-5 alkyl or alkenyl group substituted or unsubstituted straight-chain or branched, and x is an integer from 0 to 4 ;
[化学式3] [Chemical Formula 3]
环-(SiR 1 R 2 -O) n Ring - (SiR 1 R 2 -O) n
R 1及R 2独立地是氢或被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基。 R 1 and R 2 are independently hydrogen or C1-5 alkyl or alkenyl group substituted or unsubstituted C1-10 alkyl or alkenyl group, linear or branched.
6.根据权利要求5所述的半导体装置,其中所述[化学式2]中R 1及R 2独立地是甲基、乙基、丙基、或乙烯基。 6. The semiconductor device according to claim 5, wherein said [Chemical Formula 2] R 1 and R 2 are independently methyl, ethyl, propyl, or vinyl.
7.根据权利要求5所述的半导体装置,其中所述[化学式3]中R 1及R 2独立地是氢、甲基、乙基、丙基、或乙烯基。 The semiconductor device according to claim 5, wherein said [Chemical Formula 3] R 1 and R 2 are independently hydrogen, methyl, ethyl, propyl, or vinyl.
8.根据权利要求1所述的半导体装置,其中所述氧化剂选自由 The semiconductor device according to claim 1, wherein said oxidizing agent selected from the group consisting of
O 2 、N 2 O、NO、CO 2 、CO、臭氧、及其混合物组成的组。 O 2, N 2 O, NO , CO 2, CO, ozone, and mixtures thereof.
9.根据权利要求1所述的半导体装置,其中所述低介电绝缘层在1-10,000 Torr的压力和25-300℃的温度下,通过以0.2-1.5mW/cm 2的功率密度将反应气体混合物暴露给等离子体用PECVD法进行汽相淀积。 The semiconductor device according to claim 1, wherein the low-dielectric insulating layer at a pressure of 1-10,000 Torr and a temperature of 25-300 deg.] C, the power density by 0.2-1.5mW / cm 2 of the reaction the gas mixture is exposed to the plasma vapor phase deposition by PECVD.
10.一种半导体装置,所述半导体装置包括绝缘基片、第一绝缘层、薄膜晶体管、第二绝缘层、及像素电极,其中所述第一绝缘层及所述第二绝缘层中至少一层是通过加入硅烷气体SiH 4用CVD或PECVD法进行汽相淀积的低介电绝缘层,其中所述低介电绝缘层是通过将包括主源气体、硅烷SiH 4 、和氧化剂的反应气体混合物提供给包括基片的汽相淀积室用CVD法或PECVD法汽相淀积的a-SiCOH薄膜。 A semiconductor device, said semiconductor device comprising an insulating substrate, a first insulating layer, a thin film transistor, a second insulating layer, and a pixel electrode, wherein the first insulating layer and the second insulating layer at least one layer is a low-dielectric insulating layer of vapor-deposited by the addition of silane SiH 4 gas by the CVD or PECVD process, wherein the low dielectric insulating layer by the reaction gas include a main source gas, silane SiH 4, and an oxidizing agent the mixture is supplied to the vapor deposition chamber comprising a substrate a-SiCOH film by CVD or vapor deposition PECVD method.
11.根据权利要求10所述的半导体装置,其中所述a-SiCOH薄膜的具有3.6以下的介电常数,并且在400-800nm的波长范围内具有95%以上的光透射比。 11. The semiconductor device according to claim 10, wherein said a-SiCOH film having a dielectric constant of 3.6 or less and 95% or more light transmittance in the wavelength range of 400-800nm.
12.根据权利要求10所述的半导体装置,其中所述基片选自由液晶显示器、发光二极管显示器、和有机发光二极管显示器组成的组。 12. The semiconductor device according to the group according to claim 10, wherein said substrate is selected from the group consisting of a liquid crystal display, light emitting diode display, and an organic light emitting diode display thereof.
13.根据权利要求10所述的半导体装置,其中所述硅烷气体SiH 4与所述主源气体的比率是1:0.5到1:1。 The semiconductor device according to claim 10, wherein the silane gas ratio of SiH 4 gas and the main source is 1: 0.5 to 1: 1.
14.根据权利要求10所述的半导体装置,其中所述主源气体选自由以下化学式1、化学式2、和化学式3表示的有机硅组成的组中的一种或多种: 14. The semiconductor device according to claim 10, wherein said primary gas source selected from the group consisting of the following chemical formula 1, chemical formula, and a silicone group represented by Chemical Formula 3 consisting of one or more 2:
[化学式1] [Chemical Formula 1]
SiH x (CH 3 ) 4-x SiH x (CH 3) 4- x
其中,x为整数,即0、1、2、或4; Wherein, x is an integer, i.e. 1, 2, or 4;
[化学式2] [Chemical Formula 2]
Si(OR 1 ) x R 2 4-x Si (OR 1) x R 2 4-x
其中,R 1及R 2独立地是被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基,而x为0-4的整数; Wherein, R 1 and R 2 are independently a C1-10 alkyl or alkenyl group C1-5 alkyl or alkenyl group substituted or unsubstituted straight-chain or branched, and x is an integer from 0 to 4 ;
[化学式3] [Chemical Formula 3]
环-(SiR 1 R 2 -O) n Ring - (SiR 1 R 2 -O) n
R 1及R 2独立地是氢或被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基。 R 1 and R 2 are independently hydrogen or C1-5 alkyl or alkenyl group substituted or unsubstituted C1-10 alkyl or alkenyl group, linear or branched.
15.根据权利要求14所述的半导体装置,其中所述[化学式2]中R 1及R 2独立地是甲基、乙基、丙基、或乙烯基。 The semiconductor device according to claim 14, wherein said [Chemical Formula 2] R 1 and R 2 are independently methyl, ethyl, propyl, or vinyl.
16.根据权利要求14所述的半导体装置,其中所述[化学式3]中R 1及R 2独立地是氢、甲基、乙基、丙基、或乙烯基。 The semiconductor device according to claim 14, wherein said [Chemical Formula 3] R 1 and R 2 are independently hydrogen, methyl, ethyl, propyl, or vinyl.
17.根据权利要求10所述的半导体装置,其中所述氧化剂选自由O 2 、N 2 O、NO、CO 2 、CO、臭氧、及其混合物组成的组。 17. The semiconductor device group as claimed in claim 10, wherein said oxidizing agent selected from the group consisting of O 2, N 2 O, NO , CO 2, CO, ozone, and mixtures thereof.
18.根据权利要求10所述的半导体装置,其中所述低介电绝缘层在1-10,000 Torr的压力和25-300℃的温度下,通过以0.2-1.5mW/cm 2的功率密度将反应气体混合物暴露给等离子体用PECVD法进行汽相淀积。 18. The semiconductor device according to claim 10, wherein the low-dielectric insulating layer at a pressure of 1-10,000 Torr and a temperature of 25-300 deg.] C, the power density by 0.2-1.5mW / cm 2 of the reaction the gas mixture is exposed to the plasma vapor phase deposition by PECVD.
19.一种半导体装置,所述半导体装置包括:绝缘基片、数据布线、滤色器、缓冲层、栅极布线、栅极绝缘层、半导体层、及像素布线,其中所述缓冲层和所述栅极绝缘层中至少一层是通过加入硅烷气体SiH 4用CVD或PECVD法进行汽相淀积的低介电绝缘层,其中所述低介电绝缘层是通过将包括主源气体、硅烷SiH 4 、和氧化剂的反应气体混合物提供给包括基片的汽相淀积室用CVD法或PECVD法汽相淀积的a-SiCOH薄膜。 19. A semiconductor device, said semiconductor device comprising: an insulating substrate, a data wiring, a color filter, a buffer layer, a gate wiring, a gate insulating layer, a semiconductor layer, and a pixel line, wherein the buffer layer and the said at least one layer of a low dielectric insulating layer of vapor-deposited gate insulating layer by adding silane gas SiH 4 by the CVD or PECVD process, wherein the low-dielectric insulating layer is formed by including a main source gas, silane the reaction gas mixture SiH 4, and an oxidant supplied to the vapor deposition chamber comprising a substrate a-SiCOH film by CVD or vapor deposition PECVD method.
20.根据权利要求19所述的半导体装置,其中所述a-SiCOH薄膜具有3.6以下的介电常数,并且在400-800nm的波长范围内具有95%以上的光透射比。 20. The semiconductor device according to claim 19, wherein said a-SiCOH film having a dielectric constant of 3.6 or less and 95% or more light transmittance in the wavelength range of 400-800nm.
21.根据权利要求19所述的半导体装置,其中所述基片选自由液晶显示器、发光二极管显示器、和有机发光二极管显示器组成的组。 21. The semiconductor device group as claimed in claim 19, wherein said substrate is selected from the group consisting of a liquid crystal display, light emitting diode display, and an organic light emitting diode display thereof.
22.根据权利要求19所述的半导体装置,其中所述硅烷气体SiH 4与所述主源气体的比率是1:0.5到1:1。 22. The semiconductor device according to claim 19, wherein the silane gas ratio of SiH 4 gas and the main source is 1: 0.5 to 1: 1.
23.根据权利要求19所述的半导体装置,其中所述主源气体选自由以下化学式1、化学式2、和化学式3表示的有机硅组成的组中的一种或多种: 23. The semiconductor device according to claim 19, wherein said primary gas source selected from the group consisting of one or more of the following chemical formula, chemical formula, and a silicone group represented by the formula 3 12 consisting of:
[化学式1] [Chemical Formula 1]
SiH x (CH 3 ) 4-x SiH x (CH 3) 4- x
其中,x为整数,即0、1、2、或4; Wherein, x is an integer, i.e. 1, 2, or 4;
[化学式2] [Chemical Formula 2]
Si(OR 1 ) x R 2 4-x Si (OR 1) x R 2 4-x
其中,R 1及R 2独立地是被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基,而x为0-4的整数; Wherein, R 1 and R 2 are independently a C1-10 alkyl or alkenyl group C1-5 alkyl or alkenyl group substituted or unsubstituted straight-chain or branched, and x is an integer from 0 to 4 ;
[化学式3] [Chemical Formula 3]
环-(SiR 1 R 2 -O) n Ring - (SiR 1 R 2 -O) n
R 1及R 2独立地是氢或被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基。 R 1 and R 2 are independently hydrogen or C1-5 alkyl or alkenyl group substituted or unsubstituted C1-10 alkyl or alkenyl group, linear or branched.
24.根据权利要求23所述的半导体装置,其中所述[化学式2]中R 1及R 2独立地是甲基、乙基、丙基、或乙烯基。 24. The semiconductor device according to claim 23, wherein said [Chemical Formula 2] R 1 and R 2 are independently methyl, ethyl, propyl, or vinyl.
25.根据权利要求23所述的半导体装置,其中所述[化学式3]中R 1及R 2独立地是氢、甲基、乙基、丙基、或乙烯基。 25. The semiconductor device according to claim 23, wherein said [Chemical Formula 3] R 1 and R 2 are independently hydrogen, methyl, ethyl, propyl, or vinyl.
26.根据权利要求19所述的半导体装置,其中所述氧化剂选自由O 2 、N 2 O、NO、CO 2 、CO、臭氧、及其混合物组成的组。 26. The semiconductor device group as claimed in claim 19, wherein said oxidizing agent selected from the group consisting of O 2, N 2 O, NO , CO 2, CO, ozone, and mixtures thereof.
27.根据权利要求19所述的半导体装置,其中所述低介电绝缘层在1-10,000 Torr的压力和25-300℃的温度下,通过以0.2-1.5mW/cm 2的功率密度将反应气体混合物暴露给等离子体用PECVD法进行汽相淀积。 27. The semiconductor device according to claim 19, wherein the low-dielectric insulating layer at a pressure of 1-10,000 Torr and a temperature of 25-300 deg.] C, the power density by 0.2-1.5mW / cm 2 of the reaction the gas mixture is exposed to the plasma vapor phase deposition by PECVD.
28.一种半导体装置,所述半导体装置包括:绝缘基片、栅极线、栅极布线、栅极绝缘层、半导体层图案、接触层图案、数据布线、保护层图案、及透明电极层图案,其中所述栅极绝缘层及所述保护层中至少一层是通过加入硅烷气体SiH 4用CVD或PECVD法进行汽相淀积的低介电绝缘层,其中所述低介电绝缘层是通过将包括主源气体、硅烷SiH 4 、和氧化剂的反应混合物提供给包括基片的汽相淀积室用CVD法或PECVD法汽相淀积的a-SiCOH薄膜。 28. A semiconductor device, said semiconductor device comprising: an insulating substrate, a gate line, a gate wiring, a gate insulating layer, a semiconductor layer pattern, a contact layer pattern, data wiring, a protective layer pattern, and the transparent electrode layer pattern wherein the gate insulating layer and the protective layer is carried out by addition of at least one of a silane gas SiH 4 by the CVD or PECVD process low-dielectric insulating layer of vapor-deposited, wherein the low-dielectric insulating layer is is supplied to the vapor deposition chamber comprising a substrate a-SiCOH film by CVD or a PECVD method by vapor deposition including a main source gas 4, the oxidizing agent and the reaction mixture is a silane SiH.
29.根据权利要求28所述的半导体装置,其中所述a-SiCOH薄膜的具有3.6以下的介电常数,并且在400-800nm的波长范围内具有95%以上的光透射比。 29. The semiconductor device according to claim 28, wherein said a-SiCOH film having a dielectric constant of 3.6 or less and 95% or more light transmittance in the wavelength range of 400-800nm.
30.根据权利要求28所述的半导体装置,其中所述基片选自由液晶显示器、发光二极管显示器、和有机发光二极管显示器组成的组。 30. The semiconductor device according to claim 28, wherein said substrate is selected from the group consisting of a liquid crystal display, the light-emitting diode display, and an organic light emitting diode display thereof.
31.根据权利要求28所述的半导体装置,其中所述硅烷气体SiH 4与所述主源气体的比率是1:0.5到1:1。 31. The semiconductor device according to claim 28, wherein the silane gas ratio of SiH 4 gas and the main source is 1: 0.5 to 1: 1.
32.根据权利要求28所述的半导体装置,其中所述主源气体选自由以下化学式1、化学式2、和化学式3表示的有机硅组成的组中的一种或多种: 32. The semiconductor device according to claim 28, wherein said primary gas source selected from the group consisting of the following Chemical Formula 1, Chemical Formula 2, and a silicone group represented by Chemical Formula 3 consisting of one or more of:
[化学式1] [Chemical Formula 1]
SiH x (CH 3 ) 4-x SiH x (CH 3) 4- x
其中,x为整数,即0、1、2、或4; Wherein, x is an integer, i.e. 1, 2, or 4;
[化学式2] [Chemical Formula 2]
Si(OR 1 ) x R 2 4-x Si (OR 1) x R 2 4-x
其中,R 1及R 2独立地是被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基,而x为0-4的整数; Wherein, R 1 and R 2 are independently a C1-10 alkyl or alkenyl group C1-5 alkyl or alkenyl group substituted or unsubstituted straight-chain or branched, and x is an integer from 0 to 4 ;
[化学式3] [Chemical Formula 3]
环-(SiR 1 R 2 -O) n Ring - (SiR 1 R 2 -O) n
R 1及R 2独立地是氢或被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基。 R 1 and R 2 are independently hydrogen or C1-5 alkyl or alkenyl group substituted or unsubstituted C1-10 alkyl or alkenyl group, linear or branched.
33.根据权利要求32所述的半导体装置,其中所述[化学式2]中R 1及R 2独立地是甲基、乙基、丙基、或乙烯基。 33. The semiconductor device according to claim 32, wherein said [Chemical Formula 2] R 1 and R 2 are independently methyl, ethyl, propyl, or vinyl.
34.根据权利要求32所述的半导体装置,其中所述[化学式3]中R 1及R 2独立地是氢、甲基、乙基、丙基、或乙烯基。 34. The semiconductor device according to claim 32, wherein said [Chemical Formula 3] R 1 and R 2 are independently hydrogen, methyl, ethyl, propyl, or vinyl.
35.根据权利要求28所述的半导体装置,其中所述氧化剂选自由O 2 、N 2 O、NO、CO 2 、CO、臭氧、及其混合物组成的组。 35. The semiconductor device according to claim 28, wherein said oxidizing agent is selected from the group consisting of O 2, N 2 O, NO , CO 2, CO, ozone, and mixtures thereof.
36.根据权利要求28所述的半导体装置,其中所述低介电绝缘层在1-10,000 Torr的压力和25-300℃的温度下,通过以0.2-1.5mW/cm 2的功率密度将反应气体混合物暴露给等离子体用PECVD法进行汽相淀积。 36. The semiconductor device according to claim 28, wherein the low-dielectric insulating layer at a pressure of 1-10,000 Torr and a temperature of 25-300 deg.] C, the power density by 0.2-1.5mW / cm 2 of the reaction the gas mixture is exposed to the plasma vapor phase deposition by PECVD.
37.一种薄膜晶体管基片,所述薄膜晶体管基片包括: 37. A thin film transistor substrate, a thin film transistor substrate comprising:
绝缘基片; An insulating substrate;
第一信号线,形成在所述绝缘基片上; A first signal line formed on said insulating substrate;
第一绝缘层,形成在所述第一信号线上; A first insulating layer formed on said first signal line;
第二信号线,形成在所述第一绝缘层上且与所述第一信号线交叉; A second signal line, and is formed intersecting the first signal line on the first insulating layer;
薄膜晶体管,与所述第一信号线及所述第二信号线连接; The thin film transistor connected to the first signal line and the second signal line;
第二绝缘层,是低介电绝缘层,所述第二绝缘层形成在所述薄膜晶体管上且具有用于露出所述薄膜晶体管的规定电极的第一接触孔;以及 A second insulating layer, a low dielectric insulating layer, said second insulating layer and having a first contact hole for exposing a predetermined electrode of the thin film transistor on the thin film transistor; and
第一像素电极,形成在所述第二绝缘层上且通过所述第一接触孔与所述薄膜晶体管的规定电极连接, A first pixel electrode, and is formed by connecting predetermined electrodes of the first contact hole of the thin film transistor on the second insulating layer,
其中所述低介电绝缘层是通过在所述薄膜晶体管上加入包括主源气体、硅烷SiH 4 、和氧化剂的反应气体混合物用CVD法或PECVD法汽相淀积的a-SiCOH薄膜。 Wherein the low-dielectric insulating layer is a-SiCOH films by adding the reaction gas comprises a main source gas, silane SiH 4, and oxidant mixture in the thin film transistor by CVD or vapor deposition PECVD method.
38.根据权利要求37所述的薄膜晶体管基片,其中所述硅烷气体SiH 4与所述主源气体的比率是1:0.5到1:1。 38. The thin film transistor substrate according to claim 37, wherein the silane gas ratio of SiH 4 gas and the main source is 1: 0.5 to 1: 1.
39.根据权利要求37所述的薄膜晶体管基片,其中所述主源气体选自由以下化学式1、化学式2、和化学式3表示的有机硅组成的组中的一种或多种: 39. The thin film transistor substrate according to claim 37, wherein said primary gas source selected from the group consisting of the following chemical formula 1, chemical formula, and a silicone group represented by Chemical Formula 3 consisting of one or more 2:
[化学式1] [Chemical Formula 1]
SiH x (CH 3 ) 4-x SiH x (CH 3) 4- x
其中,x为整数,即0、1、2、或4; Wherein, x is an integer, i.e. 1, 2, or 4;
[化学式2] [Chemical Formula 2]
Si(OR 1 ) x R 2 4-x Si (OR 1) x R 2 4-x
其中,R 1及R 2独立地是被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基,而x为0-4的整数; Wherein, R 1 and R 2 are independently a C1-10 alkyl or alkenyl group C1-5 alkyl or alkenyl group substituted or unsubstituted straight-chain or branched, and x is an integer from 0 to 4 ;
[化学式3] [Chemical Formula 3]
环-(SiR 1 R 2 -O) n Ring - (SiR 1 R 2 -O) n
R 1及R 2独立地是氢或被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基。 R 1 and R 2 are independently hydrogen or C1-5 alkyl or alkenyl group substituted or unsubstituted C1-10 alkyl or alkenyl group, linear or branched.
40.根据权利要求39所述的薄膜晶体管基片,其中所述[化学式2]中R 1及R 2独立地是甲基、乙基、丙基、或乙烯基。 40. The thin film transistor substrate according to claim 39, wherein said [Chemical Formula 2] R 1 and R 2 are independently methyl, ethyl, propyl, or vinyl.
41.根据权利要求39所述的薄膜晶体管基片,其中所述[化学式3]中R 1及R 2独立地是氢、甲基、乙基、丙基、或乙烯基。 41. The thin film transistor substrate according to claim 39, wherein said [Chemical Formula 3] R 1 and R 2 are independently hydrogen, methyl, ethyl, propyl, or vinyl.
42.根据权利要求37所述的薄膜晶体管基片,其中所述氧化剂选自由O 2 、N 2 O、NO、CO 2 、CO、臭氧、及其混合物组成的组。 42. The thin film transistor substrate according to claim 37, wherein said oxidizing agent is selected from the group consisting of O 2, N 2 O, NO , CO 2, CO, ozone, and mixtures thereof.
43.根据权利要求37所述的薄膜晶体管基片,其中所述低介电绝缘层在1-10,000 Torr的压力和25-300℃的温度下,通过以0.2-1.5mW/cm 2的功率密度将反应气体混合物暴露给等离子体用PECVD法进行汽相淀积。 43. The thin film transistor substrate according to claim 37, wherein the low-dielectric insulating layer at a pressure of 1-10,000 Torr and a temperature of 25-300 deg.] C, the power density by 0.2-1.5mW / cm 2 of the reaction gas mixture is exposed to the plasma vapor phase deposition by PECVD.
44.根据权利要求37所述的薄膜晶体管基片,其中所述低介电绝缘层具有2-3的介电常数。 44. The thin film transistor substrate according to claim 37, wherein the low-dielectric insulating layer has a dielectric constant of 2-3.
45.根据权利要求37所述的薄膜晶体管基片,其中所述第一绝缘层包括由低介电绝缘层组成的下部层以及由氮化硅组成的上部层。 45. The thin film transistor substrate according to claim 37, wherein said first insulating layer comprises a lower layer made of a low dielectric insulating layers and an upper layer composed of silicon nitride.
46.根据权利要求37所述的薄膜晶体管基片,其中所述像素电极由反射光的不透明导电物质或透明导电物质组成。 46. ​​The thin film transistor substrate according to claim 37, wherein said conductive substance by an opaque pixel electrode or a transparent conductive material composed of the reflected light.
47.根据权利要求37所述的薄膜晶体管基片,其中所述第二绝缘层在其表面上具有不均匀的图案。 47. The thin film transistor substrate according to claim 37, wherein said second insulating layer has an uneven pattern on the surface thereof.
48.一种薄膜晶体管基片,所述薄膜晶体管基片包括: 48. A thin film transistor substrate, a thin film transistor substrate comprising:
数据布线,包括形成在绝缘基片上的数据线; Data wiring includes a data line formed on an insulating substrate;
红、绿、和蓝滤色器,形成在所述绝缘基片上; Red, green, and blue color filters are formed on said insulating substrate;
缓冲层,是低介电绝缘层,所述缓冲层形成在所述数据布线和所述滤色器上,且具有用于露出所述数据布线的规定部分的第一接触孔; The buffer layer, a low dielectric insulating layer, the buffer layer is formed on the data wiring and the color filter, and having a first contact hole for exposing a predetermined portion of the wiring of the data;
栅极布线,在所述缓冲层上形成且包括与所述数据线交叉以限定像素的栅极线、及与所述栅极线连接的栅极; A gate wiring formed on said buffer layer and comprising a data line crossing the gate line to define a pixel gate, and connected to the gate line;
栅极绝缘层,形成在所述栅极布线上且具有用于至少露出所述第一接触孔一部分的第二接触孔; A gate insulating layer formed on the gate line and having a second contact hole for exposing at least a portion of the first contact hole;
半导体层,形成在所述栅极绝缘层的区域上,所述栅极绝缘层形成在所述栅极上;以及 A semiconductor layer formed on a region of the gate insulating layer, the gate insulating layer is formed on the gate electrode; and
像素布线,包括通过所述第一接触孔及所述第二接触孔与所述数据线连接且至少一部分与所述半导体层连接的源极、在所述半导体层上与所述源极相对形成的漏极、及与所述漏极连接的像素电极, Pixel line, comprising a connection via the first contact hole and the second contact hole and at least part of the data line connected to the semiconductor layer, source electrode, on the semiconductor layer and the source electrode is formed opposite a drain, and a pixel electrode connected to the drain,
其中所述缓冲层是通过在所述滤色器上加入包括主源气体、硅烷SiH 4 、和氧化剂的反应气体混合物用CVD法或PECVD法汽相淀积的a-SiCOH薄膜。 Wherein the buffer layer comprises a reaction gas is accomplished by adding a main source gas, silane SiH 4, a mixture of oxidant and a-SiCOH film by a CVD method or a PECVD method of vapor-deposited on the color filter.
49.根据权利要求48所述的薄膜晶体管基片,其中所述硅烷气体SiH 4与主源气体的比率是1:0.5到1:1。 49. The thin film transistor substrate according to claim 48, wherein the silane gas ratio of SiH 4 gas is the main source of 1: 0.5 to 1: 1.
50.根据权利要求48所述的薄膜晶体管基片,其中所述主源气体选自由以下化学式1、化学式2、和化学式3表示的有机硅组成的组中的一种或多种: 50. The thin film transistor substrate according to claim 48, wherein said primary gas source selected from the group consisting of the following chemical formula 1, chemical formula, and a silicone group represented by Chemical Formula 3 consisting of one or more 2:
[化学式1] [Chemical Formula 1]
SiH x (CH 3 ) 4-x SiH x (CH 3) 4- x
其中,x为整数,即0、1、2、或4; Wherein, x is an integer, i.e. 1, 2, or 4;
[化学式2] [Chemical Formula 2]
Si(OR 1 ) x R 2 4-x Si (OR 1) x R 2 4-x
其中,R 1及R 2独立地是被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基,而x为0-4的整数; Wherein, R 1 and R 2 are independently a C1-10 alkyl or alkenyl group C1-5 alkyl or alkenyl group substituted or unsubstituted straight-chain or branched, and x is an integer from 0 to 4 ;
[化学式3] [Chemical Formula 3]
环-(SiR 1 R 2 -O) n Ring - (SiR 1 R 2 -O) n
R 1及R 2独立地是氢或被C1-5烷基或烯基取代或未被取代的直链或支链的C1-10烷基或烯基。 R 1 and R 2 are independently hydrogen or C1-5 alkyl or alkenyl group substituted or unsubstituted C1-10 alkyl or alkenyl group, linear or branched.
51.根据权利要求50所述的薄膜晶体管基片,其中所述[化学式2]中R 1及R 2独立地是甲基、乙基、丙基、或乙烯基。 51. The thin film transistor substrate according to claim 50, wherein said [Chemical Formula 2] R 1 and R 2 are independently methyl, ethyl, propyl, or vinyl.
52.根据权利要求50所述的薄膜晶体管基片,其中所述[化学式3]中R 1及R 2独立地是氢、甲基、乙基、丙基、或乙烯基。 52. The thin film transistor substrate according to claim 50, wherein said [Chemical Formula 3] R 1 and R 2 are independently hydrogen, methyl, ethyl, propyl, or vinyl.
53.根据权利要求48所述的薄膜晶体管基片,其中所述氧化剂选自由O 2 、N 2 O、NO、CO 2 、CO、臭氧、及其混合物组成的组。 53. The thin film transistor substrate according to claim 48, wherein said oxidizing agent is selected from the group consisting of O 2, N 2 O, NO , CO 2, CO, ozone, and mixtures thereof.
54.根据权利要求48所述的薄膜晶体管基片,其中所述低介电绝缘层在1-10,000 Torr的压力和25-300℃的温度下,通过以0.2-1.5mW/cm 2的功率密度将反应气体混合物暴露给等离子体用PECVD法进行汽相淀积。 54. The thin film transistor substrate according to claim 48, wherein the low-dielectric insulating layer at a pressure of 1-10,000 Torr and a temperature of 25-300 deg.] C, the power density by 0.2-1.5mW / cm 2 of the reaction gas mixture is exposed to the plasma vapor phase deposition by PECVD.
55.根据权利要求48所述的薄膜晶体管基片,其中所述缓冲层具有2-3的介电常数。 55. The thin film transistor substrate according to claim 48, wherein the buffer layer has a dielectric constant of 2-3.
56.根据权利要求48所述的薄膜晶体管基片,其中所述半导体图案由第一非晶硅层和具有比所述第一非晶硅层带隙小的第二非晶硅层的双层结构形成。 56. The thin film transistor substrate according to claim 48, wherein the semiconductor pattern and the first amorphous silicon layer having a double layer is smaller than the first band gap amorphous silicon of the second amorphous silicon layer structure is formed.
57.根据权利要求48所述的薄膜晶体管基片,进一步包括光遮挡部,在与所述数据线相同的层上形成,并由与所述数据线相同的物质形成,且位于对应所述半导体层图案的区域。 57. The thin film transistor substrate according to claim 48, further comprising a light shielding portion on the same data line layer is formed by the same material as the data lines are formed, and the semiconductor position corresponding region layer pattern.
58.根据权利要求48所述的薄膜晶体管基片,其中所述光遮挡部向所述栅极线方向延伸。 58. The thin film transistor substrate according to claim 48, wherein said light shielding portion extending to the gate line direction.
59.一种用于液晶显示器的薄膜晶体管基片,其包括: 59. A liquid crystal display thin film transistor substrate, comprising:
绝缘基片; An insulating substrate;
栅极布线,形成在所述基片上且包括栅极线、栅极、及栅极衬垫; A gate wiring formed on said substrate and including a gate line, a gate, and a gate pad;
栅极绝缘层,形成在所述栅极布线上且具有用于至少露出所述栅极衬垫的接触孔; A gate insulating layer formed on the gate line and having at least a contact hole for exposing the gate pad;
半导体层图案,形成在所述栅极绝缘层上; The semiconductor layer pattern is formed on the gate insulating layer;
接触层图案,形成在所述半导体层图案上; Contact layer pattern is formed on the semiconductor layer pattern;
数据布线,形成在所述接触层图案上,所述数据布线具有与所述接触层图案基本相同的形态且包括源极、漏极、数据线、和数据衬垫; Data wiring, is formed on the contact layer pattern, the data wiring layer having the contact pattern substantially the same shape and includes a source, a drain, a data line, and the data pad;
保护层图案,形成在所述数据布线上,所述保护层具有用于露出所述栅极衬垫、所述数据衬垫、及所述漏极的接触孔,且由低介电绝缘层组成;以及 The protective layer pattern is formed on the data wiring, for exposing the gate pad, a data pad, a contact hole and the drain layer having the protection, and low-dielectric insulating layers ;as well as
透明电极层图案,与露出的所述栅极衬垫、所述数据衬垫、及所述漏极电连接, Patterning the transparent electrode layer, and the exposed gate pad, a data pad, and the drain is electrically connected,
其中所述低介电绝缘层是通过在所述数据布线上加入包括主源气体、硅烷SiH 4 、和氧化剂的反应气体混合物用CVD法或PECVD法汽相淀积的a-SiCOH薄膜。 Wherein the low dielectric insulating layer by adding a reaction gas comprising a main source gas, silane SiH 4, a mixture of oxidant and a-SiCOH film by a CVD method or a PECVD method of vapor-deposited on the data wiring.
60.根据权利要求59所述的薄膜晶体管基片,其中所述硅烷气体SiH 4与主源气体的比率是1:0.5到1:1。 60. The thin film transistor substrate according to claim 59, wherein the silane gas ratio of SiH 4 gas is the main source of 1: 0.5 to 1: 1.
61.根据权利要求59所述的薄膜晶体管基片,其中所述主源气体选自由以下化学式1、化学式2、和化学式3表示的有机硅组成的组中的一种或多种: 61. The thin film transistor substrate according to claim 59, wherein said primary gas source selected from the group consisting of the following chemical formula 1, chemical formula, and a silicone group represented by Chemical Formula 3 consisting of one or more 2:
[化学式1] [Chemical Formula 1]
SiH x (CH 3 ) 4-x SiH x (CH 3) 4- x
其中,x为整数,即0、1、2、或4; Wherein, x is an integer, i.e. 1, 2, or 4;
[化学式2] [Chemical Formula 2]
Si(OR 1 ) x R 2 4-x Si (OR 1) x R 2 4-x
其中,R 1及R 2独立地是被C1-5烷基或链烯基取代或未 Wherein, R 1 and R 2 are independently a substituted or unsubstituted C1-5 alkyl or alkenyl group
被取代的直链或支链的C1-10烷基或链烯基,而x为0-4的整 Substituted straight chain or branched C1-10 alkyl or alkenyl group, and x is an integer from 0 to 4
数; number;
[化学式3] [Chemical Formula 3]
环-(SiR 1 R 2 -O) n Ring - (SiR 1 R 2 -O) n
R 1及R 2独立地是氢或被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基。 R 1 and R 2 are independently hydrogen or C1-5 alkyl or alkenyl group substituted or unsubstituted C1-10 alkyl or alkenyl group, linear or branched.
62.根据权利要求61所述的薄膜晶体管基片,其中所述[化学式2]中R 1及R 2独立地是甲基、乙基、丙基、或乙烯基。 62. The thin film transistor substrate according to claim 61, wherein said [Chemical Formula 2] R 1 and R 2 are independently methyl, ethyl, propyl, or vinyl.
63.根据权利要求61所述的薄膜晶体管基片,其中所述[化学式3]中R 1及R 2独立地是氢、甲基、乙基、丙基、或乙烯基。 63. The thin film transistor substrate according to claim 61, wherein said [Chemical Formula 3] R 1 and R 2 are independently hydrogen, methyl, ethyl, propyl, or vinyl.
64.根据权利要求59所述的薄膜晶体管基片,其中所述氧化剂选自由O 2 、N 2 O、NO、CO 2 、CO、臭氧、及其混合物组成的组。 64. The thin film transistor substrate according to claim 59, wherein said oxidizing agent is selected from the group consisting of O 2, N 2 O, NO , CO 2, CO, ozone, and mixtures thereof.
65.根据权利要求59所述的薄膜晶体管基片,其中所述低介电绝缘层在1-10,000 Torr的压力和25-300℃的温度下,通过以0.2-1.5mW/cm 2的功率密度将反应气体混合物暴露给等离子体用PECVD法进行汽相淀积。 65. The thin film transistor substrate according to claim 59, wherein the low-dielectric insulating layer at a pressure of 1-10,000 Torr and a temperature of 25-300 deg.] C, the power density by 0.2-1.5mW / cm 2 of the reaction gas mixture is exposed to the plasma vapor phase deposition by PECVD.
66.根据权利要求59所述的薄膜晶体管基片,其中所述低介电绝缘层具有2-3的介电常数。 66. The thin film transistor substrate according to claim 59, wherein the low-dielectric insulating layer has a dielectric constant of 2-3.
67.根据权利要求59所述的薄膜晶体管基片,进一步包括: 67. The thin film transistor substrate according to claim 59, further comprising:
存储电容线,在与所述绝缘基片的所述栅极布线相同的层上形成; Storage capacitor lines formed on the gate wiring and the insulating layer of the same substrate;
存储电容器半导体图案,与所述存储电容线重叠,并在与所述半导体图案的相同的层上形成; Semiconductor pattern storage capacitor, the storage capacitor lines overlap, and are formed on the same layer and the semiconductor pattern;
存储电容器接触层图案,形成在所述存储电容器半导体图案上,并与所述存储电容器半导体图案具有相同的区域和形态;以及 A storage capacitor contact layer pattern is formed on the semiconductor pattern the storage capacitor, the storage capacitor and the semiconductor pattern having the same shape and area; and
存储电容器导电体图案,形成在所述存储电容器接触层图案上,并与所述存储电容器半导体图案具有相同的区域和形态, The storage capacitor conductor patterns formed on the storage capacitor contact layer pattern, and have the same area and shape with the storage capacitor semiconductor pattern,
其中,所述存储电容器半导体图案与所述透明电极图案的一部分连接。 Wherein a portion of the storage capacitor and the semiconductor pattern is connected to the transparent electrode pattern.
68.一种用于制造薄膜晶体管基片的方法,包括以下工序: 68. A method for manufacturing a thin film transistor substrate, comprising the steps of:
在绝缘基片上形成包括栅极线、与所述栅极线连接的栅极、及与所述栅极线连接的栅极衬垫的栅极布线; Comprising forming a gate line on an insulating substrate, a gate connected to the gate line, the gate pad and the gate wiring connected to the gate line;
形成栅极绝缘层; Forming a gate insulating layer;
形成半导体层; Forming a semiconductor layer;
堆垛并对导电物质制作布线图案以形成数据布线,所述数据布线包括与所述栅极线交叉的数据线、与所述数据线连接的数据衬垫、与所述数据线连接且邻接所述栅极的源极、及位于在所述栅极周围的所述源极的相对侧的漏极; Stacking and patterning a conductive material to form a data wiring, a data wiring includes a data line intersecting the gate pad and a data line, the data line is connected, is connected to the data line and adjacent to the electrode, and a drain positioned around opposite sides of the gate electrode to the source of said source of said gate;
堆垛低介电绝缘层以形成保护层; Stacking low dielectric insulating layer to form a protective layer;
对所述保护层和所述栅极绝缘层一起制作布线图案,以形成分别露出所述栅极衬垫、所述数据衬垫、及所述漏极的接触孔;以及 Patterning together with the protective layer and the gate insulating layer to expose the gate pad are formed, the data pad, a contact hole and the drain electrode; and
通过接触孔堆垛并对透明导电层制作布线图案以形成分别与所述栅极衬垫、所述数据衬垫、及所述漏极连接的辅助栅极衬垫、辅助数据衬垫、及像素电极, A contact hole through the stack and the transparent conductive layer is patterned to form the gate pad, a data pad, and an auxiliary gate pad connected to the drain, and the auxiliary data pad, respectively, and the pixel electrode,
其中通过在所述数据布线上加入包括主源气体、硅烷SiH 4 、和氧化剂的反应气体混合物以用CVD法或PECVD法汽相淀积a-SiCOH薄膜进行形成保护层的工序。 Which comprises a main step by the addition of a source gas, a reaction gas is silane SiH 4, and an oxidizer mixture with a CVD method or a vapor deposition method PECVD a-SiCOH film is formed on the protective layer data wiring.
69.根据权利要求68所述的用于制造薄膜晶体管基片的方法,其中所述硅烷气体SiH 4与主源气体的比率是1:0.5到1:1。 69. The method for manufacturing a thin film transistor substrate according to claim 68, wherein the silane gas ratio of SiH 4 gas is the main source of 1: 0.5 to 1: 1.
70.根据权利要求68所述的用于制造薄膜晶体管基片的方法,其中所述主源气体选自由以下化学式1、化学式2、和化学式3表示的有机硅组成的组中的一种或多种: 70. The method of one or more sets for manufacturing a thin film transistor substrate according to claim 68, wherein said primary gas source selected from the group consisting of the following Chemical Formula 1, Chemical Formula 2, Chemical Formula 3, and the silicone composition represented by the species:
[化学式1] [Chemical Formula 1]
SiH x (CH 3 ) 4-x SiH x (CH 3) 4- x
其中,x为整数,即0、1、2、或4; Wherein, x is an integer, i.e. 1, 2, or 4;
[化学式2] [Chemical Formula 2]
Si(OR 1 ) x R 2 4-x Si (OR 1) x R 2 4-x
其中,R 1及R 2独立地是被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基,而x为0-4的整数; Wherein, R 1 and R 2 are independently a C1-10 alkyl or alkenyl group C1-5 alkyl or alkenyl group substituted or unsubstituted straight-chain or branched, and x is an integer from 0 to 4 ;
[化学式3] [Chemical Formula 3]
环-(SiR 1 R 2 -O) n Ring - (SiR 1 R 2 -O) n
R 1及R 2独立地是氢或被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基。 R 1 and R 2 are independently hydrogen or C1-5 alkyl or alkenyl group substituted or unsubstituted C1-10 alkyl or alkenyl group, linear or branched.
71.根据权利要求70所述的用于制造薄膜晶体管基片的方法,其中所述[化学式2]中R 1及R 2独立地是甲基、乙基、丙基、或乙烯基。 71. The method for manufacturing a thin film transistor substrate according to claim 70, wherein said [Chemical Formula 2] R 1 and R 2 are independently methyl, ethyl, propyl, or vinyl.
72.根据权利要求70所述的用于制造薄膜晶体管基片的方法,其中所述[化学式3]中R 1及R 2独立地是氢、甲基、乙基、丙基、或乙烯基。 72. The method for manufacturing a thin film transistor substrate according to claim 70, wherein said [Chemical Formula 3] R 1 and R 2 are independently hydrogen, methyl, ethyl, propyl, or vinyl.
73.根据权利要求68所述的用于制造薄膜晶体管基片的方法,其中所述氧化剂选自由O 2 、N 2 O、NO、CO 2 、CO、臭氧、及其混合物组成的组。 73. A method for manufacturing a thin film transistor substrate according to claim 68, wherein said oxidizing agent is selected from the group consisting of O 2, N 2 O, NO , CO 2, CO, ozone, and mixtures thereof.
74.根据权利要求68所述的用于制造薄膜晶体管基片的方法,其中所述低介电绝缘层具有2-3的介电常数。 74. A method for manufacturing a thin film transistor substrate according to claim 68, wherein the low-dielectric insulating layer has a dielectric constant of 2-3.
75.根据权利要求68所述的用于制造薄膜晶体管基片的方法,其中所述数据布线及所述半导体层用具有第一部分、比所述第一部分厚度厚的第二部分、及比所述第一部分厚度薄的第三部分的感光层图案一起进行光学蚀刻工序。 75. A method for manufacturing a thin film transistor substrate according to claim 68, wherein the data wiring and the semiconductor layer having a first portion thicker than the thickness of the second portion of the first portion, and the ratio of optical etching step with a first portion of the thickness of the third portion of the photosensitive layer pattern.
76.根据权利要求68所述的用于制造薄膜晶体管基片的方法,其中在所述光学蚀刻工序中,使所述第一部分位于所述源极和所述漏极之间,而使所述第二部分位于所述数据布线上。 76. A method for manufacturing a thin film transistor substrate according to claim 68, wherein said optical etching step, the first portion positioned between the source and the drain, leaving the a second portion located on the data wiring.
77.根据权利要求68所述的用于制造薄膜晶体管基片的方法,其中所述形成栅极绝缘层的工序由汽相淀积低介电绝缘层的第一工序及汽相淀积氮化硅层的第二工序组成,所述第一工序和所述第二工序在保持真空状态下进行。 77. The method for manufacturing a thin film transistor substrate according to claim 68, wherein said step of forming a gate insulating layer by vapor deposition of a low dielectric insulating layer and a first step of vapor depositing a nitride the second step of the silicon layer is composed of the first step and the second step is performed while maintaining a vacuum state.
78.一种用于制造薄膜晶体管基片的方法,包括以下工序: 78. A method for manufacturing a thin film transistor substrate, comprising the steps of:
第一工序,在绝缘基片上形成包含数据线的数据布线; A first step of forming a data line comprising a data wiring on an insulating substrate;
第二工序,在所述基片上形成红、绿、和蓝滤色器; A second step of forming red, green, and blue color filters on the substrate;
第三工序,用低介电绝缘层形成覆盖所述数据布线及所述滤色器的缓冲层; A third step, low-dielectric insulating layer forming a buffer layer covering the data wiring and the color filter;
第四工序,在所述绝缘层上形成包含栅极线及栅极的栅极布线; A fourth step of forming a gate wiring including a gate line and a gate electrode on said insulating layer;
第五工序,形成覆盖所述栅极布线的栅极绝缘层; A fifth step of forming a gate insulating layer covering the gate wiring;
第六工序,在所述栅极绝缘层上形成欧姆接触层和半导体层图案的同时在所述栅极绝缘层和所述缓冲层形成露出所述数据线一部分的第一接触孔; Meanwhile a sixth step of forming an ohmic contact layer and the semiconductor layer pattern is formed on the gate insulating layer to expose a first contact hole in a portion of the data line of the gate insulating layer and the buffer layer;
第七工序,形成彼此分离且在同一层上形成的源极及漏极,并且在所述欧姆接触层图案上形成包括与所述漏极连接的像素电极的像素布线;以及 A seventh step of forming a wiring separated from each other and the pixel in the source and drain are formed on the same layer, and comprising a pixel electrode connected to the drain electrode on the ohmic contact layer pattern; and
第八工序,除去位于所述源极和所述漏极之间所述欧姆接触层图案的露出部分以将所述欧姆接触层图案分成两部分, An eighth step of removing said source positioned pattern the ohmic contact layer between the drain electrode and to the exposed portion of the ohmic contact layer pattern is divided into two portions,
其中通过在所述滤色器上加入包括主源气体、硅烷SiH 4 、和氧化剂的反应气体混合物以用CVD法或PECVD法汽相淀积a-SiCOH薄膜进行形成所述缓冲层的工序。 Which comprises a main step by the addition of a source gas, a reaction gas is silane SiH 4, and an oxidizer mixture with a CVD method or a vapor deposition method PECVD a-SiCOH film is formed on the buffer layer in the color filter.
79.根据权利要求78所述的用于制造薄膜晶体管基片的方法,其中所述硅烷气体SiH 4与主源气体的比率是1:0.5到1:1。 79. The method for manufacturing a thin film transistor substrate according to claim 78, wherein the silane gas ratio of SiH 4 gas is the main source of 1: 0.5 to 1: 1.
80.根据权利要求78所述的用于制造薄膜晶体管基片的方法,其中所述主源气体选自由以下化学式1、化学式2、和化学式3表示的有机硅组成的组中的一种或多种: 80. The method of one or more sets for manufacturing a thin film transistor substrate according to claim 78, wherein said primary gas source selected from the group consisting of the following Chemical Formula 1, Chemical Formula 2, Chemical Formula 3, and the silicone composition represented by the species:
[化学式1] [Chemical Formula 1]
SiH x (CH 3 ) 4-x SiH x (CH 3) 4- x
其中,x为整数,即0、1、2、或4; Wherein, x is an integer, i.e. 1, 2, or 4;
[化学式2] [Chemical Formula 2]
Si(OR 1 ) x R 2 4-x Si (OR 1) x R 2 4-x
其中,R 1及R 2独立地是被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基,而x为0-4的整数; Wherein, R 1 and R 2 are independently a C1-10 alkyl or alkenyl group C1-5 alkyl or alkenyl group substituted or unsubstituted straight-chain or branched, and x is an integer from 0 to 4 ;
[化学式3] [Chemical Formula 3]
环-(SiR 1 R 2 -O) n Ring - (SiR 1 R 2 -O) n
R 1及R 2独立地是氢或被C1-5烷基或链烯基取代或未被取代的直链或支链的C1-10烷基或链烯基。 R 1 and R 2 are independently hydrogen or C1-5 alkyl or alkenyl group substituted or unsubstituted C1-10 alkyl or alkenyl group, linear or branched.
81.根据权利要求80所述的用于制造薄膜晶体管基片的方法,其中所述[化学式2]中R 1及R 2独立地是甲基、乙基、丙基、或乙烯基。 81. The method for manufacturing a thin film transistor substrate according to claim 80, wherein said [Chemical Formula 2] R 1 and R 2 are independently methyl, ethyl, propyl, or vinyl.
82.根据权利要求80所述的用于制造薄膜晶体管基片的方法,其中所述[化学式3]中R 1及R 2独立地是氢、甲基、乙基、丙基、或乙烯基。 82. The method for manufacturing a thin film transistor substrate according to claim 80, wherein said [Chemical Formula 3] R 1 and R 2 are independently hydrogen, methyl, ethyl, propyl, or vinyl.
83.根据权利要求78所述的用于制造薄膜晶体管基片的方法,其中所述氧化剂选自由O 2 、N 2 O、NO、CO 2 、CO、臭氧、及其混合物组成的组。 83. The method for manufacturing a group of thin film transistor substrate according to claim 78, wherein said oxidizing agent selected from the group consisting of O 2, N 2 O, NO , CO 2, CO, ozone, and mixtures thereof.
84.根据权利要求78所述的用于制造薄膜晶体管基片的方法,其中所述低介电绝缘层具有2-3的介电常数。 84. The method for manufacturing a thin film transistor substrate according to claim 78, wherein the low-dielectric insulating layer has a dielectric constant of 2-3.
85.根据权利要求78所述的用于制造薄膜晶体管基片的方法,其中所述第六工序包括以下工序: 85. The method for manufacturing a thin film transistor substrate according to claim 78, wherein said sixth step comprises the steps of:
在所述栅极绝缘层上依次汽相淀积非晶硅层和掺杂的非晶硅层; Successively vapor-deposited amorphous silicon layer and the doped amorphous silicon layer on the gate insulating layer;
形成由覆盖所述栅极上规定区域的第一部分、及覆盖除了将形成所述第一接触孔的区域的所述规定区域的第二部分组成,所述第二部分比所述第一部分薄; Said gate electrode is formed by covering a predetermined region on the first portion, and a cover except the contact hole forming region of the first predetermined region of the second portion, and said second portion is thinner than the first portion;
将所述感光层的第一部分及第二部分作为掩模以蚀刻其下部的膜和层,即,所述掺杂的非晶硅层、所述非晶硅层、所述栅极绝缘层、及所述缓冲层,以形成所述第一接触孔; The first portion and the second portion of the photosensitive layer as a mask to etch the film and its lower layer, i.e., the doped amorphous silicon layer, the amorphous silicon layer, the gate insulating layer, and the buffer layer, to form the first contact hole;
除去所述感光层图案的第二部分; Removing the second portion of the photosensitive layer pattern;
将所述感光层图案的第一部分作为掩模以蚀刻其下部的膜和层,即,所述掺杂的非晶硅层和所述非晶硅层,以形成半导体层图案和欧姆接触层图案;以及 The first portion of the photosensitive layer pattern as a mask to etch the film and its lower layer, i.e., the doped amorphous silicon layer and the amorphous silicon layer to form a semiconductor layer pattern and the ohmic contact layer pattern ;as well as
除去所述感光层图案的第一部分。 A first portion of the photosensitive layer pattern is removed.
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