KR102242893B1 - Display Device - Google Patents

Abstract

The present invention includes a display panel and a driver. The display panel includes sub-pixels and displays an image. The driver drives the display panel and supplies driving signals to sub-pixels of the display panel. The sub-pixel includes a thin film transistor overlapping a data line formed on a lower substrate.

Description

Display Device

The present invention relates to a display device.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, a flat panel display (FPD) such as a liquid crystal display (LCD), an organic light emitting diode display (OLED), a plasma display panel (PDP), etc. ) Is on the rise.

Some of the above-described display devices, for example, a liquid crystal display device or an organic light emitting display device, include a display panel including a plurality of sub-pixels arranged in a matrix form and a driver driving the display panel. The driver includes a scan driver that supplies a scan signal (or a gate signal) to the display panel, and a data driver that supplies a data signal to the display panel.

In the above display device, when a scan signal and a data signal are supplied to a display panel including sub-pixels arranged in a matrix form, the selected sub-pixel emits light, thereby displaying an image.

On the other hand, liquid crystal display devices or organic light emitting display devices need to improve the transmittance and aperture ratio of sub-pixels included in the display panel in response to the trend of increasing high resolution and size, as well as reducing the mask process to improve production yield, etc. The problem of is emerging.

The present invention for solving the problems of the above-described background technology improves the transmittance and aperture ratio of the sub-pixels included in the display panel, reduces the mask process to improve the production yield, etc., and improves the reliability of the device. It is to provide a display device.

As a means for solving the above problems, the present invention includes a display panel and a driving unit. The display panel includes sub-pixels and displays an image. The driver drives the display panel and supplies driving signals to sub-pixels of the display panel. The sub-pixel includes a thin film transistor overlapping a data line formed on a lower substrate.

In the thin film transistor, a drain region, a channel region, and a source region may vertically overlap a data line.

In the thin film transistor, the shape and position of the drain electrode and the source electrode may be asymmetric.

In the thin film transistor, the drain electrode and the source electrode may be positioned at different heights, and one of the drain electrode and the source electrode may be positioned at the same height as the channel region.

In the thin film transistor, the channel region may form a straight line corresponding to the data line or may form an oblique line toward the opening region of the sub-pixel.

In the thin film transistor, one of the drain electrode and the source electrode may extend to an opening area of the sub-pixel to become a pixel electrode.

The display panel includes a first sub-pixel, and the first sub-pixel is positioned on the i-th data line and the i-th data line formed on the lower substrate, and the drain region, the channel region, and the source region are vertically overlapped with the i-th data line. It may include a thin film transistor.

The display panel includes a second sub-pixel located under the first sub-pixel, and the second sub-pixel includes an i-th data line formed on a lower substrate, and a drain region located on the i-th data line. , A thin film transistor in which the channel region and the source region are vertically overlapped, and the first sub-pixel is connected to the j-th gate line, and the second sub-pixel is connected to the k-th gate line located on the next line of the j-th gate line. have.

The display panel includes a second sub-pixel positioned below the first sub-pixel, and the second sub-pixel is positioned on the j-th data line and the j-th data line adjacent to the i-th data line. A thin film transistor in which a drain region, a channel region, and a source region are vertically overlapped may be included, and the first sub-pixel and the second sub-pixel may be commonly connected to the j-th gate line.

The sub-pixel includes a data metal formed on a lower substrate, at least one lower insulating film formed on the data metal and having a first contact hole exposing the data metal, a semiconductor layer formed on the insulating film and connected to the data metal, and a semiconductor It may include an upper insulating layer formed on the layer and formed at a position adjacent to the first contact hole, and a gate metal formed on the upper insulating layer.

In the present invention, since the thin film transistor does not exist in the open area as in the related art, but is formed to overlap the data line corresponding to the non-open area, both the transmittance and the aperture ratio of the sub-pixel can be improved. In addition, according to the present invention, the data metal is formed directly on the lower substrate and the semiconductor layer of the thin film transistor is protected from external light, thereby improving the reliability of the device. In addition, according to the present invention, as the structure and process of the thin film transistor are innovatively changed, the electrode or the contact structure between electrodes can be simplified, so that the deposition process, the photo process, the mask process, etc. can be omitted, thereby improving the production yield. have.

1 is a block diagram schematically showing a liquid crystal display device.
FIG. 2 is a circuit diagram schematically showing a sub-pixel shown in FIG. 1;
3 is a plan view of a sub-pixel according to the first embodiment of the present invention.
4 is a plan view of a sub-pixel according to a modified example of the first embodiment of the present invention.
5 to 9 are cross-sectional views illustrating regions A1-A2 of FIGS. 3 and 4.
10 is a plan view of a sub-pixel according to another modified example of the first embodiment of the present invention.
11 is a plan view of a sub-pixel according to a second embodiment of the present invention.
12 to 15 are cross-sectional views illustrating regions B1-B2 of FIG. 11.
16 is a cross-sectional view showing a region C1-C2 of FIG. 11;

Hereinafter, specific details for carrying out the present invention will be described with reference to the accompanying drawings.

The display devices described below are implemented in small (eg, smart phones, watches, etc.), medium (eg, monitors, televisions, etc.) and large (eg, televisions) models. In addition, the display device described below includes a display panel and a driver (gate driver, data driver) that supplies driving signals to the display panel. In addition, the display device described below is implemented as a liquid crystal display device or an organic light emitting display device according to the structure and configuration of the display panel.

Hereinafter, in the present invention, for convenience of description, a liquid crystal display, which is one of the display devices, will be described as an example. Specifically, the first embodiment describes an IPS (In Plane Switching) mode and the second embodiment describes a TN (Twisted Nematic) mode as an example, but may be used in other modes. In addition, the thin film transistor described below may also be used for a switching transistor or a compensation transistor included in a display panel of an organic light emitting display device.

<First Example>

1 is a block diagram schematically illustrating a liquid crystal display device, and FIG. 2 is a circuit diagram schematically illustrating a sub-pixel illustrated in FIG. 1.

1 and 2, the liquid crystal display device includes a timing control unit 130, a gate driving unit 140, a data driving unit 150, a liquid crystal panel 160, and a backlight unit 170.

The timing control unit 130 outputs a gate timing control signal GDC for controlling the operation timing of the gate driving unit 140 and a data timing control signal DDC for controlling the operation timing of the data driving unit 150. The timing control unit 130 supplies the data signal (or data voltage) DATA supplied from the image processing unit 110 together with the data timing control signal DDC to the data driver 150.

The gate driver 140 outputs a gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing control unit 130. The gate driver 140 supplies a gate signal to the sub-pixels SP included in the liquid crystal panel 160 through the gate lines GL. The gate driver 140 is formed in the form of an integrated circuit (IC) or formed on the liquid crystal panel 160 in a gate in panel (Gate In Panel) method.

The data driver 150 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing control unit 130, converts it to a gamma reference voltage, and outputs the sample. The data driver 150 supplies a data signal DATA to the sub-pixels SP included in the liquid crystal panel 160 through the data lines DL. The data driver 150 is formed in the form of an integrated circuit (IC).

The liquid crystal panel 160 displays an image in response to the gate signal supplied from the gate driver 140 and the data signal DATA supplied from the data driver 150. The liquid crystal panel 160 includes sub-pixels SP that control light provided through the backlight unit 170.

One sub-pixel includes a switching transistor SW, a storage capacitor Cst, and a liquid crystal layer Clc. The gate electrode of the switching transistor SW is connected to the gate line GL1 and the source electrode is connected to the data line DL1. The storage capacitor Cst has one end connected to the drain electrode of the switching transistor SW and the other end connected to the common voltage line Vcom. The liquid crystal layer Clc is formed between the pixel electrode 1 connected to the drain electrode of the switching transistor SW and the common electrode 2 connected to the common voltage line Vcom.

The liquid crystal panel 160 is a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching) mode according to the structure of the pixel electrode 1 and the common electrode 2 Alternatively, it is implemented in an Electrically Controlled Birefringence (ECB) mode.

The backlight unit 170 provides light to the liquid crystal panel 160 using a light source or the like that emits light. The backlight unit 170 includes a light-emitting diode (hereinafter, referred to as LED), an LED driver for driving the LED, an LED substrate on which the LED is mounted, a light guide plate for converting light emitted from the LED into a surface light source, a reflector for reflecting light from the lower portion of the light guide plate, And optical sheets for condensing and diffusing light emitted from the light guide plate.

Hereinafter, a first embodiment of the present invention will be embodied with reference to a plan view and a cross-sectional view of a sub pixel.

3 is a plan view of a sub-pixel according to a first embodiment of the present invention, FIG. 4 is a plan view of a sub-pixel according to a modified example of the first embodiment of the present invention, and FIGS. 5 to 9 are A cross-sectional view showing areas A1-A2, and FIG. 10 is a plan view of a sub-pixel according to still another modified example of the first embodiment of the present invention.

As shown in FIG. 3, according to the first embodiment of the present invention, thin film transistors TFT driving the subpixels SP11 and SP21 are formed in the non-opening area. The non-opening area includes data lines DLi to DLj and gate lines GLi to GLk that transmit data signals to the subpixels SP11 and SP21.

Referring to the thin film transistor TFT that drives the eleventh sub-pixel SP11, the thin film transistor TFT is formed in the first direction y (or the major axis direction of the sub-pixel) to form the i-th data line DLi. ) In the vertical (or up and down) direction. Specifically, the thin film transistor TFT is formed in the first direction y so that the drain region DA, the channel region CHA, and the source region SA are perpendicular to (or up and down) the ith data line DL. It will overlap in the direction. CH1 refers to a contact hole in which the data line and the semiconductor layer of the thin film transistor (TFT) contact.

When describing the thin film transistor TFT that drives the 21st sub-pixel SP21, the thin film transistor TFT is formed in the first direction y (or the major axis direction of the sub-pixel) and is connected to the i-th data line DLi. They overlap in one vertical (or vertical) direction. Specifically, the thin film transistor TFT is formed in the first direction y so that the drain region DA, the channel region CHA, and the source region SA are perpendicular to (or up and down) the ith data line DL. It will overlap in the direction.

The eleventh sub-pixel SP11 and the twenty-first sub-pixel SP21 positioned under the eleventh sub-pixel SP11 are vertically divided by the j-th gate line GLj. The eleventh sub-pixel SP11 and the 21st sub-pixel SP21 are commonly connected to the i-th data line DLi to share one data line.

The thin film transistor TFT driving the eleventh subpixel SP11 and the thin film transistor TFT driving the 21th subpixel SP21 are formed to overlap in a direction perpendicular to the i-th data line DLi. However, the thin film transistor TFT driving the eleventh sub-pixel SP11 is formed adjacent to the j-th gate line GLj. On the other hand, the thin film transistor driving the 21st sub-pixel SP21 is not shown, but is formed adjacent to the k-th gate line GLk, which is the next line of the j-th gate line GLj. That is, the thin film transistor TFT for driving the eleventh sub-pixel SP11 and the thin film transistor TFT for driving the 21st sub-pixel SP21 are positioned up and down on the same line.

As shown in FIG. 4, according to a modified example of the first embodiment of the present invention, the thin film transistors TFT included in the sub-pixels SP11 and SP21 are formed in the non-opening area. The non-opening area includes data lines DLi to DLj and gate lines GLi to GLk that transmit data signals to the subpixels SP11 and SP21.

Referring to the thin film transistor TFT that drives the eleventh sub-pixel SP11, the thin film transistor TFT is formed in the first direction y (or the major axis direction of the sub-pixel) to form the i-th data line DLi. ) In the vertical (or up and down) direction. Specifically, the thin film transistor TFT is formed in the first direction y so that the drain region DA, the channel region CHA, and the source region SA are perpendicular to (or up and down) the ith data line DL. It will overlap in the direction. CH1 refers to a contact hole in which the data line and the semiconductor layer of the thin film transistor (TFT) contact.

When describing the thin film transistor TFT that drives the 21st sub-pixel SP21, the thin film transistor TFT is formed in the first direction y (or the major axis direction of the sub-pixel) and is connected to the i-th data line DLi. They overlap in one vertical (or vertical) direction. Specifically, the thin film transistor TFT is formed in the first direction y so that the drain region DA, the channel region CHA, and the source region SA are perpendicular to (or up and down) the ith data line DL. It will overlap in the direction.

The eleventh sub-pixel SP11 and the twenty-first sub-pixel SP21 positioned under the eleventh sub-pixel SP11 are vertically divided by the j-th gate line GLj. The eleventh sub-pixel SP11 is connected to the i-th data line DLi, but the 21st sub-pixel SP21 is connected to the j-th data line DLj, which is a side line.

The thin film transistor TFT for driving the eleventh sub-pixel SP11 is formed to overlap in a direction perpendicular to the i-th data line DL, and the thin film transistor TFT for driving the 21st sub-pixel SP21 is It is formed to overlap in a direction perpendicular to the j data line DLj. However, the thin film transistor TFT for driving the eleventh sub-pixel SP11 and the thin film transistor for driving the 21st sub-pixel SP21 are formed adjacent to the j-th gate line GLj.

The thin film transistor TFT for driving the eleventh sub-pixel SP11 and the thin film transistor TFT for driving the 21st sub-pixel SP21 are positioned vertically on an oblique line. In addition, the thin film transistor TFT for driving the eleventh sub-pixel SP11 and the thin film transistor TFT for driving the 21st sub-pixel SP21 are common to the j-th gate line GLj so as to share one gate line. Connected.

As can be seen from the above description, the thin film transistor TFT for driving the eleventh sub-pixel SP11 and the thin film transistor TFT for driving the 21st sub-pixel SP21 may be implemented to share one data line. have. Also, unlike this, the thin film transistor TFT for driving the eleventh sub-pixel SP11 and the thin film transistor TFT for driving the 21st sub-pixel SP21 may be implemented to share one gate line.

As described above, in the first embodiment of the present invention, since the thin film transistor (TFT) does not exist in the open area as in the prior art and is formed to overlap in a direction perpendicular to the data line corresponding to the non-open area, the transmittance and aperture ratio of the sub-pixels You will be able to improve all of them.

In the above description, as shown in FIG. 3, when viewed in the second direction (x) (or the short axis direction of the sub-pixel), thin film transistors driving the sub-pixels are arranged in a parallel direction as an example. In addition, in the above description, as shown in FIG. 4, when viewed in the second direction (x) (or the short axis direction of the sub-pixel), thin film transistors that drive the sub-pixels are arranged in a diagonal direction as an example.

However, this is only an example, and after matching the thin film transistor TFT and the data line, the position of the thin film transistor TFT may be changed according to the shape of the pixel electrode of another device or sub-pixel. For this reason, in the first embodiment of the present invention, referring to FIGS. 3 and 5, a plan view showing different positions of the thin film transistors (TFTs) is shown.

Meanwhile, in the above description, since the thin film transistor TFT is of the N type, it is shown that the source region SA of the semiconductor layer exists in the opening region of the sub-pixel. However, when the thin film transistor TFT is of the P type, the drain region DA of the semiconductor layer will exist in the opening region of the sub-pixel.

Hereinafter, a structural understanding of the first embodiment of the present invention and a modified example thereof will be aided with reference to FIGS. 5 to 9 showing cross-sectional views of the area A1-A2 of FIGS. 3 and 4.

As shown in FIG. 5, a data metal 161 is formed on the lower substrate 160a, and patterned along the i-th data line area. Data metal 161 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or an alloy thereof It may be, and may be made of a single layer or multiple layers. The data metal 161 is formed in a first direction (refer to the y direction in FIG. 3). The patterned data metal 161 becomes an i-th data line DLi.

As described above, in the first embodiment of the present invention, since the data metal 161 is formed directly on the lower substrate 160a, the semiconductor layer of the thin film transistor formed below can be protected from external light, thereby improving the reliability of the device. There will be.

As shown in FIG. 6, a first insulating layer 162 is formed on the lower substrate 160a to cover the data metal 161. The first insulating layer 162 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The first insulating layer 162 may be defined as a first protective layer.

A second insulating layer 163 is formed on the first insulating layer 162. The second insulating layer 163 may be made of an organic material such as polyimide, benzocyclobutene series resin, acrylate, and photoacrylate. The second insulating layer 163 may be defined as a planarization layer, which may be omitted depending on a process and a material.

A first contact hole CH1 is formed so that the data metal 161 is exposed. The first contact hole CH1 is formed collectively after forming the first insulating layer 162 and the second insulating layer 163 on the lower substrate 160a, or the first insulating layer 162 and the second insulating layer 163 It can also be individually formed in the middle of forming.

7, a semiconductor layer 164 is formed on the second insulating layer 163. After the semiconductor layer 164 is formed, a portion of the semiconductor layer 164 is vertically overlapped with the data metal 161 and is connected (contacted) with the data metal 161 through the first contact hole CH1, and the remaining portion is an opening of the sub-pixel. Pattern to extend to the area. The semiconductor layer 164 is made of an amorphous oxide semiconductor such as indium gallium zinc oxide (IGZO).

As shown in FIG. 8, a third insulating layer 165 is formed on the semiconductor layer 164. The third insulating layer 165 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The third insulating layer 165 may be defined as a gate insulating layer.

As described above, the second insulating layer 163 of the first and second insulating layers 162 and 163 may be omitted depending on the structure, and the first and second insulating layers 162 and 163 are used as the lower insulating layer and the third insulating layer 163. The insulating layer 165 may be defined as an upper insulating layer.

A gate metal 166 is formed on the third insulating layer 165 and patterned along the j-th gate line region. The gate metal 166 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or an alloy thereof It may be, and may be made of a single layer or multiple layers. The gate metal 166 is formed in the second direction (refer to the x direction in FIG. 3 ). The patterned gate metal 166 becomes the j-th gate line GLj and becomes a gate electrode in the region of the thin film transistor TFT.

To perform the above process, a third insulating layer 165 and a gate metal 166 are sequentially formed on the lower substrate 160a, and correspond to the j-th gate line region adjacent to the first contact hole CH1. Patterning is done so that only the part that is to be left remains. Accordingly, the third insulating layer 165 and the gate metal 166 exist in the form of an island at a position adjacent to the first contact hole CH1 when viewed in cross section. However, when viewed in plan view, the third insulating layer 165 and the gate metal 166 have a line shape that is elongated along the second direction.

On the other hand, when patterning the gate metal 166, dry etching is performed. Then, in the semiconductor layer 164, except for the channel region CHA protected by the third insulating layer 165, the portion and sub-area existing in the non-opening region such as the portion DA overlapping and connected to the data metal 161 The portion SA extending to the opening area of the pixel is metalized.

The portion DA of the semiconductor layer 164 overlapping and connected to the data metal 161 becomes a drain electrode of the thin film transistor TFT, and the portion SA extending to the opening region of the sub-pixel is the thin film transistor TFT. It becomes a source electrode of and at the same time becomes a pixel electrode. That is, the source region SA of the semiconductor layer 164 serves as a pixel electrode together with the source electrode.

In general, the drain electrode and the source electrode of the thin film transistor TFT exist on the same layer (or the same height) (the shape and position of the drain electrode and the source electrode are symmetrical). However, as can be seen from the drawings, in the structure according to the first embodiment of the present invention, the drain electrode and the source electrode of the thin film transistor (TFT) exist in different layers (or different heights) (the shape of the drain electrode and the source electrode). And the position is asymmetric).

Specifically, a portion of the drain electrode (a portion in contact with the data line) of the thin film transistor TFT exists in a layer different from the source electrode. As described above, the drain electrode and the source electrode of the thin film transistor TFT vary depending on whether they are in contact with the data line and also serve as a pixel electrode. In addition, as the drain electrode and the source electrode of the transistor TFT become asymmetric, one of them can use a wide area.

For example, as shown in the drawing, the source electrode of the thin film transistor TFT exists at a higher position than the drain electrode. In other words, it can be said that the channel region CHA and the source region SA of the thin film transistor TFT exist at the same height and also exist at a higher position than the drain region DA. In addition, as shown in the drawing, the source electrode of the thin film transistor TFT exists flat with the channel region, but the drain electrode is recessed and bent.

The reason why metallization occurs in the semiconductor layer 164 that is not protected by the third insulating layer 165 is that the semiconductor layer 164 such as IGZO reacts with oxygen caused by plasma during dry etching. Hereinafter, since the method of metallizing the semiconductor layer 164 corresponds to a conventional technique, a detailed description thereof will be omitted.

When dry etching is performed in this way, the structures 164, 165, and 166 formed in the regions overlapping the data metal 161 become thin film transistors (TFTs). Meanwhile, in the above description, metallization of the semiconductor layer 164 for each region using dry etching has been described as an example. However, metallization of the semiconductor layer 164 for each region is not limited to the above description.

As described above, the first embodiment of the present invention simplifies the contact structure between electrodes by changing the structure and process of a thin film transistor (TFT), thereby omitting a deposition process, a photo process, a mask process, etc., thereby improving production yield. I can.

9, a fourth insulating layer 167 is formed to cover the semiconductor layer 164 and the gate metal 166. The third insulating layer 165 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The fourth insulating layer 167 may be defined as a second protective layer.

A common electrode 168 is formed on the fourth insulating layer 167. After the common electrode 168 is formed, it is patterned to have a divided finger (or fork, etc.) shape within the opening area. The common electrode 168 is connected to a common voltage line (not shown) formed on the lower substrate 160a. The common electrode 168 is formed of the same indium gallium zinc oxide (IGZO) as the semiconductor layer 164 or an oxide material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

If the above process is performed, a liquid crystal panel can be manufactured with a total of 6 mask processes. However, the above description is only an example, and it goes without saying that the number of masks may increase or decrease according to the structure of the subpixel to be implemented.

As shown in FIG. 10, according to another modified example, the channel region CHA of the thin film transistor TFT may not be formed in a linear shape as in the first embodiment (FIG. 3 or 4), but may be formed in an oblique shape. have.

As in another modified example, when the channel region CHA of the thin film transistor TFT is formed in an oblique shape (or obliquely toward the opening region of the sub-pixel) with respect to the data line, L ( The value of length) can be increased, so that the off current of the thin film transistor TFT can be improved.

Meanwhile, as in the first embodiment (FIG. 3 or 4), an example in which the channel region CHA of the thin film transistor TFT is formed in a straight line (or a straight line corresponding to the data line) with respect to the data line is the channel region ( Since CHA) exists in a semiconductor state, it is possible because the effect of parasitic capacitors is small.

<Second Example>

11 is a plan view of a sub-pixel according to a second embodiment of the present invention, FIGS. 12 to 15 are cross-sectional views illustrating regions B1-B2 of FIG. 11, and FIG. 16 is a cross-sectional view illustrating regions C1-C2 of FIG. 11. .

As shown in FIG. 11, according to the second embodiment of the present invention, thin film transistors TFT driving the subpixels SP11 and SP21 are formed in the non-opening area. The non-opening area includes data lines DLi to DLj and gate lines GLi to GLk that transmit data signals to the subpixels SP11 and SP21.

Referring to the thin film transistor TFT that drives the eleventh sub-pixel SP11, the thin film transistor TFT is formed in the first direction y (or the major axis direction of the sub-pixel) to form the i-th data line DLi. ) In the direction perpendicular to it. Specifically, the thin film transistor TFT is formed in the first direction y so that the drain region DA, the channel region CHA, and the source region SA overlap in a direction perpendicular to the i-th data line DLi. do. CH1 refers to a contact hole in which the data line and the semiconductor layer of the thin film transistor (TFT) contact.

When describing the thin film transistor TFT that drives the 21st sub-pixel SP21, the thin film transistor TFT is formed in the first direction y (or the major axis direction of the sub-pixel) and is connected to the i-th data line DLi. They overlap in a vertical direction. Specifically, the thin film transistor TFT is formed in the first direction y so that the drain region DA, the channel region CHA, and the source region SA overlap in a direction perpendicular to the i-th data line DLi. do.

The eleventh sub-pixel SP11 and the twenty-first sub-pixel SP21 positioned under the eleventh sub-pixel SP11 are vertically divided by the j-th gate line GLj. The eleventh sub-pixel SP11 and the 21st sub-pixel SP21 are commonly connected to the i-th data line DLi to share one data line.

The thin film transistor TFT driving the eleventh subpixel SP11 and the thin film transistor TFT driving the 21th subpixel SP21 are formed to overlap in a direction perpendicular to the i-th data line DLi. However, the thin film transistor TFT driving the eleventh sub-pixel SP11 is formed adjacent to the j-th gate line GLj. On the other hand, the thin film transistor driving the 21st sub-pixel SP21 is not shown, but is formed adjacent to the k-th gate line GLk, which is the next line of the j-th gate line GLj. That is, the thin film transistor TFT for driving the eleventh sub-pixel SP11 and the thin film transistor TFT for driving the 21st sub-pixel SP21 are positioned up and down on the same line.

As can be seen from the above description, the thin film transistor TFT for driving the eleventh sub-pixel SP11 and the thin film transistor TFT for driving the 21st sub-pixel SP21 may be implemented to share one data line. have. Also, unlike this, the thin film transistor TFT for driving the eleventh sub-pixel SP11 and the thin film transistor TFT for driving the 21st sub-pixel SP21 may be implemented to share one gate line.

As described above, in the second embodiment of the present invention, since the thin film transistor (TFT) does not exist in the open area as in the prior art and is formed to overlap in a direction perpendicular to the data line corresponding to the non-open area, the transmittance and aperture ratio of the sub-pixels You will be able to improve all of them.

In the above description, as shown in FIG. 11, when viewed in the second direction (x) (or the short axis direction of the sub-pixel), thin film transistors driving the sub-pixels are arranged in a parallel direction as an example. However, as shown in FIG. 4 of the first embodiment, thin film transistors that drive the sub-pixels may be disposed in a diagonal direction when viewed in the second direction (x) (or the short axis direction of the sub-pixel).

However, this is only an example, and after matching the thin film transistor TFT and the data line, the position of the thin film transistor TFT may be changed according to the shape of the pixel electrode of another device or sub-pixel.

Meanwhile, in the above description, since the thin film transistor TFT is of the N type, it is shown that the source region SA of the semiconductor layer exists in the opening region of the sub-pixel. However, when the thin film transistor TFT is of the P type, the drain region DA of the semiconductor layer will exist in the opening region of the sub-pixel.

Hereinafter, a structural understanding of the second embodiment of the present invention will be aided with reference to FIGS. 12 to 15 showing a cross-sectional view of the region B1-B2 of FIG. 11 and FIG. 16 showing a cross-sectional view of the region C1-C2 of FIG. 11.

As shown in FIG. 12, a data metal 161 is formed on the lower substrate 160a, and patterned along the ith data line region. Data metal 161 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or an alloy thereof It may be, and may be made of a single layer or multiple layers. The data metal 161 is formed in the first direction (refer to the y direction in FIG. 11 ). The patterned data metal 161 becomes an i-th data line DLi.

As described above, in the second embodiment of the present invention, since the data metal 161 is formed directly on the lower substrate 160a, the semiconductor layer of the thin film transistor formed below can be protected from external light, thereby improving the reliability of the device. There will be.

13, a first insulating layer 162 (lower insulating layer) is formed on the lower substrate 160a to cover the data metal 161. The first insulating layer 162 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The first insulating layer 162 may be defined as a first protective layer.

Thereafter, a first contact hole CH1 is formed in the first insulating layer 162 so that the data metal 161 is exposed. Meanwhile, in the above description, only the first insulating layer 162 is formed as an example. However, depending on the structure, a second insulating film (not shown) for planarizing the surface on the first insulating film 162 may be further formed.

As shown in FIG. 14, a semiconductor layer 164 is formed on the first insulating layer 162. After the semiconductor layer 164 is formed, a portion of the semiconductor layer 164 is vertically overlapped with the data metal 161 and is connected (contacted) with the data metal 161 through the first contact hole CH1, and the remaining portion is an opening of the sub-pixel. Pattern to extend to the area. The semiconductor layer 164 is made of an amorphous oxide semiconductor such as indium gallium zinc oxide (IGZO).

As shown in FIG. 15, a third insulating layer 165 (upper insulating layer) is formed on the semiconductor layer 164. The third insulating layer 165 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The third insulating layer 165 may be defined as a gate insulating layer.

A gate metal 166 is formed on the third insulating layer 165 and patterned along the j-th gate line region. The gate metal 166 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or an alloy thereof It may be, and may be made of a single layer or multiple layers. The gate metal 166 is formed in the second direction (refer to the x direction in FIG. 3 ). The patterned gate metal 166 becomes the j-th gate line GLj and becomes a gate electrode in the region of the thin film transistor TFT.

To perform the above process, a third insulating layer 165 and a gate metal 166 are sequentially formed on the lower substrate 160a, and correspond to the j-th gate line region adjacent to the first contact hole CH1. Patterning is done so that only the part to be left remains.

Accordingly, the third insulating layer 165 and the gate metal 166 exist in the form of an island at a position adjacent to the first contact hole CH1 when viewed in cross section. However, when viewed in plan view, the third insulating layer 165 and the gate metal 166 have a line shape that is elongated along the second direction.

On the other hand, when patterning the gate metal 166, dry etching is performed. Then, in the semiconductor layer 164, except for the channel region CHA protected by the third insulating layer 165, the portion and sub-area existing in the non-opening region such as the portion DA overlapping and connected to the data metal 161 The portion SA extending to the opening area of the pixel is metalized.

The portion DA of the semiconductor layer 164 overlapping and connected to the data metal 161 becomes a drain electrode of the thin film transistor TFT, and the portion SA extending to the opening region of the sub-pixel is the thin film transistor TFT. It becomes a source electrode of and at the same time becomes a pixel electrode. That is, the source region SA of the semiconductor layer 164 serves as a pixel electrode together with the source electrode. In this case, the portion that becomes the pixel electrode may be formed in the form of a conductive electrode or a finger (or a fork) in the opening area.

The reason why metallization occurs in the semiconductor layer 164 that is not protected by the third insulating layer 165 is that the semiconductor layer 164 such as IGZO reacts with oxygen caused by plasma during dry etching. Hereinafter, since the method of metallizing the semiconductor layer 164 corresponds to a conventional technique, a detailed description thereof will be omitted.

When dry etching is performed in this way, the structures 164, 165, and 166 formed in the regions overlapping the data metal 161 become thin film transistors (TFTs). Meanwhile, in the above description, metallization of the semiconductor layer 164 for each region using dry etching has been described as an example. However, metallization of the semiconductor layer 164 for each region is not limited to the above description.

As described above, the second embodiment of the present invention simplifies the contact structure between electrodes by changing the structure and process of a thin film transistor (TFT), so that the deposition process, photo process, mask process, etc. can be omitted, thereby improving production yield. I can.

The common voltage line is formed in the opening area of the sub-pixel by the above process, which will be described below with reference to FIG. 16.

As shown in FIG. 16, a common voltage line 169 is formed on the lower substrate 160a together with the data metal 161 serving as the i-th data line DLi. The data metal 161 is formed in the non-opening area, but the common voltage line 169 is formed in the open area of the sub-pixel.

The common voltage line 169 is connected to a common electrode formed on an upper substrate (not shown) that faces the lower substrate 160a. The common electrode faces the pixel electrode of the sub-pixel with a liquid crystal layer therebetween.

The common voltage line 169 is formed of the same indium gallium zinc oxide (IGZO) as the semiconductor layer 164 or an oxide material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A first insulating layer 162 is formed on the data metal 161 and the common voltage line 169. The first insulating layer 162 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The first insulating layer 162 may be defined as a first protective layer.

A semiconductor layer 164 is formed on the first insulating layer 162. The illustrated semiconductor layer 164 is a drain electrode and a portion of a pixel electrode extending to an opening region of a sub-pixel. As described above, the semiconductor layer 164 is made of an amorphous oxide semiconductor such as IGZO.

As described above, in the present invention, since the thin film transistor does not exist in the open region as in the prior art, but is formed to overlap in a vertical direction with the data line corresponding to the non-open region, both transmittance and aperture ratio of the sub-pixel can be improved. In addition, according to the present invention, the data metal is formed directly on the lower substrate and the semiconductor layer of the thin film transistor is protected from external light, thereby improving the reliability of the device. In addition, according to the present invention, as the structure and process of the thin film transistor are innovatively changed, the electrode or the contact structure between electrodes can be simplified, so that the deposition process, the photo process, the mask process, etc. can be omitted, thereby improving the production yield. have.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above is in other specific forms without changing the technical spirit or essential features of the present invention by those skilled in the art. It will be appreciated that it can be implemented. Therefore, the embodiments described above are illustrative in all respects and should be understood as non-limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

130: timing control unit 140: gate driving unit
150: data driving unit 160: liquid crystal panel
170: backlight unit TFT: thin film transistor
DA: Drain area CHA: Channel area
SA: source region 161: data metal
164: semiconductor layer 166: gate metal

Claims (11)

Display panel;
Sub-pixels included in the display panel; And
And a driving unit supplying a driving signal to a sub-pixel of the display panel,
The sub-pixel includes a thin film transistor overlapping a data line formed on a lower substrate,
The thin film transistor is
A drain electrode, a channel region, and a source electrode are formed based on one semiconductor layer, and one of the drain electrode and the source electrode is positioned between the data line and the channel region, and the data line is formed through an insulating film having a contact hole. In addition to contacting with, a sidewall of the insulating layer is contacted, and the other is extended to an opening area of a sub-pixel on the insulating layer to become a pixel electrode. The method of claim 1,
In the thin film transistor, a drain region selected as the drain electrode, the channel region, and a source region selected as the source electrode all overlap in a vertical direction of the data line. The method of claim 1,
The thin film transistor is
The display device, wherein the shape and position of the drain electrode and the source electrode are asymmetric. The method of claim 3,
The thin film transistor is
And the drain electrode and the source electrode are positioned at different heights, and one of the drain electrode and the source electrode is positioned at the same height as the channel region. The method of claim 2,
The thin film transistor is
The display device, wherein the channel region forms a straight line corresponding to the data line or an oblique line toward the opening region of the sub-pixel. delete The method of claim 1,
The display panel includes a first sub-pixel,
The first sub-pixel includes an i-th data line formed on the lower substrate,
A display device including a thin film transistor positioned on the i-th data line and vertically overlapping a drain region, a channel region, and a source region on the i-th data line. The method of claim 7,
The display panel includes a second sub-pixel positioned below the first sub-pixel,
The second sub-pixel includes the i-th data line formed on the lower substrate,
A thin film transistor positioned on the i-th data line and vertically overlapping a drain region, a channel region, and a source region on the i-th data line,
And the first sub-pixel is connected to a j-th gate line, and the second sub-pixel is connected to a k-th gate line positioned on a line next to the j-th gate line. The method of claim 7,
The display panel includes a second sub-pixel positioned below the first sub-pixel,
The second sub-pixel includes a j-th data line adjacent to the i-th data line,
A thin film transistor positioned on the j-th data line and vertically overlapping a drain region, a channel region, and a source region on the j-th data line,
And the first sub-pixel and the second sub-pixel are connected in common to a j-th gate line. The method of claim 1,
The sub-pixel is
A data metal formed on the lower substrate,
At least one lower insulating layer formed on the data metal and having a contact hole exposing the data metal;
A semiconductor layer formed on the insulating layer and connected to the data metal;
An upper insulating layer formed on the semiconductor layer and formed at a position adjacent to the contact hole;
A display device including a gate metal formed on the upper insulating layer. The method of claim 10,
The contact hole is
A display device completely overlapping the vertical direction of the data metal.

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