KR102231043B1 - Liquid Crystal Display Device - Google Patents

Abstract

The present invention relates to a liquid crystal display device including a first substrate, a pixel electrode, a common electrode, a data line, a second insulating film, a liquid crystal layer, and a black matrix. The pixel electrode is located in an opening defined on the first substrate. The common electrode is positioned in an opening defined on the first substrate and is positioned on a different layer from the pixel electrode. The data line is located in a non-opening part defined on the first substrate. The liquid crystal layer is tilted in response to an electric field applied by the pixel electrode and the common electrode. The black matrix may cover a region corresponding to the data line and may be non-overlapping with the pixel electrode.

Description

Liquid Crystal Display Device

The present invention relates to a liquid crystal display device.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, a flat panel display (FPD) such as a liquid crystal display (LCD), an organic light emitting diode display (OLED), a plasma display panel (PDP), etc. ) Is on the rise. Among them, a liquid crystal display device capable of realizing high resolution and capable of miniaturization as well as enlargement is widely used.

A liquid crystal display device includes a first substrate on which a thin film transistor or the like is formed, a second substrate on which a color filter or the like is formed, and a liquid crystal layer interposed therebetween. Among the liquid crystal display devices, in a method such as an IPS (In Plane Switching) or FFS (Fringe Field Switching) mode, a common electrode and a pixel electrode are formed on the thin film first substrate.

In order to block VAC (Viewing Angle Crosstalk) from the diagonal viewing direction, the IPS or FFS mode liquid crystal display device needs a design to increase the size (width) of the black matrix that covers the data line.

However, if the size of the black matrix in the corresponding area is increased to cover the data line, the aperture ratio decreases. For this reason, the higher the PPI (Pixel Per Inch), the greater the decrease in the aperture ratio. Conventionally, a shielding electrode for shielding the electric field of the planarization layer and the data line has been proposed in order to improve the above problem.

However, a structure that is difficult to form a shielding electrode due to structural and process characteristics causes VAC generation due to movement of the black matrix during the bonding process of the substrate. Accordingly, a structure in which it is difficult to form a shielding electrode among IPS or FFS mode liquid crystal display devices is inevitably required to increase the size of the black matrix covering the data line in consideration of the aperture ratio.

The present invention for solving the problems of the above-described background art prevents the occurrence of VAC due to the movement of the black matrix, improves the aperture ratio by further reducing the size of the black matrix covering the data line, and simplifies the process and provides fairness ( Tact Time).

The present invention relates to a liquid crystal display device including a first substrate, a pixel electrode, a common electrode, a data line, a second insulating film, a liquid crystal layer, and a black matrix. The pixel electrode is located in an opening defined on the first substrate. The common electrode is positioned in an opening defined on the first substrate and is positioned on a different layer from the pixel electrode. The data line is located in a non-opening part defined on the first substrate. The liquid crystal layer is tilted in response to an electric field applied by the pixel electrode and the common electrode. The black matrix may cover a region corresponding to the data line and may be non-overlapping with the pixel electrode.

The distance between the pixel electrode and the adjacent pixel electrode may be larger than the size of the black matrix.

The distance between the pixel electrode and the black matrix may be smaller than the size of the black matrix.

The liquid crystal layer may be aligned so as to be perpendicular to the direction of an electric field applied by the pixel electrode and the common electrode.

The liquid crystal layer may be a negative liquid crystal.

The pixel electrode may be positioned between the first substrate and the first insulating layer, and the common electrode may be positioned between the second insulating layer and the liquid crystal layer positioned on the first insulating layer.

The common electrode may be positioned between the first substrate and the first insulating layer, and the pixel electrode may be positioned between the second insulating layer and the liquid crystal layer positioned on the first insulating layer.

The present invention can prevent the occurrence of VAC due to movement of the black matrix even in a structure in which it is difficult to form a shielding electrode due to structural and process characteristics. In addition, according to the present invention, the size of the black matrix that covers the data line can be further reduced, thereby improving the aperture ratio. In addition, in the present invention, since the planarization layer and the shielding electrode can be eliminated, the process can be simplified and the processability can be improved. In addition, according to the present invention, since the electrode connected to the shielding electrode can be deleted, data load and parasitic capacitance (Cdc) can be reduced. In addition, the present invention simplifies the process and improves processability, so that the substrate bonding margin and the VAC margin do not need to be considered, thereby increasing the degree of freedom in design.

1 is a block diagram schematically showing a liquid crystal display device.
2 is a circuit diagram of a sub-pixel shown in FIG. 1;
3 is a view for explaining a problem according to the experimental example.
4 is a view showing a simulation result of the experimental example shown in FIG. 3.
5 is a view for explaining an improvement point according to the first embodiment.
6 is a view showing a simulation result of the first embodiment shown in FIG. 5.
7 is a plan layout diagram schematically showing sub-pixels of a liquid crystal display according to a first embodiment of the present invention.
8 is a cross-sectional view of a region A1-A2 of FIG. 7;
9 is a view for explaining a comparison of the first embodiment compared to the conventional structure.
10 is a plan layout diagram schematically showing sub-pixels of a liquid crystal display according to a second embodiment of the present invention.
FIG. 11 is a first example view showing a sectional view of a region B1-B2 of FIG. 10;
FIG. 12 is a second exemplary view showing a sectional view of a region B1-B2 of FIG. 10;
13 is a plan layout diagram schematically showing sub-pixels of a liquid crystal display according to a third exemplary embodiment of the present invention.
FIG. 14 is a first exemplary view showing a sectional view of a region C1-C2 of FIG. 13;
15 is a second exemplary view showing a sectional view of a region C1-C2 of FIG. 12;

Hereinafter, specific details for carrying out the present invention will be described with reference to the accompanying drawings.

<First Example>

1 is a block diagram schematically illustrating a liquid crystal display device, and FIG. 2 is a circuit configuration diagram of a sub-pixel shown in FIG. 1.

1 and 2, the liquid crystal display includes a timing control unit 130, a gate driving unit 140, a data driving unit 150, a liquid crystal panel 160, and a backlight unit 170.

The timing control unit 130 receives a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a clock signal, a data signal, and the like from the outside. The timing control unit 130 controls operation timings of the data driving unit 150 and the gate driving unit 140 using timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal.

Since the timing control unit 130 may determine the frame period by counting the data enable signal of one horizontal period, the vertical synchronization signal and the horizontal synchronization signal supplied from the outside may be omitted. The control signals generated by the timing control unit 130 include a gate timing control signal GDC for controlling the operation timing of the gate driving unit 140 and a data timing control signal DDC for controlling the operation timing of the data driving unit 150. ) May be included.

The gate driver 140 outputs a gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing control unit 130. The gate driver 140 supplies a gate signal to the liquid crystal panel 160 through the gate lines GL. The gate driver 140 is formed in an IC form or formed on the liquid crystal panel 160 in a gate in panel method.

The data driving unit 150 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing control unit 130, and converts it into an analog form in response to the gamma reference voltage and outputs the sample. The data driver 150 supplies a data signal DATA to the liquid crystal panel 160 through the data lines DL. The data driver 150 is formed in the form of an IC.

The liquid crystal panel 160 displays an image in response to a gate signal and a data signal DATA supplied from a driver including the gate driver 140 and the data driver 150. The liquid crystal panel 160 includes a plurality of sub-pixels SP that control light provided through the backlight unit 170.

One sub-pixel includes a switching transistor TFT, a storage capacitor Cst, and a liquid crystal layer Clc. The gate electrode of the switching transistor TFT is connected to the gate line GL1 and the source electrode is connected to the data line DL1. The storage capacitor Cst has one end connected to the drain electrode of the switching transistor TFT and the other end connected to the common voltage line Vcom. The liquid crystal layer Clc is formed between the pixel electrode 1 connected to the drain electrode of the switching transistor TFT and the common electrode 2 connected to the common voltage line Vcom.

The liquid crystal panel 160 includes a first substrate on which a thin film transistor is formed, a second substrate on which a color filter is formed, and a liquid crystal layer interposed therebetween. The lower polarizing plate is attached to the lower surface of the first substrate, and the upper polarizing plate is attached to the upper surface of the second substrate. The liquid crystal panel 160 is implemented in an IPS (In Plane Switching) mode or a FFS (Fringe Field Switching) mode in which the pixel electrode 1 and the common electrode 2 are formed on the first substrate.

The backlight unit 170 provides light to the liquid crystal panel 160. The backlight unit 170 includes a light-emitting diode (hereinafter, referred to as LED), an LED driver that drives the LED, a light guide plate that converts light emitted from the LED into a surface light source, and optical sheets for condensing and diffusing the light emitted from the light guide plate. .

Meanwhile, the aforementioned IPS or FFS mode liquid crystal display device needs to be designed to increase the size (width) of the black matrix covering the data line in order to block VAC (Viewing Angle Crosstalk) in the diagonal viewing direction. The black matrix is defined as a non-opening part from which light is not emitted.

However, if the size of the black matrix in the corresponding area is increased to cover the data line, the aperture ratio decreases. For this reason, the higher the PPI (Pixel Per Inch), the greater the decrease in the aperture ratio. Conventionally, a shielding electrode for shielding the electric field of the planarization layer and the data line has been proposed in order to improve the above problem.

However, a structure that is difficult to form a shielding electrode due to structural and process characteristics causes VAC generation due to movement of the black matrix during the bonding process of the substrate. Accordingly, a structure in which it is difficult to form a shielding electrode among IPS or FFS mode liquid crystal display devices is inevitably required to increase the size of the black matrix covering the data line in consideration of the aperture ratio.

3 is a diagram for explaining a problem according to the experimental example, FIG. 4 is a diagram showing a simulation result of the experimental example shown in FIG. 3, and FIG. 5 is a diagram for explaining improvements according to the first embodiment, and FIG. 6 is a diagram showing a simulation result of the first embodiment shown in FIG. 5.

[Experimental Example]

3 and 4, the liquid crystal display according to the experimental example is implemented in the IPS or FFS mode as follows.

Specifically, the pixel electrodes 162 and PXL are formed on the openings of the first substrate 160a. The pixel electrodes 162 and PXL are formed in the form of a conductive electrode on the opening. A first insulating layer 163 covering the pixel electrodes 162 and PXL is formed on the first substrate 160a. An Nth data line DLn including a semiconductor layer 164 and a metal layer 165 is formed on the first insulating layer 163.

A second insulating layer 166 is formed on the first insulating layer 163 to cover the Nth data line DLn. Common electrodes 167 and VCOM are formed on the openings of the second insulating layer 166. The common electrodes 167 and VCOM are formed in the form of divided electrodes on the openings.

A black matrix BM covering the Nth data line DLn is positioned on the non-opening portion of the inner surface of the second substrate 160b. The black matrix (BM) is formed of a black resin that can block light.

In the liquid crystal display according to the experimental example, the liquid crystal layers 168 and LC are aligned so that they are horizontal with respect to the direction of the electric field (E-Field). In other words, the liquid crystal layers 168 and LC are aligned to be perpendicular to the Nth data line DLn. When the liquid crystal display according to the experimental example had the following conditions, it was found that VAC was induced while tilting the liquid crystal as shown in FIG. 4.

Condition (1) Opening: Maintaining the black voltage after charging

Condition (2) Nth data line DLn: A state in which the white voltage (White) is applied

Condition (3) Liquid crystal layer: A state in which positive liquid crystals (Positive LC) are arranged

In the liquid crystal display according to the experimental example, since Δn (difference in dielectric constant) of the liquid crystal is different depending on the viewing angle, light leakage occurs in a region adjacent to the data line (or the data electrode part). This is because the liquid crystal layers 168 and LC are aligned horizontally with respect to the electric field direction (E-Field), so that the liquid crystal tilts according to the electric field direction (E-Field) of the data line.

As a result of various experiments to solve the above problem, the problem according to the experimental example could be improved by the following first example.

[First Embodiment]

5 and 6, the liquid crystal display according to the first embodiment is implemented in an IPS or FFS mode as follows.

Specifically, the pixel electrodes 162 and PXL are formed on the openings of the first substrate 160a. The pixel electrodes 162 and PXL are formed in the form of a conductive electrode on the opening. A first insulating layer 163 covering the pixel electrodes 162 and PXL is formed on the first substrate 160a. An Nth data line DLn including a semiconductor layer 164 and a metal layer 165 is formed on the first insulating layer 163.

A second insulating layer 166 is formed on the first insulating layer 163 to cover the Nth data line DLn. Common electrodes 167 and VCOM are formed on the openings of the second insulating layer 166. The common electrodes 167 and VCOM are formed in the form of divided electrodes on the openings.

A black matrix BM covering the Nth data line DLn is positioned on the non-opening portion of the inner surface of the second substrate 160b. The black matrix (BM) is formed of a black resin that can block light.

In the liquid crystal display according to the first embodiment, the liquid crystal layers 168 and LC are aligned so that they are perpendicular to the direction of the electric field (E-Field). In other words, the liquid crystal layers 168 and LC are aligned horizontally with the Nth data line DLn. When the liquid crystal display according to the first embodiment has the following conditions, it was found that VAC is not induced because the tilt does not occur in the liquid crystal as shown in FIG. 6.

Condition (1) Opening: Maintaining the black voltage after charging

Condition (2) Nth data line DLn: A state in which the white voltage (White) is applied

Condition (3) Liquid crystal layer: Negative LC is arranged

In the liquid crystal display according to the first exemplary embodiment, even if the viewing angle is different, since Δn (differential dielectric constant) of the liquid crystal is similar or the same, light leakage does not occur in a region adjacent to the data line (or the data electrode part). The reason is that the liquid crystal layers 168 and LC are aligned so as to be perpendicular to the direction of the electric field (E-Field), so that the liquid crystal does not tilt according to the direction of the electric field (E-Field) of the data line.

Hereinafter, a description will be given of a liquid crystal display device implemented based on the first embodiment. However, in the following, as the liquid crystal layers 168 and LC are aligned so as to be perpendicular to the direction of the electric field (E-Field), the structural design-related parts will be specified.

7 is a plan layout diagram schematically showing sub-pixels of a liquid crystal display according to the first embodiment of the present invention, and FIG. 8 is a cross-sectional view of areas A1-A2 of FIG. 7, and FIG. 9 is a first compared to the conventional structure. It is a figure for comparatively demonstrating an Example.

As shown in FIG. 7, the subpixels SPn-1 and SPn of the liquid crystal display according to the first embodiment of the present invention include a plurality of electrodes (eg, a pixel electrode or a common electrode) positioned in the opening. It is implemented in an IPS or FFS mode method that forms a multi-domain as it is divided into. A cross section of the two subpixels SPn-1 and SPn adjacent to the left and right based on the Nth data line DLn is as follows.

As shown in FIG. 8, pixel electrodes 162 and PXL are formed on the openings of the first substrate 160a. The pixel electrodes 162 and PXL are formed in the form of a conductive electrode on the opening. The pixel electrodes 162 and PXL may be formed of a transparent metal such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A first insulating layer 163 covering the pixel electrodes 162 and PXL is formed on the first substrate 160a. The first insulating layer 163 may be formed of silicon oxide (SiOx) or silicon nitride (SiNx).

An Nth data line DLn including a semiconductor layer 164 and a metal layer 165 is formed on the first insulating layer 163. The semiconductor layer 164 may be selected from one of a silicon (Si) series, an oxide series, a graphene series including carbon nanotubes (CNT), a nitride series, and an organic semiconductor series. . The metal layer 165 is any selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be formed of one or an alloy thereof.

A second insulating layer 166 is formed on the first insulating layer 163 to cover the Nth data line DLn. The second insulating layer 166 may be formed of silicon oxide (SiOx) or silicon nitride (SiNx).

Common electrodes 167 and VCOM are formed on the openings of the second insulating layer 166. The common electrodes 167 and VCOM are formed in the form of divided electrodes on the openings. The common electrode 167 (VCOM) may be formed of a transparent metal such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

A black matrix BM covering the Nth data line DLn is positioned on the Nth data line DLn. The black matrix BM is positioned on a second substrate that is bonded and sealed with the first substrate 160a. In the drawings, the second substrate is omitted for convenience of description.

In the first embodiment of the present invention, the size (width) of the black matrix BM covering the Nth data line DLn can be narrowed as the liquid crystal layer uses a negative liquid crystal aligned to be perpendicular to the direction of the electric field. It was confirmed to be.

In this case, in order to minimize the size (width) of the black matrix (BM), the liquid crystal described above may be used and the following design may be performed.

(1) A data line and an outer portion of an electrode adjacent to the data line (eg, a pixel electrode or a common electrode) are arranged so as to maintain a parallel straight line shape within the opening.

(2) Horizontal or vertical rubbing is performed and formed to have multi-domains.

(3) Delete the shielding electrode existing at the position overlapping the data line.

(4) Arrange so that the black matrix that covers the data line and the pixel electrode do not overlap each other (vertical non-overlapping) when viewed from the cross-section. For example, as the distance L3 between the black matrix BM covering the Nth data line DLn and the N-1th subpixel SPn-1 or the Nth subpixel SPn, the Nth data line DLn The black matrix BM and the pixel electrodes 162 and PXL are spaced apart from each other.

(5) The distance (PXL to PXL distance) between the pixel electrode and the (adjacent) pixel electrode is larger than the size of the black matrix covering the data line. For example, it is formed larger than the size L1 of the black matrix BM covering the Nth data line DLn, such as a distance L2 between the N-1th and Nth subpixels SPn-1 and SPn. .

In addition to the above conditions, the distance L3 between the black matrix BM covering the Nth data line DLn and the N-1th subpixel SPn-1 or the Nth subpixel SPn is the Nth data line. It is possible to add a condition to form smaller than the size (L1) of the black matrix (BM) that covers (DLn).

[Comparison between the conventional structure and the first embodiment]

As shown in (a) of FIG. 9, the conventional structure includes the planarization layer 169 and the N-th data line DLn in order to block VAC in the diagonal viewing direction when implementing the IPS or FFS mode liquid crystal display. A shielding electrode 180 is used to shield the electric field.

Since the conventional structure uses the planarization layer 169 and the shielding electrode 180, the size L5 of the black matrix BM covering the Nth data line DLn can be narrowed compared to other structures. However, when the shielding electrode 180 as shown in FIG. 9A is not used, the size L5 of the black matrix BM covering the Nth data line DLn is the pixel electrode 162, It is large enough to overlap with PXL).

That is, when the shielding electrode 180 proposed in the conventional structure of FIG. 9A is not used, the size L5 of the black matrix BM covering the Nth data line DLn is the pixel electrode and the pixel. The distance between the electrodes (PXL to PXL distance) increases similarly or equal to L6.

As shown in (b) of FIG. 9, in the first embodiment, when implementing the IPS or FFS mode liquid crystal display, the liquid crystal layer is aligned so as to be perpendicular to the direction of the electric field in order to block VAC in the diagonal viewing direction. The negative liquid crystal is used and the black matrix BM covering the N-th data line DLn and the pixel electrodes 162 and PXL are disposed so as not to overlap each other (vertical non-overlapping).

In the first embodiment, the size L1 of the black matrix BM that covers the Nth data line DLn while not using the planarization layer 169 and the shielding electrode 180 can be narrowed compared to the conventional structure and other structures. In addition, the first embodiment is the distance between the black matrix BM covering the N-th data line DLn and the N-1 sub-pixel SPn-1 or the N-th sub-pixel SPn compared to the conventional structure and other structures. By widening (L3), the aperture ratio can be improved (see comparison between L7 and L3).

As can be seen through a simple comparison as shown in FIG. 9, the first embodiment of the present invention can prevent the occurrence of VAC due to the movement of the black matrix even in a structure in which it is difficult to form a shielding electrode due to structural and process characteristics. In addition, the first embodiment of the present invention can be applied to a liquid crystal panel having a high PPI (Pixel Per Inch) because the size of the black matrix that covers the data line can be reduced to a smaller size compared to the conventional structure, thereby improving the aperture ratio. In addition, according to the first embodiment of the present invention, since the planarization film and the shielding electrode used in the conventional structure can be eliminated, the process can be simplified and the Tact Time can be improved.

<Second Example>

FIG. 10 is a plan layout diagram schematically showing sub-pixels of a liquid crystal display according to a second embodiment of the present invention, FIG. 11 is a first example view showing a sectional view of regions B1-B2 of FIG. 10, and FIG. 12 is It is a 2nd example view showing the sectional plane of the area|region B1-B2 of FIG.

As shown in FIG. 10, the subpixels SPn-1 and SPn of the liquid crystal display according to the second embodiment of the present invention include a plurality of electrodes (eg, a pixel electrode or a common electrode) positioned in the opening. It is implemented in an IPS or FFS mode method that forms a multi-domain as it is divided into.

One of the electrodes (eg, a pixel electrode or a common electrode) positioned in the opening is arranged in the X-axis direction (or short axis direction) of the sub-pixels SPn-1 and SPn, so that the top and bottom are inclined in different directions ( To have a different slope).

Specifically, one of the electrodes (for example, a pixel electrode or a common electrode) positioned in the opening has the straight electrodes lying in the X-axis direction (or short axis direction) of the sub-cells SPn-1 and SPn (-) at the center of the opening. It is formed so that the left side is tilted toward the area. In the drawing, only two electrodes described above are shown, but N (N is an integer of 2 or more) or more are arranged.

A cross section of the two subpixels SPn-1 and SPn adjacent to the left and right based on the Nth data line DLn is as follows.

As shown in FIG. 11, pixel electrodes 162 and PXL (or first transparent electrodes) are formed on the openings of the first substrate 160a. The pixel electrodes 162 and PXL are formed in the form of a conductive electrode on the opening. The pixel electrodes 162 and PXL may be formed of a transparent metal such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A first insulating layer 163 covering the pixel electrodes 162 and PXL is formed on the first substrate 160a. The first insulating layer 163 may be formed of silicon oxide (SiOx) or silicon nitride (SiNx).

An Nth data line DLn including a semiconductor layer 164 and a metal layer 165 is formed on the first insulating layer 163. The semiconductor layer 164 may be selected from one of a silicon (Si) series, an oxide series, a graphene series including carbon nanotubes (CNT), a nitride series, and an organic semiconductor series. . The metal layer 165 is any selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be formed of one or an alloy thereof.

A second insulating layer 166 is formed on the first insulating layer 163 to cover the Nth data line DLn. The second insulating layer 166 may be formed of silicon oxide (SiOx) or silicon nitride (SiNx).

A common electrode 167 (VCOM) (or a second transparent electrode) is formed on the opening of the second insulating layer 166. The common electrodes 167 and VCOM are formed in the form of divided electrodes on the openings. The common electrode 167 (VCOM) may be formed of a transparent metal such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

A black matrix BM covering the Nth data line DLn is positioned on the Nth data line DLn. The black matrix BM is positioned on a second substrate that is bonded and sealed with the first substrate 160a. In the drawings, the second substrate is omitted for convenience of description.

As shown in FIG. 12, the electrode formed on the opening of the first substrate 160a may be a common electrode 167 (VCOM), and the electrode formed on the opening of the second insulating layer 166 may be a pixel electrode ( 162, PXL).

In the second embodiment of the present invention, the size (width) of the black matrix BM covering the N-th data line DLn can be narrowed as the liquid crystal layer uses a negative liquid crystal aligned to be perpendicular to the direction of the electric field. There will be. In this case, in order to minimize the size (width) of the black matrix (BM), the liquid crystal described above may be used and the following design may be performed.

(1) A data line and an outer portion of an electrode adjacent to the data line (eg, a pixel electrode or a common electrode) are arranged so as to maintain a parallel straight line shape within the opening.

(2) Horizontal or vertical rubbing is performed and formed to have multi-domains.

(3) Delete the shielding electrode existing at the position overlapping the data line.

(4) Arrange so that the black matrix that covers the data line and the pixel electrode do not overlap each other (vertical non-overlapping) when viewed from the cross-section. For example, as the distance L3 between the black matrix BM covering the Nth data line DLn and the N-1th subpixel SPn-1 or the Nth subpixel SPn, the Nth data line DLn The black matrix BM and the pixel electrodes 162 and PXL are spaced apart from each other.

(5) The distance (PXL to PXL distance) between the pixel electrode and the (adjacent) pixel electrode is larger than the size of the black matrix covering the data line. For example, it is formed larger than the size L1 of the black matrix BM covering the Nth data line DLn, such as a distance L2 between the N-1th and Nth subpixels SPn-1 and SPn. .

In addition to the above conditions, the distance L3 between the black matrix BM covering the Nth data line DLn and the N-1th subpixel SPn-1 or the Nth subpixel SPn is the Nth data line. It is possible to add a condition to form smaller than the size (L1) of the black matrix (BM) that covers (DLn).

<Third Example>

FIG. 13 is a plan layout diagram schematically showing subpixels of a liquid crystal display according to a third embodiment of the present invention, FIG. 14 is a first example view showing a cutaway of a region C1-C2 of FIG. 13, and FIG. 15 It is a 2nd example view showing the sectional plane of the area|region C1-C2 of FIG. 12.

As shown in FIG. 13, the subpixels SPn-1 and SPn of the liquid crystal display according to the third embodiment of the present invention are divided into a plurality of electrodes positioned in the openings, thereby forming a multi-domain. It is implemented in the FFS mode method. A cross section of the two subpixels SPn-1 and SPn adjacent to the left and right based on the Nth data line DLn is as follows.

One of the electrodes (eg, a pixel electrode or a common electrode) positioned in the opening is arranged in the X-axis direction (or short axis direction) of the sub-pixels SPn-1 and SPn, so that the top and bottom are inclined in different directions ( To have a different slope).

Specifically, one of the electrodes (for example, a pixel electrode or a common electrode) positioned in the opening is straight in the Y-axis direction (or the major axis direction) of the sub-cells SPn-1 and SPn. It is formed to be inclined toward the right based on the central area. In the drawing, only two electrodes described above are shown, but N (N is an integer of 2 or more) or more are arranged.

A cross section of the two subpixels SPn-1 and SPn adjacent to the left and right based on the Nth data line DLn is as follows.

As shown in FIG. 14, pixel electrodes 162 and PXL (or first transparent electrodes) are formed on the openings of the first substrate 160a. The pixel electrodes 162 and PXL are formed in the form of a conductive electrode on the opening. The pixel electrodes 162 and PXL may be formed of a transparent metal such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A first insulating layer 163 covering the pixel electrodes 162 and PXL is formed on the first substrate 160a. The first insulating layer 163 may be formed of silicon oxide (SiOx) or silicon nitride (SiNx).

An Nth data line DLn including a semiconductor layer 164 and a metal layer 165 is formed on the first insulating layer 163. The semiconductor layer 164 may be selected from one of a silicon (Si) series, an oxide series, a graphene series including carbon nanotubes (CNT), a nitride series, and an organic semiconductor series. . The metal layer 165 is any selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be formed of one or an alloy thereof.

A second insulating layer 166 is formed on the first insulating layer 163 to cover the Nth data line DLn. The second insulating layer 166 may be formed of silicon oxide (SiOx) or silicon nitride (SiNx).

A common electrode 167 (VCOM) (or a second transparent electrode) is formed on the opening of the second insulating layer 166. The common electrodes 167 and VCOM are formed in the form of divided electrodes on the openings. The common electrode 167 (VCOM) may be formed of a transparent metal such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A black matrix BM covering the Nth data line DLn is positioned on the Nth data line DLn. The black matrix BM is positioned on a second substrate that is bonded and sealed with the first substrate 160a. In the drawings, the second substrate is omitted for convenience of description.

As shown in FIG. 15, the electrode formed on the opening of the first substrate 160a may be a common electrode 167 (VCOM), and the electrode formed on the opening of the second insulating layer 166 may be a pixel electrode ( 162, PXL).

In the third embodiment of the present invention, the size (width) of the black matrix BM covering the N-th data line DLn can be narrowed as the liquid crystal layer uses a negative liquid crystal aligned to be perpendicular to the direction of the electric field. There will be. In this case, in order to minimize the size (width) of the black matrix (BM), the liquid crystal described above may be used and the following design may be performed.

(1) A data line and an outer portion of an electrode adjacent to the data line (eg, a pixel electrode or a common electrode) are arranged so as to maintain a parallel straight line shape within the opening.

(2) Horizontal or vertical rubbing is performed and formed to have multi-domains.

(3) Delete the shielding electrode existing at the position overlapping the data line.

(4) Arrange so that the black matrix that covers the data line and the pixel electrode do not overlap each other (vertical non-overlapping) when viewed from the cross-section. For example, as the distance L3 between the black matrix BM covering the Nth data line DLn and the N-1th subpixel SPn-1 or the Nth subpixel SPn, the Nth data line DLn The black matrix BM and the pixel electrodes 162 and PXL are spaced apart from each other.

(5) The distance (PXL to PXL distance) between the pixel electrode and the (adjacent) pixel electrode is larger than the size of the black matrix covering the data line. For example, it is formed larger than the size L1 of the black matrix BM covering the Nth data line DLn, such as a distance L2 between the N-1th and Nth subpixels SPn-1 and SPn. .

In addition to the above conditions, the distance L3 between the black matrix BM covering the Nth data line DLn and the N-1th subpixel SPn-1 or the Nth subpixel SPn is the Nth data line. It is possible to add a condition to form smaller than the size (L1) of the black matrix (BM) that covers (DLn).

Meanwhile, in the second and third embodiments of the present invention, only two examples having two domains as a structure of an electrode forming a multi-domain are shown. However, this is only an example, and the present invention is not limited thereto, and can be appropriately applied to an electrode structure forming a multi-domain.

As described above, even in a structure in which it is difficult to form a shielding electrode due to structural and process characteristics, it is possible to prevent the occurrence of VAC due to the movement of the black matrix. In addition, according to the present invention, the size of the black matrix that covers the data line can be further reduced, thereby improving the aperture ratio. In addition, in the present invention, since the planarization layer and the shielding electrode can be eliminated, the process can be simplified and the processability can be improved. In addition, according to the present invention, since the electrode connected to the shielding electrode can be deleted, data load and parasitic capacitance (Cdc) can be reduced. In addition, the present invention simplifies the process and improves processability, so that the substrate bonding margin and the VAC margin do not need to be considered, thereby increasing the degree of freedom in design.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above is in other specific forms without changing the technical spirit or essential features of the present invention by those skilled in the art. It will be appreciated that it can be implemented. Therefore, the embodiments described above are illustrative in all respects and should be understood as non-limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

130: timing control unit 140: gate driving unit
150: data driving unit 160: liquid crystal panel
170: backlight unit 160a: first substrate
162, PXL: pixel electrode 163: first insulating layer
166: second insulating layer DLn: Nth data line
167, VCOM: common electrode BM: black matrix
168, LC: liquid crystal layer

Claims (7)

A first substrate;
A pixel electrode positioned in an opening defined on the first substrate;
A common electrode positioned in an opening defined on the first substrate and positioned on a layer different from the pixel electrode;
A data line positioned in a non-opening portion defined on the first substrate;
A liquid crystal layer tilted in response to an electric field generated by the pixel electrode and the common electrode; And
Covering a region corresponding to the data line and including a black matrix non-overlapping with the pixel electrode,
The distance between the pixel electrode and the adjacent pixel electrode is greater than the size of the black matrix,
The distance between the pixel electrode and the black matrix is smaller than the size of the black matrix,
The liquid crystal layer is a negative liquid crystal, and is aligned to be perpendicular to the direction of an electric field applied by the pixel electrode and the common electrode,
The pixel electrode is divided into a plurality of the pixel electrodes in the opening and arranged in the same direction as the data line, and the pixel electrode is inclined toward the right with respect to the center line of the opening so that the central region of the opening protrudes to the left. delete delete delete delete The method of claim 1,
The pixel electrode is located between the first substrate and the first insulating layer,
And the common electrode is positioned between the liquid crystal layer and a second insulating layer on the first insulating layer. The method of claim 1,
The common electrode is located between the first substrate and the first insulating layer,
And the pixel electrode is positioned between the liquid crystal layer and a second insulating layer on the first insulating layer.

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