KR102167137B1 - Liquid Crystal Display Device and Manufacturing Method the same - Google Patents

Abstract

The present invention is a lower substrate; A thin film transistor formed on the lower substrate; A protective film formed on the lower substrate and the thin film transistor, exposing the drain electrode of the thin film transistor, and having an island shape in the transmission region of the sub-pixel and divided into a plurality; A common electrode partially formed on the passivation layer outside the transmissive area of the sub-pixel, and divided into a plurality of fingers having a finger shape on the island-shaped passivation layer disposed in the transmissive area of the sub-pixel; A pixel electrode formed on the lower substrate, connected to the drain electrode of the thin film transistor, having a finger shape in the transmission region of the sub-pixel, divided into a plurality, and non-overlapping the common electrode; And a horizontal common voltage line disposed on a common electrode positioned outside the transmission region of the sub-pixel.

Description

Liquid Crystal Display Device and Manufacturing Method the same}

The present invention relates to a liquid crystal display device and a method of manufacturing the same.

With the development of information technology, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, a flat panel display (FPD) such as a liquid crystal display (LCD), an organic light emitting diode display (OLED), and a plasma display panel (PDP). ) Is on the rise. Among them, a liquid crystal display device capable of realizing high resolution and capable of miniaturization as well as enlargement is widely used.

The liquid crystal display device is composed of a liquid crystal panel and a backlight unit that provides light to the liquid crystal panel. The liquid crystal panel includes a lower substrate including a thin film transistor and a storage capacitor, and an upper substrate including a color filter and a black matrix. A liquid crystal layer is formed between the lower substrate and the upper substrate, and the two substrates are bonded and sealed.

Meanwhile, some of the driving modes of a liquid crystal panel are in-plane switching (IPS) modes, which are widely applied to high-resolution and low-power applications because of their advantages in high transmittance and low voltage driving. However, some transverse electric field modes cause a decrease in transmittance as the pixel electrode and the common electrode existing in the opening area overlap. In addition, some of the transverse electric field modes have a problem of increasing the complexity of the process due to the large number of masks used in the enhancement process step. In addition, some transverse electric field modes have a problem that it is difficult to apply to large-sized televisions having a small pixel per inch (PPI).

The present invention for solving the problems of the above-described background technology is a liquid crystal display that can be applied to a large television by fabricating a transverse electric field mode liquid crystal panel capable of improving transmittance and reducing a driving voltage in a 4 mask process or a 5 mask process. It is to provide an apparatus and a method of manufacturing the same.

The present invention as a means for solving the above problems is a lower substrate; A thin film transistor formed on the lower substrate; A protective film formed on the lower substrate and the thin film transistor, exposing the drain electrode of the thin film transistor, and having an island shape in the transmission region of the sub-pixel and divided into a plurality; A common electrode partially formed on the passivation layer outside the transmissive area of the sub-pixel, and divided into a plurality of fingers having a finger shape on the island-shaped passivation layer disposed in the transmissive area of the sub-pixel; A pixel electrode formed on the lower substrate, connected to the drain electrode of the thin film transistor, having a finger shape in the transmission region of the sub-pixel, divided into a plurality, and non-overlapping the common electrode; And a horizontal common voltage line disposed on a common electrode positioned outside the transmission region of the sub-pixel.

The horizontal common voltage line may be disposed in a horizontal direction adjacent to the gate line formed on the lower substrate.

A gate pad portion and a data pad portion formed on the lower substrate are included, and the gate pad portion is formed on the gate pad electrode formed on the lower substrate, the transparent electrode formed on the gate pad electrode, and the horizontal common voltage line is formed on the transparent electrode. And a metal electrode formed of a material, and the data pad portion includes an insulating film formed on a lower substrate, a semiconductor layer formed on the insulating film, a source drain metal formed on the semiconductor layer, and a horizontal common voltage line formed on the source drain metal. It may include a metal electrode formed of the same material.

It is formed between the transistor and the passivation layer, and may further include a planarization layer covering the transistor.

In another aspect, the present invention includes forming a thin film transistor on a lower substrate; Exposing the drain electrode of the thin film transistor and forming a protective film divided into a plurality of islands in the transmission region of the sub-pixel; Forming a finger shape and divided into a plurality of common electrodes on an island-shaped passivation layer that is partially formed on the passivation layer outside the transmissive area of the sub-pixel and is located in the transmissive area of the sub-pixel; Forming a pixel electrode connected to the drain electrode of the thin film transistor, having a finger shape in the transmission region of the sub-pixel, divided into a plurality of pixels, and non-overlapping the common electrode; And forming a horizontal common voltage line disposed on a common electrode located outside the transmissive region of the sub-pixel.

The forming of the thin film transistor includes defining a horizontal common voltage line region, a thin film transistor region, a transmissive region, a gate pad region, and a data pad region on a lower substrate, forming a gate metal on the lower substrate, Forming a first photoresist on the substrate, forming a gate electrode on the thin film transistor region using a first mask, forming a gate pad electrode on the gate pad region, and forming an insulating film, a semiconductor layer, and a source on the lower substrate. A drain metal is sequentially formed, a second photoresist is formed on the source drain metal, and an insulating film, a semiconductor layer, and a source drain metal are formed on the gate electrode located on the thin film transistor region using a second mask. It may include forming a data pad electrode including an insulating layer, a semiconductor layer, and a source drain metal on the data pad region.

Forming the protective layer and the common electrode includes forming a first transparent electrode and a third photoresist on the lower substrate, the gate pad electrode, and the data pad electrode, and using a third mask to form part of the thin film transistor region and the gate pad region. And forming an island-shaped and divided protective film in the transmission region of the sub-pixel while exposing a part of the data pad region, etching using a third photoresist, and forming a part of the thin film transistor region, the sub-pixel And removing the protective layer and the first transparent electrode exposed through a part of the transparent region, a part of the gate pad region, and a part of the data pad region.

The forming of the pixel electrode includes sequentially forming a second transparent electrode and a fourth photoresist on the lower substrate and the third photoresist, and ashing the fourth photoresist to transmit a portion of the thin film transistor region and the subpixel. Removing a portion of the area, a portion of the gate pad area, and only a portion of the data pad area, etching the second transparent electrode exposed on the third photoresist, and removing the second transparent electrode exposed on the third photoresist. After etching, it may include removing the third photoresist and the fourth photoresist.

Forming the horizontal common voltage line includes forming a metal electrode in the form of a front electrode on the first transparent electrode and the second transparent electrode, forming a fifth photoresist on the metal electrode, and forming a fifth photoresist on the lower substrate. Aligning the fourth mask and forming a region corresponding to the horizontal common voltage line region, the gate pad region, and the data pad region to have a shape protruding from the surface using the fifth photoresist.

In the forming of the horizontal common voltage line, the second transparent electrode and the metal electrode are etched using a fifth photoresist, and the second transparent electrode and the metal electrode are positioned in the exposed area around the gate pad area and the data pad area. Removing, ashing the fifth photoresist to form only the horizontal common voltage line region, the gate pad region, and the data pad region in an island shape, and etching the metal electrode exposed to the outside of the fifth photoresist. It may include forming only the common voltage line region, the gate pad region, and the data pad region such that the metal electrode is present.

The horizontal common voltage line may be disposed in a horizontal direction adjacent to the gate line formed on the lower substrate.

Between the step of forming the thin film transistor and the step of forming the protective layer, the step of forming a planarization layer covering the transistor may be further included.

The present invention has the effect of providing a liquid crystal display device that can be applied to a large television, etc. by manufacturing a liquid crystal panel in a transverse electric field mode capable of improving transmittance and reducing a driving voltage by a 4 mask process or a 5 mask process, and a manufacturing method thereof. have.

1 is a block diagram schematically showing a liquid crystal display device.
FIG. 2 is a circuit diagram schematically showing a sub-pixel shown in FIG. 1;
3 is a plan view of a sub-pixel according to the first embodiment of the present invention.
4 to 17 are process flow charts based on the cross-sectional structures of areas A1-A2 and A2-A3 shown in FIG. 3;
18 is a cross-sectional structural view of FIG. 17 according to another embodiment.
FIG. 19 is a cross-sectional structure diagram showing areas A1-A2 and A2-A3 shown in FIG. 3 according to a second embodiment of the present invention.

Hereinafter, specific details for carrying out the present invention will be described with reference to the accompanying drawings.

<First Example>

1 is a block diagram schematically illustrating a liquid crystal display device, and FIG. 2 is a circuit configuration diagram schematically illustrating a sub-pixel illustrated in FIG. 1.

1 and 2, the liquid crystal display device includes a timing control unit 130, a gate driving unit 140, a data driving unit 150, a liquid crystal panel 160, and a backlight unit 170.

The timing control unit 130 receives a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), a clock signal (CLK), and a data signal (DATA) from the outside. The timing control unit 130 controls the operation timing of the data driving unit 150 and the gate driving unit 140 by using timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. Since the timing control unit 130 may determine the frame period by counting the data enable signal of one horizontal period, the vertical synchronization signal and the horizontal synchronization signal supplied from the outside may be omitted.

The control signals generated by the timing control unit 130 include a gate timing control signal GDC for controlling the operation timing of the gate driving unit 140 and a data timing control signal DDC for controlling the operation timing of the data driving unit 150. ) May be included. The gate timing control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse (GSP) is supplied to a gate drive IC (Integrated Circuit) in which the first gate signal is generated.

The gate shift clock GSC is a clock signal commonly input to the gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the outputs of the gate drive ICs. The data timing control signal DDC includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), a source output enable signal (Source Output Enable, SOE), and the like. The timing control unit 130 supplies the data signal DATA together with the data timing control signal DDC to the data driver 150.

The gate driver 140 outputs a gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing control unit 130. The gate driver 140 supplies a gate signal to the liquid crystal panel 160 through the gate lines GL. The gate driver 140 is formed in an IC form or formed on the liquid crystal panel 160 in a gate in panel method.

The data driver 150 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing control unit 130, converts it into a gamma reference voltage, and outputs the sample. The data driver 150 supplies a data signal DATA to the liquid crystal panel 160 through the data lines DL. The data driver 150 is formed in the form of an IC.

The liquid crystal panel 160 includes a lower substrate on which a thin film transistor is formed, an upper substrate on which a color filter is formed, and a liquid crystal layer interposed therebetween. An alignment layer for setting a pre-tilt angle of the liquid crystal is formed on the lower substrate and the inner upper portion of the lower substrate. The lower polarizing plate is attached to the lower surface of the lower substrate, and the upper polarizing plate is attached to the upper surface of the upper substrate. The liquid crystal panel 160 is implemented in an IPS (In Plane Switching) mode or a FFS (Fringe Field Switching) mode. In addition, the liquid crystal panel 160 may be implemented in any form such as a transmissive liquid crystal display, a transflective liquid crystal display, and a reflective liquid crystal display.

The liquid crystal panel 160 displays an image in response to the gate signal supplied from the gate driver 140 and the data signal DATA supplied from the data driver 150. The liquid crystal panel 160 includes sub-pixels that control light provided through the backlight unit 170. One sub-pixel SP includes a thin film transistor TFT, a storage capacitor Cst, and a liquid crystal layer Clc.

The gate electrode of the thin film transistor TFT is connected to the gate line GL1 and the source electrode is connected to the data line DL1. The storage capacitor Cst has one end connected to the drain electrode of the thin film transistor TFT and the other end connected to the common voltage line Vcom. The liquid crystal layer Clc is formed between the pixel electrode 1 connected to the drain electrode of the thin film transistor TFT and the common electrodes 2 and Vcom connected to the horizontal common voltage line AVcom. The horizontal common voltage line AVcom is formed on the lower substrate of the liquid crystal panel 160 and is disposed in the same horizontal direction (or horizontal direction) as the gate lines. The horizontal common voltage line AVcom is formed of a low-resistance material to reduce RC (R is resistance-resistance, C is capacity-capacitance) delay, and is formed for each line like the gate lines.

The backlight unit 170 provides light to the liquid crystal panel 160. The backlight unit 170 includes a light-emitting diode (hereinafter, referred to as LED), an LED driver that drives the LED, a light guide plate that converts light emitted from the LED into a surface light source, and optical sheets for condensing and diffusing the light emitted from the light guide plate. . The backlight unit 170 may provide light to the liquid crystal panel 160 by using not only an LED but also other light sources.

Hereinafter, the present invention will be embodied with reference to sub-pixels formed on the liquid crystal panel 160.

3 is a plan view of a sub-pixel according to the first embodiment of the present invention, and FIGS. 4 to 17 are process flow charts based on the cross-sectional structures of areas A1-A2 and A2-A3 shown in FIG. 3.

As shown in FIG. 3, the sub-pixels according to the first embodiment of the present invention include a first data line DL1 disposed in a vertical direction y and a first gate line GL1 disposed in a horizontal direction x. ) And a horizontal common voltage line AVcom arranged in the horizontal direction x. The horizontal common voltage line AVcom is disposed to pass the upper or lower direction of the sub-pixel in the horizontal direction x. The horizontal common voltage line AVcom is formed for every line like the first gate line GL1.

The sub-pixel has a thin film transistor TFT connected to the first data line DL1 and the first gate line GL1. The sub-pixel has a pixel electrode 118 connected to the drain electrode of the thin film transistor TFT and a common electrode 116 connected to the horizontal common voltage line AVcom. The drain electrode and the pixel electrode 118 of the thin film transistor TFT are electrically connected through a contact hole CH. Since the horizontal common voltage line AVcom is formed directly on the common electrode 116, it is directly electrically connected without a contact hole.

As illustrated, the first data line DL1 has an inequality sign (<) inclined with respect to the central area of the sub-pixel. The horizontal common voltage line AVcom has a linear shape disposed in the horizontal direction x adjacent to the first gate line GL1. A first data pad part DP1 is formed at one end of the first data line DL1 and a first gate pad part GP1 is formed at one end of the first gate line GL1.

The pixel electrode 118 and the common electrode 116 have a finger portion having an inequality sign (<) inclined with respect to the central region of the sub-pixel as shown. The finger portions of the pixel electrode 118 and the common electrode 116 are formed so as to be non-overlapping in the transmission area TA of the sub-pixel.

Meanwhile, in the above description and drawings, the first data line DL1, the pixel electrode 118, and the common electrode 116 have an inclined slope similar to the shape of an inequality sign (<). However, this is only an example, and the first data line DL1, the pixel electrode 118, and the common electrode 116 may have a linear shape.

Hereinafter, a method of manufacturing the same will be described based on the cross-sectional structure of the area A1-A2 and the area A2-A3 shown in FIG. 3.

[First mask process: see FIGS. 3, 4 and 5]

A horizontal common voltage line area VCA, a thin film transistor area CHA, a transparent area TA, a gate pad area GPA, and a data pad area DPA are respectively defined on the lower substrate 110.

A gate metal 111 is formed on the lower substrate 110. The gate metal 111 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or an alloy thereof It may be, and may be formed as a single layer or multiple layers.

A first photoresist PR1 is formed on the gate metal 111, the first mask MM1 is aligned on the lower substrate 110, and ultraviolet rays are irradiated through the aligned first mask MM1. Exposure and development. The first mask MM1 is selected as a photo mask. The first mask MM1 has a blocking portion NOPN corresponding to the thin film transistor area CHA and the gate pad area GPA, and has a horizontal common voltage line area VCA, a transparent area TA, and a data pad area DPA. ), which has a transmission part OPN.

The first mask MM1 is removed and the lower substrate 110 is etched to form the gate electrode 111a on the thin film transistor region CHA, and at the same time, the gate pad electrode 111b is formed on the gate pad region GPA. To form. The gate electrode 111a becomes the gate electrode 111a of the thin film transistor TFT, and the gate pad electrode 111b becomes the first gate pad portion GP1.

[Second mask process: see FIGS. 3, 5 and 6]

An insulating layer 112, a semiconductor layer 113, and a source drain metal 114 are sequentially formed on the lower substrate 110. The insulating film 112 is selected from a silicon oxide film (SiOx) or a silicon nitride film (SiNx). The source drain metal 114 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or It may be an alloy, and may be formed as a single layer or multiple layers.

A second photoresist PR2 is formed on the source drain metal 114 positioned on the uppermost layer, and the second mask HM1 is aligned on the lower substrate 110, and exposed and developed. The second mask HM1 is selected as a halftone mask. The second mask HM1 has a semi-transmissive portion HOPN corresponding to the central area of the thin film transistor area CHA, has a blocking portion NOPN around it, and has a horizontal common voltage line area VCA and a transparent area TA. ) And the gate pad area GPA with a full-transmissive portion FOPN and a blocking portion OPN corresponding to the data pad area DPA.

The second mask HM1 is removed and the lower substrate 110 is etched to form an insulating layer 112, a semiconductor layer 113a, and a source drain metal 114a on the gate electrode 111a positioned on the thin film transistor region CHA. , 114b). At the same time, an insulating layer 112, a semiconductor layer 113b, and a source drain metal 114c are formed on the lower substrate 110 positioned on the data pad area DPA. As a result, a thin film transistor including a gate electrode 111a, a semiconductor layer 113a, a source electrode 114a, and a drain electrode 114b is formed on the lower substrate 110. Here, the data pad electrodes 113b and 114c including the semiconductor layer 113b and the source drain metal 114c become the first data pad portion DP1.

[Third mask process: see Figs. 3 and 7 to 13]

A protective film 115, a first transparent electrode 116, and a third photoresist PR3 are sequentially formed on the lower substrate 110, the gate pad electrode 111b, and the source-drain metals 114a to 114c. The first transparent electrode 116 is formed of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), IGZO (Indium Gallium Zinc Oxide) or graphene. The same transparent conductive film is selected. The first transparent electrode 116 becomes a common electrode through a subsequent process.

The third mask MM2 is aligned on the lower substrate 110 and exposed and developed. The third mask MM2 is selected as a photo mask. The third mask MM2 includes a portion 117a of the thin film transistor area CHA, a portion 117b and 117c of the transmissive area TA of the sub-pixel, a portion 117d of the gate pad area GPA, and a data pad area. One having a transmissive portion OPN corresponding to the part 117e of (DPA) and a blocking portion NOPN corresponding to the remaining area is used.

When the third photoresist PR3 is developed, a portion 117a of the thin film transistor area CHA, a portion 117b and 117c of the transmissive area TA of the sub-pixel, and a portion 117d of the gate pad area GPA ) And a part 117e of the data pad area DPA are exposed and cover the rest of the area. At this time, the third photoresist PR3 positioned in the transmission area TA of the sub-pixel has an island shape and is divided into a plurality.

The lower substrate 110 is etched using the third photoresist PR3, and a portion 117a of the thin film transistor region CHA, a portion 117b and 117c of the transmissive region TA of the subpixel, and the gate pad region ( The protective layer 115 and the first transparent electrode 116 exposed through the part 117d of the GPA) and the part 117e of the data pad area DPA are removed. In this case, a portion 117a of the thin film transistor area CHA, a portion 117b and 117c of the transmissive area TA of the sub-pixel, a portion 117d of the gate pad area GPA, and a portion of the data pad area DPA The first transparent electrode 116 exposed through the side surface of (117e) becomes an undercut shape drawn in the inward direction.

A second transparent electrode 118 and a fourth photoresist PR4 are sequentially formed on the lower substrate 110 and the third photoresist PR3. At this time, the second transparent electrode 118 is connected to the drain electrode 114b of the thin film transistor and has a finger shape in the transmissive region TA of the sub-pixel and is divided into a plurality.

A part of the second transparent electrode 118 is located on the third photoresist PR3 as well as the source drain metal 114c above the gate pad electrode 111b of the gate pad area GPA and the source drain metal 114c of the data pad area DPA. ). The second transparent electrode 118 is formed of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), IGZO (Indium Gallium Zinc Oxide) or graphene. The same transparent conductive film is selected. The second transparent electrode 118 becomes a pixel electrode through a subsequent process.

The step difference (height) of the fourth photoresist PR4 is reduced by ashing the fourth photoresist PR4. Accordingly, the fourth photoresist PR4 includes a portion 117a of the thin film transistor region CHA, a portion 117b and 117c of the transmissive region TA of the subpixel, a portion 117d of the gate pad region GPA, and Only a part 117e of the data pad area DPA is left and removed. In addition, the second transparent electrode 118 formed on the third photoresist PR3 is exposed to the outside.

After etching the second transparent electrode 118 exposed on the third photoresist PR3 and etching the second transparent electrode 118 exposed on the third photoresist PR3, the third photoresist PR3 ) And the fourth photoresist PR4 are removed. Accordingly, the second transparent electrode 118 is located only in the thin film transistor area CHA, the sub-pixel transmission area TA, the gate pad area GPA, and the data pad area DPA, and the rest are removed.

When the third photoresist PR3 and the fourth photoresist PR4 are removed, the first transparent electrode 116 becomes a horizontal common voltage line region VCA, a thin film transistor region CHA, a transparent region TA, and a gate pad. It is formed separately on the area GPA and the data pad area DPA. In addition, the first transparent electrode 116 has a finger shape on the passivation layer 115 positioned in the transmissive area TA of the sub-pixel and is divided into a plurality. Here, since the first transparent electrode 116 is located on the island-shaped protective film 115 and the second transparent electrode 118 is located between the protective films 115 separated in an island shape, the first transparent electrode 116 And the second transparent electrode 118 are non-overlapping with each other.

[Fourth mask process: see Figs. 3 and 14 to 17]

A metal electrode 119 is formed in the form of a front electrode on the first transparent electrode 116 and the second transparent electrode 118 positioned at the top of the lower substrate 110, and a fifth photoresist on the metal electrode 119 (PR5) is formed. The metal electrode 119 is selected from one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu).

The fourth mask HM2 is aligned, exposed, and developed on the lower substrate 110. The fourth mask HM2 is selected as a halftone mask. The fourth mask HM2 has a blocking portion NOPN corresponding to the horizontal common voltage line area VCA, the gate pad area GPA, and the data pad area DPA, and has a gate pad area GPA and a data pad area. DPA) has a full-permeable portion (FOPN) corresponding to the periphery, and a semi-permeable portion (HOPN) corresponding to the remaining area is used. When the fifth photoresist PR5 is developed, the horizontal common voltage line area VCA, the gate pad area GPA, and the data pad area DPA protrude from the surface.

The second transparent electrode 118 and the metal electrode 119 are etched using the fifth photoresist PR5. Accordingly, the second transparent electrode 118 and the metal electrode 119 are removed from only the regions 120a to 120c exposed through the peripheries of the gate pad area GPA and the data pad area DPA, and the rest remain.

After removing a portion of the second transparent electrode 118 and the metal electrode 119, the fifth photoresist PR5 is ashing to lower the step (height) of the fifth photoresist PR5. Accordingly, in the fifth photoresist PR5, only the horizontal common voltage line area VCA, the gate pad area GPA, and the data pad area DPA exist in an island shape, and the rest are removed.

After the fifth photoresist PR5 is ashing, the metal electrode 119 exposed to the outside is etched. Accordingly, in the metal electrode 119, only the horizontal common voltage line area VCA, the gate pad area GPA, and the data pad area DPA exist, and the rest are removed.

After the metal electrode 119 is etched, the fifth photoresist PR5 is removed. When the fifth photoresist PR5 is removed, the metal electrode 119a located in the horizontal common voltage line region VCA is electrically connected to the first transparent electrode 116 serving as a common electrode, and is adjacent to each other along the horizontal direction. It is formed in a bar shape to be connected to the common electrode. The metal electrode 119a positioned in the horizontal common voltage line area VCA becomes a horizontal common voltage line AVcom.

The metal electrode 119b positioned in the gate pad area GPA is formed in an island shape to be electrically connected to the gate pad electrode 111b. The metal electrode 119b positioned in the gate pad area GPA becomes the first gate pad portion GP1 together with the gate pad electrode 111b. The metal electrode 119c positioned in the data pad area DPA is formed in an island shape to be electrically connected to the data pad electrodes 113b and 114c. The metal electrode 119c positioned in the data pad area DPA becomes the first data pad portion DP1 together with the data pad electrodes 113b and 114c.

In the above description, as an example, the metal electrodes 119b and 119c are positioned on the uppermost layers of the first gate pad portion GP1 and the first data pad portion DP1. However, according to another first embodiment illustrated in FIG. 18, the first gate pad portion GP1 and the metal electrodes 119b and 119c positioned on the uppermost layer of the first data pad portion DP1 are formed in the previous process. 3 It may be omitted depending on the shape of the photoresist PR3.

Meanwhile, in the structure of the first embodiment, since the CHF (Contact Hole Filling) process is performed in the third mask process, the first transparent electrode 116 serving as the common electrode and the second transparent electrode 118 serving as the pixel electrode are self-aligned. (Self-Align) is possible, so the distance between them can be formed within 1㎛.

Further, in the structure of the first embodiment, the first transparent electrode 116 serving as the common electrode and the second transparent electrode 118 serving as the pixel electrode are non-overlapping, and the driving voltage can be reduced as the positions thereof are close. In addition, since the thickness of the transmissive region TA is thin (the thickness and number of insulating films, etc. are small), the transmittance can be improved.

As described above, the first embodiment of the present invention provides a liquid crystal display device that can be applied to a large-sized television, and a method of manufacturing the liquid crystal panel in a transverse electric field mode capable of improving transmittance and reducing driving voltage through a 4-mask process. It works.

Meanwhile, in the first embodiment of the present invention described above, an example in which a liquid crystal panel in a transverse electric field mode capable of improving transmittance and reducing a driving voltage is manufactured by a four-mask process has been described. However, a liquid crystal panel in a transverse electric field mode capable of improving transmittance and reducing a driving voltage may be manufactured by a 5-mask process as follows.

The second embodiment of the present invention described below is compared with the first embodiment, except that a mask process is added to further form a planarization layer covering the thin film transistor between the second mask process and the third mask process. And the following processes are the same. Therefore, in the following second embodiment, a detailed description of the mask process required in the manufacturing method is omitted, and the structure is mainly described.

<Second Example>

FIG. 19 is a cross-sectional structural diagram showing areas A1-A2 and A2-A3 shown in FIG. 3 according to a second embodiment of the present invention.

19, on the lower substrate 110, a horizontal common voltage line area (VCA), a thin film transistor area (CHA), a transmissive area (TA), a gate pad area (GPA), and a data pad area (DPA) are Each is defined.

A gate electrode 111a and a gate pad electrode 111b are formed on the lower substrate 110. The gate electrode 111a and the gate pad electrode 111b are a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be one selected from or an alloy thereof, and may be formed as a single layer or multiple layers. The gate electrode 111a and the gate pad electrode 111b are formed separately in the thin film transistor area CHA and the gate pad area GPA defined on the lower substrate 110. The gate electrode 111a becomes a gate electrode of the thin film transistor, and the gate pad electrode 111b becomes a first gate pad portion.

An insulating layer 112 is formed on the lower substrate 110. The insulating film 112 is selected from a silicon oxide film (SiOx) or a silicon nitride film (SiNx). The insulating layer 112 is formed separately in the horizontal common voltage line area VCA, the transmissive area TA, and the data pad area DPA.

First and second semiconductor layers 113a and 113b are formed on the insulating layer 112. The first and second semiconductor layers 113a and 113b may be selected from one of a Si series, an oxide series, a Grephene series including a carbon nanotube (CNT), a Nitride series, and an organic semiconductor series. The first and second semiconductor layers 113a and 113b are formed by being divided into the thin film transistor area CHA and the data pad area DPA defined on the lower substrate 110.

A source electrode 114a, a drain electrode 114b, and a source drain metal 114c are formed on the first semiconductor layer 113a. The source electrode 114a, the drain electrode 114b, and the source drain metal 114c are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper. It may be one selected from the group consisting of (Cu) or an alloy thereof, and may be formed as a single layer or multiple layers. The source electrode 114a, the drain electrode 114b, and the source drain metal 114c are formed separately in the thin film transistor area CHA and the data pad area DPA defined on the lower substrate 110. The second semiconductor layer and the source drain metals 113b and 114c become the first data pad.

A planarization layer 125 is formed on the lower substrate 110 to cover the source electrode 114a and the drain electrode 114b. The planarization layer 125 may be formed of an organic material such as polyimide, benzocyclobutene series resin, acrylate, and photoacrylate. The planarization layer 125 serves to uniformly and flatly form layers to be formed thereafter.

The planarization layer 125 is formed in the horizontal common voltage line area VCA, the thin film transistor area CHA, and the transmissive area TA. However, the remaining regions except for the horizontal common voltage line region VCA, the thin film transistor region CHA, and the transmission region TA are etched and removed. The planarization layer 125 has a thickness greater than that of the insulating layers formed below and is formed only in the horizontal common voltage line area VCA, the thin film transistor area CHA, and the transmissive area TA. Accordingly, the first transparent electrode 116 and the second transparent electrode 118 formed on the planarization layer 125 are formed at positions higher than the first gate pad portion and the first data pad portion.

A passivation layer 115 is formed on the planarization layer 125 and the lower substrate 110. The protective film 115 is selected from a silicon oxide film (SiOx) or a silicon nitride film (SiNx). The passivation layer 115 is formed to cover all of the horizontal common voltage line area VCA, the thin film transistor area CHA, the transmission area TA, the gate pad area GPA, and the data pad area DPA. However, the passivation layer 115 includes a portion 117a of the thin film transistor area CHA, a portion 117b and 117c of the transmission area TA of the subpixel, a portion 117d of the gate pad area GPA, and a data pad area. In addition to exposing a part 117e of the (DPA), it has a shape covering the rest of the area. In this case, the passivation layer 115 positioned in the transmissive region TA of the sub-pixel has an island shape and is divided into a plurality.

A first transparent electrode 116 is formed on the passivation layer 115. The first transparent electrode 116 is formed of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), IGZO (Indium Gallium Zinc Oxide) or graphene. The same transparent conductive film is selected. The first transparent electrode 116 becomes a common electrode. At this time, the first transparent electrode 116 positioned in the transmissive area TA of the sub-pixel has an island shape and is divided into a plurality. Therefore, the first transparent electrode 116 is on the island-shaped protective film 115, and the second transparent electrode 118 is on the planarization film 125 located between the protective films 115 separated in the island shape. Since it is formed, the first transparent electrode 116 and the second transparent electrode 118 are non-overlapping with each other.

A second transparent electrode 118 is formed on the planarization layer 125 exposed through the passivation layer 115. The second transparent electrode 118 is formed of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), IGZO (Indium Gallium Zinc Oxide) or graphene. The same transparent conductive film is selected. The second transparent electrode 118 becomes a pixel electrode. The second transparent electrode 118 is connected to the drain electrode 114b of the thin film transistor and has a finger shape in the transmissive region TA of the sub-pixel and is divided into a plurality. In addition, a part of the second transparent electrode 118 is positioned above the gate pad electrode 111b in the gate pad region GPA and on the source drain metal 114c in the data pad region DPA. That is, the second transparent electrode 118 is located only in the thin film transistor area CHA, the sub-pixel transmission area TA, the gate pad area GPA, and the data pad area DPA, and the rest are removed.

A metal electrode 119 is formed in the horizontal common voltage line region VCA defined on the lower substrate 110. The metal electrode 119 is selected from one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). The metal electrode 119 located in the horizontal common voltage line area VCA is electrically connected to the first transparent electrode 116 serving as a common electrode, and has a bar shape so as to be connected to the adjacent common electrode along the horizontal direction. Is formed. The metal electrode 119 positioned in the horizontal common voltage line area VCA becomes a horizontal common voltage line.

On the other hand, the structure of the second embodiment also performs a contact hole filling (CHF) process in the mask process following the formation of the planarization film as in the first embodiment, so the first transparent electrode 116 used as the common electrode and the first transparent electrode 116 used as the pixel electrode 2 Since the transparent electrodes 118 can be self-aligned, the distance between them can be formed within 1 μm.

In addition, in the structure of the second embodiment, the first transparent electrode 116 serving as a common electrode and the second transparent electrode 118 serving as the pixel electrode are non-overlapping, and the driving voltage can be reduced as their positions are close.

The second embodiment of the present invention provides a liquid crystal display device that can be applied to a large-sized television by manufacturing a transverse electric field mode liquid crystal panel capable of improving transmittance and reducing a driving voltage through a 5-mask process, and a method of manufacturing the same. It works.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above is in other specific forms without changing the technical spirit or essential features of the present invention by those skilled in the art. It will be appreciated that it can be implemented. Therefore, the embodiments described above are illustrative in all respects and should be understood as non-limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

130: timing control unit 140: gate driving unit
150: data driver 160: liquid crystal panel
170: backlight unit 110: lower substrate
VCA: horizontal common voltage line area CHA: thin film transistor area
TA: Transmissive area GPA: Gate pad area
DPA: Data pad area PR1 to PR5: First to fifth photoresist
116: first transparent electrode 118: second transparent electrode
119: metal electrode AVcom: horizontal common voltage line

Claims (13)

A lower substrate;
A thin film transistor formed on the lower substrate;
A protective film formed on the lower substrate and the thin film transistor, exposing the drain electrode of the thin film transistor, and having an island shape in a transmission region of the sub-pixel and divided into a plurality;
A common electrode partially formed on the passivation layer outside the transmissive region of the sub-pixel, and divided into a plurality of finger shapes on the island-shaped passivation layer disposed within the transmissive region of the sub-pixel;
A pixel electrode formed on the lower substrate, connected to a drain electrode of the thin film transistor, divided into a plurality of finger shapes within the transmissive region of the sub-pixel, and non-overlapping the common electrode;
A horizontal common voltage line disposed on a common electrode outside the transmission region of the sub-pixel; And
A gate pad portion and a data pad portion formed on the lower substrate,
The gate pad part
A gate pad electrode formed on the lower substrate, a transparent electrode formed on the gate pad electrode, and a metal electrode formed on the transparent electrode and formed of the same material as the horizontal common voltage line,
The data pad part
An insulating film formed on the lower substrate, a semiconductor layer formed on the insulating film, a source drain metal formed on the semiconductor layer, and a metal electrode formed on the source drain metal and made of the same material as the horizontal common voltage line. A liquid crystal display device comprising: a. The method of claim 1,
The horizontal common voltage line is
A liquid crystal display device, wherein the liquid crystal display device is disposed in a horizontal direction adjacent to the gate line formed on the lower substrate. delete The method of claim 1,
Formed between the transistor and the protective layer,
A liquid crystal display device further comprising a planarization layer covering the transistor. Forming a thin film transistor on a lower substrate;
Exposing the drain electrode of the thin film transistor and forming a protective layer divided into a plurality of islands in the transmission region of the sub-pixel;
Forming a finger shape and divided into a plurality of common electrodes on a protective film in the form of an island, which is partially formed on the passivation layer outside the transmissive region of the sub-pixel and is located in the transmissive region of the sub-pixel;
Forming a pixel electrode connected to the drain electrode of the thin film transistor, having a finger shape in the transmission region of the sub-pixel, divided into a plurality, and non-overlapping the common electrode; And
And forming a horizontal common voltage line disposed on a common electrode located outside the transmission region of the sub-pixel,
Forming the thin film transistor
Defining a horizontal common voltage line region, a thin film transistor region, a transmissive region, a gate pad region, and a data pad region on a lower substrate; and
A gate metal is formed on the lower substrate, a first photoresist is formed on the gate metal, and a gate electrode is formed on the thin film transistor region using a first mask, and a gate pad is formed on the gate pad region. Forming an electrode,
An insulating layer, a semiconductor layer, and a source drain metal are sequentially formed on the lower substrate, a second photoresist is formed on the source drain metal, and a second mask is used on the gate electrode located on the thin film transistor region. And forming the insulating layer, the semiconductor layer, and the source drain metal on the data pad area, and forming a data pad electrode including the insulating layer, the semiconductor layer, and the source drain metal on the data pad area. delete The method of claim 5,
Forming the protective layer and the common electrode comprises:
A first transparent electrode and a third photoresist are formed on the lower substrate, the gate pad electrode, and the data pad electrode, and a part of the thin film transistor area, a part of the gate pad area, and the data pad are formed using a third mask. Forming the protective layer divided into a plurality of islands and having the island shape in the transmission area of the sub-pixel while exposing a part of the area,
After etching using the third photoresist, a portion of the thin film transistor region, a portion of the transmissive region of the sub-pixel, a portion of the gate pad region, and a protective layer and a first transparent electrode exposed through a portion of the data pad region are formed. A method of manufacturing a liquid crystal display device comprising the step of removing. The method of claim 7,
The step of forming the pixel electrode
Sequentially forming a second transparent electrode and a fourth photoresist on the lower substrate and the third photoresist,
Ashing the fourth photoresist to remove a portion of the thin film transistor region, a portion of the transmissive region of the sub-pixel, a portion of the gate pad region, and a portion of the data pad region,
Etching the second transparent electrode exposed on the third photoresist, and removing the third photoresist and the fourth photoresist after etching the second transparent electrode exposed on the third photoresist Method of manufacturing a liquid crystal display device. The method of claim 8,
Forming the horizontal common voltage line
Forming a metal electrode in the form of a front electrode on the first transparent electrode and the second transparent electrode,
Forming a fifth photoresist on the metal electrode,
Aligning a fourth mask on the lower substrate and forming a region corresponding to the horizontal common voltage line region, the gate pad region, and the data pad region to have a shape protruding from the surface using the fifth photoresist A method of manufacturing a liquid crystal display device comprising a step. The method of claim 9,
Forming the horizontal common voltage line
Etching the second transparent electrode and the metal electrode using the fifth photoresist, and removing the second transparent electrode and the metal electrode positioned in an area exposed through the periphery of the gate pad area and the data pad area. Wow,
Ashing the fifth photoresist to form only the horizontal common voltage line region, the gate pad region, and the data pad region in an island shape;
And etching the metal electrode exposed to the outside of the fifth photoresist to form only the horizontal common voltage line region, the gate pad region, and the data pad region such that the metal electrode is present . The method of claim 5,
The horizontal common voltage line is
A method of manufacturing a liquid crystal display device, characterized in that it is disposed in a horizontal direction adjacent to the gate line formed on the lower substrate. The method of claim 5,
The method of manufacturing a liquid crystal display device further comprising forming a planarization layer covering the transistor between the forming the thin film transistor and the forming the protective layer. The method of claim 1,
The horizontal common voltage line is
A liquid crystal display device disposed in a horizontal direction adjacent to a gate line formed on the lower substrate, and having a region non-overlapping with the gate line in the horizontal direction.

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