CN100452305C - Control method for surface perfect of preparation region of silion single chip device - Google Patents
Control method for surface perfect of preparation region of silion single chip device Download PDFInfo
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- CN100452305C CN100452305C CNB2006100143034A CN200610014303A CN100452305C CN 100452305 C CN100452305 C CN 100452305C CN B2006100143034 A CNB2006100143034 A CN B2006100143034A CN 200610014303 A CN200610014303 A CN 200610014303A CN 100452305 C CN100452305 C CN 100452305C
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Abstract
The present invention relates to a technical control method for improving the perfection of the substrate slice surface of a silicon single crystal, which comprises the following implementation steps: (1) after the silicon wafer is polished and cleaned, the surface of the silicon wafer carries out oxidation treatment; the silicon wafer after polished and cleaned is soaked in pure water containing oxydol or ozone so that a clean oxidation layer of 3 to 5 nm is generated on the surface of the silicon wafer; the surface of the silicon wafer is sealed so that the silicon wafer is effectively protected and avoids contamination; (2) a scribing region carries out mingling, a misfit dislocation network is made; the regional stress of the device is released, and metal impurities at the region of the device are sucked. The present invention applies back seal to protect the silicon wafer and the scribing region to carry out re-mingling to manufacture the misfit dislocation network, etc. based on the technical characteristics of processing the substrate slice of the silicon single crystal to obtain silicon wafers with good surface perfection of the device region. The present invention which has the advantages of simple operation, low cost, high efficiency and no pollution without adding other equipment, can obviously improve device performance and improve the rate of finished products.
Description
Technical field
The present invention relates to the process of silicon single crystal flake processing, especially relate to a kind of control method of surface perfect of preparation region of silion single chip device.
Background technology
Silicon single crystal is the main backing material of present IC, and along with the integrated level of IC improves constantly, characteristic size constantly reduces, and requires more and more higher to the perfection of silicon chip surface.Because the particle on polished silicon wafer surface and metal impurities contamination can badly influence breakdown characteristics, interfacial state and minority carrier life time, particularly the MOS large scale integrated circuit influence to surperficial effect type is bigger, so evenness, defective, roughness, metal impurities contamination and the particle on polished silicon wafer surface had extremely strict requirement and control.
Intrinsic at present commonly used is absorbed the removal of carrying out metal impurities, need be by the heat treatment of 10-17h, time is long, efficient is low, cost and contamination have been increased, because the oxygen that intrinsic is absorbed molten condition is converted into the precipitation state, cause the silicon chip mechanical strength to reduce in addition, the major diameter silicon substrate is easily buckled, and long heat treatment can only be at the extension row that advances, and externally the absorption role of the contamination of Yanzhong and harmful substance is limited.Absorb for polycrystalline and damage, though effect obviously, the asymmetric of stress still easily makes the bending of major diameter silicon substrate, and the technology cost increases.
Summary of the invention
The objective of the invention is to overcome above-mentioned weak point, because the perfection difference in surface device zone causes the technical problem of device or IC inefficacy, provide a kind of control method of surface perfect of preparation region of silion single chip device for solving silicon single crystal flake.
Implementation of the present invention is as follows for achieving the above object:
A kind of process control method that improves silicon monocrystalline substrate sheet surface perfection, implementation step is:
(1) cleans the back at silicon wafer polishing oxidation processes is carried out on its surface, promptly after silicon wafer polishing cleans, silicon chip is soaked in the pure water that contains hydrogen peroxide or ozone, the content that adds hydrogen peroxide is 0.1~1%, or the feeding amount of ozone is 50~150ml/min, ventilation 10~15min; Make silicon chip surface generate oxide layer, silicon chip surface is sealed; It is 3~5nm that described silicon chip surface generates oxide layer;
(2) heavy doping is carried out in the subregion of scribe area, make the misfit dislocation network, discharge the device regional stress, and absorb the metal impurities of device area; Described heavy doping making misfit dislocation network is meant in device area doping process and mixes excessive levels of impurities to scribe area that doping content is 1 * 10
19Cm
-3~9 * 10
19Cm
-3The subregion of described scribe area is meant in scribe area apart from scribe area edge 0.05~0.1mm scope.
Research and analyse, metal impurities are pressed stress intensity and corresponding distribution behind high-temperature process in silicon substrate, dislocation and fault are areas of stress concentration, can absorb microdefect and metal impurities, according to this rule, after the silicon wafer polishing cleaning, soak silicon chip with the pure water that adds hydrogen peroxide or ozone etc., make the silicon chip surface accelerated oxidation generate clean oxide layer, oxidated layer thickness can reach 3-5nm, protects anti-the contamination; Pyroprocess median surface stress has the effect of absorbing metal impurities, carries out heavy doping at scribe area, introduces the mismatch network, and owing to the radius difference of major impurity phosphorus boron in the silicon and silicon atom, heavily doped region can produce a large amount of misfit dislocations, forms the region of high stress.
The invention has the beneficial effects as follows:
(1) add hydrogen peroxide or feeding ozone in the pure water of cleaning back and can promote surface generation oxide layer, environmentally safe is protected anti-the contamination, and silicon chip surface is had no side effect.
(2) make the misfit dislocation network at scribe area, discharge the device regional stress, and absorb the metal impurities of microdefect and device area, can obviously improve device performance, improve rate of finished products.
(3) with original process compatible, do not increase new operation, can finish the gettering of scribe area when mixing, method is simple, effect is remarkable.
Embodiment
Below in conjunction with preferred embodiment, to details are as follows according to embodiment provided by the invention:
Embodiment 1:
(1) silicon chip after the cleaning is put into the pure water that adds 0.1% hydrogen peroxide, places 3 minutes, and the surface generates the oxide layer of 3nm;
(2) open the diffusion window at scribe area, window edge is in 0.05~0.1mm scope apart from the scribe area edge, carries out all the window in the scribe area being mixed in the doping process in the subregion at every turn, makes scribe area form heavy doping, makes doping content reach 1 * 10
19Cm
-3, scribe area forms the misfit dislocation network, absorbs microdefect to 10
2Cm
-2, the absorption distance of microdefect is reached 60 μ m.
Embodiment 2:
(1) silicon chip after the cleaning is put into the pure water that feeds ozone, places 3 minutes, and the surface generates the oxide layer of 5nm; Ozone feeding amount is 50~150ml/min, ventilation 10~15min;
(2) open the diffusion window at scribe area, window edge is in 0.05~0.1mm scope apart from the scribe area edge, carries out all the window in the scribe area being mixed in the doping process in the subregion at every turn, makes scribe area form heavy doping, makes doping content reach 5 * 10
19Cm
-3, scribe area forms the misfit dislocation network, absorbs microdefect to 0.5 * 10
2Cm
-2, the absorption distance of microdefect is reached 75 μ m.
Embodiment 3:
(1) silicon chip after the cleaning is put into the pure water that adds 1% hydrogen peroxide, places 3 minutes, and the surface generates the oxide layer of 3.5nm;
(2) open the diffusion window at scribe area, window edge is in 0.05~0.1mm scope apart from the scribe area edge, carries out all the window in the scribe area being mixed in the doping process in the subregion at every turn, makes scribe area form heavy doping, makes doping content reach 9 * 10
19m
-3, scribe area forms the misfit dislocation network, absorbs microdefect to 0.4 * 10
2Cm
-2Below, the absorption of microdefect distance is reached 80 μ m.
Above-mentioned detailed description of the control method of surface perfect of preparation region of silion single chip device being carried out with reference to embodiment; be illustrative rather than determinate; can list several embodiment according to institute's limited range; therefore in the variation and the modification that do not break away under the general plotting of the present invention, should belong within protection scope of the present invention.
Claims (1)
1, a kind of process control method that improves silicon monocrystalline substrate sheet surface perfection, implementation step is:
(1) cleans the back at silicon wafer polishing oxidation processes is carried out on its surface, promptly after silicon wafer polishing cleans, silicon chip is soaked in the pure water that contains hydrogen peroxide or ozone, the content that adds hydrogen peroxide is 0.1~1%, or the feeding amount of ozone is 50~150ml/min, ventilation 10~15min; Make silicon chip surface generate oxide layer, silicon chip surface is sealed; It is 3~5nm that described silicon chip surface generates oxide layer;
(2) heavy doping is carried out in the subregion of scribe area, make the misfit dislocation network, discharge the device regional stress, and absorb the metal impurities of device area; Described heavy doping making misfit dislocation network is meant in device area doping process and mixes excessive levels of impurities to scribe area that doping content is 1 * 10
19Cm
-3~9 * 10
19Cm
-3The subregion of described scribe area is meant in scribe area apart from scribe area edge 0.05~0.1mm scope.
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CNB2006100143034A CN100452305C (en) | 2006-06-09 | 2006-06-09 | Control method for surface perfect of preparation region of silion single chip device |
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CN1870227A CN1870227A (en) | 2006-11-29 |
CN100452305C true CN100452305C (en) | 2009-01-14 |
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Families Citing this family (6)
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CN101752213B (en) * | 2008-12-08 | 2011-09-07 | 北京有色金属研究总院 | Low temperature heat-treatment process for eliminating water mist on silicon chip surface |
WO2010125942A1 (en) * | 2009-04-28 | 2010-11-04 | 株式会社Sumco | Method for cleaning silicon sludge |
CN101880609A (en) * | 2010-06-30 | 2010-11-10 | 国电光伏(江苏)有限公司 | Silicon wafer cleaning agent and use method thereof |
CN105932097A (en) * | 2016-05-13 | 2016-09-07 | 浙江晶科能源有限公司 | Silicon chip oxidation method |
CN109698256A (en) * | 2018-12-29 | 2019-04-30 | 无锡琨圣科技有限公司 | A kind of silicon chip surface oxidative system and method |
CN113793801B (en) * | 2021-09-07 | 2023-06-02 | 广东先导微电子科技有限公司 | Method for cleaning indium phosphide substrate wafer |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN86104069A (en) * | 1986-06-09 | 1987-02-11 | 电子工业部第四十四研究所 | The multiple impurity-absorbing technique of silicon and multiple impurity-absorbed silicon slice |
CN86102476A (en) * | 1986-04-10 | 1987-02-11 | 天津大学 | Reduce the pipeline electric leakage of bipolar device and the method for surface leakage |
-
2006
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN86102476A (en) * | 1986-04-10 | 1987-02-11 | 天津大学 | Reduce the pipeline electric leakage of bipolar device and the method for surface leakage |
CN86104069A (en) * | 1986-06-09 | 1987-02-11 | 电子工业部第四十四研究所 | The multiple impurity-absorbing technique of silicon and multiple impurity-absorbed silicon slice |
Non-Patent Citations (5)
Title |
---|
. . |
ULSI衬底硅单晶片清洗技术现状与展望. 刘玉岭,古海云,檀柏梅,桑建新.稀有金属,第25卷第2期. 2001 |
ULSI衬底硅单晶片清洗技术现状与展望. 刘玉岭,古海云,檀柏梅,桑建新.稀有金属,第25卷第2期. 2001 * |
集成电路制备中金属杂质与微缺陷自吸除. 刘玉岭.河北工学院学报,第2期. 1980 |
集成电路制备中金属杂质与微缺陷自吸除. 刘玉岭. 河北工学院学报,第2期. 1980 * |
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