CN100401470C - Method for controlling and removing fog-shaped micro-defect of silicon gas-phase epitaxial layer - Google Patents
Method for controlling and removing fog-shaped micro-defect of silicon gas-phase epitaxial layer Download PDFInfo
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- CN100401470C CN100401470C CNB2006100140411A CN200610014041A CN100401470C CN 100401470 C CN100401470 C CN 100401470C CN B2006100140411 A CNB2006100140411 A CN B2006100140411A CN 200610014041 A CN200610014041 A CN 200610014041A CN 100401470 C CN100401470 C CN 100401470C
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Abstract
The present invention discloses a method for controlling and eliminating fog-shaped micro defects of a silicon gas-phase epitaxial layer, which aims to provide a method for effectively eliminating fog-shaped micro defects and controlling the fog-shaped micro defects of a silicon gas-phase epitaxial layer under the condition that the cost and the complexity of technology and equipment are not increased. The method comprises the steps that a conventional chemical mechanical polishing method is used for double-face polishing processing and cleaning for a silicon substrate sheet; after pure water is finally used for cleaning in the cleaning process, oxydant is added in a cleaning groove for processing for 1 to 15 minutes; therefore, a clean SiO<2> oxidizing layer is formed on the surface of the whole silicon sheet; the thickness of the oxidizing layer is generally from 3 to 5 nm; then, the silicon sheet is put in an epitaxial furnace for epitaxial growth. In the process of growth, the thickness of the epitaxial layer can be larger than the preset thickness under the control; then, gas-phase polishing is used for eliminating the residual thickness. The method has the advantages of simple manufacturing technology, high work efficiency and no need of addition of additive equipment; the method is completely compatible with the conventional epitaxial technology. Besides, the effect of eliminating fog-shaped micro defects is very obvious.
Description
Technical field
The present invention relates to a kind of control and eliminate the method that fog-shaped micro-defect appears in silicon-phase epitaxial sheet surface.
Background technology
Silicon epitaxial wafer is original multiplex in ambipolar circuit and device, to obtain higher signal transmission rate.Along with developing rapidly of integrated circuit industry, except requiring two-forty, also electrical characteristics and the integrated level to IC proposed more and more high requirement, and this just requires further strict to the electrical characteristics that the epitaxial loayer that is used for preparing bipolar device possesses.MOS circuit and device can significantly improve integrated level, directly on the substrate polished silicon wafer, prepare and the MOS device is many originally, in the last few years, epitaxy technique is applied in the technology of MOS integrated circuit, and show strong further advantage: can effectively control the soft error of a particle, latch-up, reduce noise, improve electrical characteristics unanimity or the like, make and increase sharply with the integrated circuit proportion of silicon epitaxial wafer as substrate, therefore being suitable for the required silicon epitaxial wafer of deep submicron process will become the main flow of silicon materials development from now on, and so just quality and the performance to silicon epitaxial wafer proposed strict more requirement.
We find after deliberation: the silicon epitaxy layer fog-shaped micro-defect focuses mostly in epi-layer surface, this mainly is in the high temperature epitaxy growth, the solid solubility of the beavy metal impurity that harmfulness is very big in the system environments in silicon is bigger, it is big to add heavy metal atom radius ratio silicon atom, makes heavy metal atom concentrate on the lower epitaxial loayer top layer of energy.Epitaxial growth is reduced to low temperature by high temperature after finishing, and the solid solubility of heavy metal element this moment in silicon becomes minimum and (differ 1 * 10 as the solid solubility of Cu under high temperature and low temperature
6Times), thereby make heavy metal atom become the nuclearing centre of fog-shaped micro-defect in the epitaxial loayer superficial deposit.Beavy metal impurity is assembled on the epitaxial loayer top layer, the perfection of meeting heavy damage epi-layer surface, and the zone of device is also made on the epitaxial loayer top layer just, make device if use the epitaxial wafer that fog-shaped micro-defect occurs, the beavy metal impurity that then concentrates on the top layer can reduce minority carrier lifetime, increases leakage current, cause that ion puncture or soft breakdown, knot degeneration, transoid or the pipeline that causes leaking electricity make collector emitter break-through, MOS threshold voltage shift, capability of resistance to radiation decline or the like a series of device reliability problems that device is early stage, high temperature failure thereby cause.
For eliminating the harm of fog-shaped micro-defect, main method is exactly to reduce the pollution of beavy metal impurity in the epitaxial process, the source that just farthest cuts off heavy metal pollution.
Currently used process for vapor phase epitaxy is:
At first, substrate is through again chemical polishing of twin grinding, and every face 20～25 μ m that skim remove rough surface, to reduce stress and impurity, clean afterwards.Use again Br
2Gas or HCl gas are thrown substrate, remove impurity and polysilicon in the micro-crack.Afterwards, to the extension pedestal through vacuum (10
-1～10
-2Pa) high temperature (1350 ℃) is handled, and thoroughly to vapor away easy diffusion impurity, carries out epitaxial growth at last.
In growth course, require to improve the tube edge sealing, anti-locking system leaks gas, and improves the purity of hydrogen, reduces the content of oxygen and water.Though technological requirement is followed in strictness, many times also extremely do not proving effective.
For the epitaxial wafer that vaporific surface occurs, generally take following oxidation breakaway corrosion method to remedy: to obtain the 600nm oxide layer, float SiO with HF
2Layer falls epitaxial loayer 0.5 μ m thickness tubulation again through chemical corrosion again.SiO
2Layer has the nearly surface impurity effect of absorption.This method complex process, the cost height, and have side effect.
In addition, before epitaxial growth, implement the appearance that following method also can reduce fog-shaped micro-defect:
1. back of the body envelope substrate slice method: implement this method and be silicon chip back to be sealed and is fixed on the pedestal with the method for growth intrinsic silicon, to stop the beavy metal impurity that comes out by the silicon chip back side to pollute the growing system environment, but after temperature changes, easily make epitaxial wafer the stress defective occur because the coefficient of expansion of silicon chip and pedestal is inconsistent.
2. the back side polishing with substrate slice is mao method on sand surface, its purpose is, very high stress value can appear with the substrate slice back side after this method processing, and at high temperature, metallic atom is easy to the big region clustering of stress, therefore, and in epitaxially grown hot environment, the metallic atom of silicon chip front active area can be concentrated in the passive region of the back side, thereby improves the cleanliness factor of front epitaxial loayer.But implement this method, can make the unequal power distribution of silicon chip positive and negative, the alice distortion often appears under the high temperature action of epitaxy technique, and coarse surface, back side easy cleaning not, can retain a large amount of objectionable impurities and become severe contamination source in the epitaxial process, can not reach the effect of eliminating fog-shaped micro-defect well.
3. intrinsic is absorbed or oxygen precipitation absorption metal impurities.Make this method can reach desired effects, must expend time in, had a strong impact on operating efficiency, be not suitable for large-scale industrial production up to tens to hundreds of hour.
Therefore, under the prerequisite that does not increase great amount of cost and technology and equipment complexity, be a technical difficult problem that needs to be resolved hurrily how and find a kind of extension new technology that can effectively eliminate fog-shaped micro-defect.
Summary of the invention
The present invention be directed to and exist in the known silicon-phase epitaxial technology: can not effectively eliminate fog-shaped micro-defect and need the enforcing remedies method, though perhaps can reduce the appearance of fog-shaped micro-defect, but numerous and diverse, the inefficient technical matters of technology, and a kind of fog-shaped micro-defect of can effectively eliminating is disclosed, and it is with low cost, technology is simple, and the method compatible mutually with conventional epitaxy technique.
The present invention is achieved through the following technical solutions:
The method of a kind of control and elimination fog-shaped micro-defect of silicon gas-phase epitaxial layer is characterized in that comprising the steps:
(1) adopts cmp method that silicon substrate film is carried out twin polishing and process the cleaning after polishing afterwards;
(2) after the last pure water of cleaning process cleans, in rinse bath, add oxidizer treatment 1～15min, make the whole silicon wafer surface generate the SiO of one deck cleaning
2Oxide layer, thickness of oxide layer are 3～5nm;
(3) this length there is the silicon chip of clean oxide layer put into epitaxial furnace and carries out epitaxial growth.
Described oxidant is H
2O
2, H
2O
2The mass percent that accounts for pure water is 1-5%.
Described oxidant is O
3, Ventilation Rate is 500-1000ml/min.
In order to remove the heavy metal pollution that produces in the epitaxial process, in the outer layer growth process, the growth thickness of control epitaxial loayer carries out the gas phase polishing with hydrogen halide or halogen elementary gas to epitaxial wafer again greater than predetermined thickness 0.1～1 μ m, removes the reservation thickness of 0.1～1 μ m.Reserving thickness determines according to the situation of experiment slice.
Used hydrogen halide is HCl or HBr.
Used halogen elementary gas is Cl
2Or Br
2
The present invention has following technique effect:
1. the silicon substrate film of the present invention before to conventional epitaxy technique increases a step cleaningization processing, and obtains the technology of one deck cleaning oxide layer, through lot of experiments and definite.We put and study the back in order to a large amount of test datas and find, there are a large amount of dangling bonds in fresh processed silicon chip surface, these dangling bonds can be spontaneously absorption and from surrounding environment at a large amount of beavy metal impurity of silicon chip surface enrichment, grow a layer thickness simultaneously and be about the surperficial natural oxidizing layer of 3nm, this oxide layer is coated on the beavy metal impurity of absorption wherein, and becomes the important pollutant sources in the epitaxial process.This situation is only being carried out single-sided polishing and is being carried out in the epitaxial growth more serious substrate slice, because the affected layer at the silicon chip back side and crushable layer are very thick, make that dangling bonds density is bigger, unsaturated position is stronger, correspondingly to the absorption of metal or other type dopant and to be enriched in the effect on top layer stronger.This process can be verified in the test of the polishing fluid before and after the polishing being carried out metal ion content: the applied metal ion concentration is that the polishing fluid of ppb level polishes silicon chip, and to the polishing after polishing fluid again measure metal ion content, the result shows, metal ion content exceeds two orders of magnitude before using, this has shown that fully silicon chip is in put procedure, the interior absorption of the damage layer on its surface and crushable layer has also retained a large amount of metal impurities, and in polishing process, be discharged into gradually in the polishing fluid, cause the metal ion content of polishing fluid greatly to increase.Therefore, this method requires silicon substrate film is implemented twin polishing, with a large amount of removal damages and crushable layer, realizes glossy surface, to reduce the metal impurities that bring thus.Ensuing polished silicon wafer is carried out cleaning after, use oxidant to generate fast the SiO of one deck cleaning on the whole surface of silicon chip
2Oxide layer is to replace the natural oxidizing layer that has pollutant by the natural way growth.This layer oxide layer has following four significant feature effects:
(1) this oxide layer itself is clean, does not especially have the beavy metal impurity that can cause occurring fog-shaped micro-defect.This is because after implementing cleaning treatment, and the silicon substrate film surface is clean, but also does not break away from the clean environment of cleaning, and is just direct on the integral surface of silicon chip, forms fast layer of oxide layer with oxidant, so this oxide layer is the oxide layer of one deck cleaning.
(2) though this cleaning oxide layer thickness is little, and the 3～5nm that only has an appointment is thick, and structure is very fine and close, can play buffer action, thereby prevent that external environment from causing the pollution of metal impurities to silicon chip surface the metal impurities that exist in the surrounding environment.
(3) be used for carrying out the clean oxide layer that epitaxially grown front covers, before epitaxial growth, can directly be removed by the gas phase polishing, and the back side still can completely remain.This layer oxide layer that the back side keeps not only can play the effect of inhibition of self-doped effect in epitaxial process, and the SiO at the back side
2Clean microdefect and area of stress concentration that the stress that exists on-the Si interface and clean oxide layer are protected; can play the deimpurity effect of inhaling in the temperature-fall period after epitaxial growth; a small amount of metal impurities that positive extension top layer is remaining shift to the back side, so that it is higher more perfect to be used for the positive purity of fabricate devices.
(4) this method technology is simple, and high efficiency need not added extras, and is fully compatible with conventional epitaxy technique, and the effect of elimination fog-shaped micro-defect is very remarkable.
2. in epitaxial process, owing to reasons such as technology controlling and process, remaining a small amount of beavy metal impurity still can be deposited on the top layer of epitaxial loayer in the growing system, generates the situation of thinner heavy metal pollution layer.The present invention has increased the gas phase polishing process after epitaxial growth, thereby removes this layer heavy metal pollution layer, has further eliminated the generation of fog-shaped micro-defect.And the removal thickness of gas phase polishing is little, and the time is short, and technology is simple, and cost is low, and effect is remarkable, and prepared epitaxial loayer electrical characteristics are better.
Embodiment
Below in conjunction with specific embodiment to the detailed description of the invention.
The present invention, increases the silicon chip before the epitaxial growth is carried out the cleaningization processing and the epitaxial loayer after the growth is carried out the top layer lift-off processing on the basis of implementing conventional epitaxy technique for realizing goal of the invention.
Embodiment 1
Adopt conventional cmp method that silicon substrate film is carried out twin polishing and handle, carry out the cleaning after the conventional polishing afterwards.After the last pure water of cleaning process cleans, in rinse bath, add oxidant H
2O
2Process 1min, H
2O
2The mass percent that accounts for pure water is 5%, makes whole silicon chip surface generate the SiO of one deck cleaning
2Oxide layer.Carry out again afterwards conventional epitaxial growth.
The epitaxial wafer that said method obtains is through (NH
4)
2Cr
2O
7Show liquid processing 1min, observe no fog-shaped micro-defect, epitaxial wafer can directly use.
Embodiment 2
Adopt conventional cmp method that silicon substrate film is carried out twin polishing and handle, carry out the cleaning after the conventional polishing afterwards.After the last pure water of cleaning process cleans, in rinse bath, add oxidant H
2O
2Process 10min, H
2O
2The mass percent that accounts for pure water is 3%, makes whole silicon chip surface generate the SiO of one deck cleaning
2Oxide layer.Carry out conventional epitaxial growth afterwards.
The epitaxial wafer that said method obtains is through (NH
4)
2Cr
2O
7Show liquid processing 1min, observing has slight fog-shaped micro-defect.Then the growth thickness of control epitaxial loayer carries out the gas phase polishing with HBr to epitaxial wafer again greater than predetermined thickness 1 μ m in epitaxial process, removes the reservation thickness of 1 μ m.After the gas phase polishing, epitaxial wafer is again through (NH
4)
2Cr
2O
7Show liquid processing 1min, observe no fog-shaped micro-defect.
Embodiment 3
Adopt conventional cmp method that silicon substrate film is carried out twin polishing and handle, carry out the cleaning after the conventional polishing afterwards.After the last pure water of cleaning process cleans, in rinse bath, add oxidant H
2O
2Process 15min, H
2O
2The mass percent that accounts for pure water is 1%, makes whole silicon chip surface generate the SiO of one deck cleaning
2Oxide layer.Carry out conventional epitaxial growth afterwards.
The epitaxial wafer that said method obtains is through (NH
4)
2Cr
2O
7Show liquid processing 1min, observe no fog-shaped micro-defect, epitaxial wafer can directly use.
Embodiment 4
Adopt conventional cmp method that silicon substrate film is carried out twin polishing and handle, carry out the cleaning after the conventional polishing afterwards.After the last pure water of cleaning process cleans, in rinse bath, pass into O
315min, Ventilation Rate are 500ml/min.Make the whole silicon wafer surface generate the SiO of one deck cleaning
2Oxide layer.Carry out conventional epitaxial growth afterwards.
The epitaxial wafer that said method obtains is through (NH
4)
2Cr
2O
7Show liquid processing 1min, observing has slight fog-shaped micro-defect.Then the growth thickness of control epitaxial loayer is used Cl again greater than predetermined thickness 0.1 μ m in epitaxial process
2Epitaxial wafer is carried out the gas phase polishing, remove the reservation thickness of 0.1 μ m.After the gas phase polishing, epitaxial wafer is again through (NH
4)
2Cr
2O
7Show liquid processing 1min, observe no fog-shaped micro-defect.
Embodiment 5
Adopt conventional cmp method that silicon substrate film is carried out twin polishing and handle, carry out the cleaning after the conventional polishing afterwards.After the last pure water of cleaning process cleans, in rinse bath, pass into O
310min, Ventilation Rate are 800ml/min.Make the whole silicon wafer surface generate the SiO of one deck cleaning
2Oxide layer.Carry out conventional epitaxial growth afterwards.
The epitaxial wafer that said method obtains is through (NH
4)
2Cr
2O
7Show liquid processing 1min, observing has slight fog-shaped micro-defect.Then the growth thickness of control epitaxial loayer is used Br again greater than predetermined thickness 0.5 μ m in epitaxial process
2Epitaxial wafer is carried out the gas phase polishing, remove the reservation thickness of 0.5 μ m.After the gas phase polishing, epitaxial wafer is again through (NH
4)
2Cr
2O
7Show liquid processing 1min, observe no fog-shaped micro-defect.
Embodiment 6
Adopt conventional cmp method that silicon substrate film is carried out twin polishing and handle, carry out the cleaning after the conventional polishing afterwards.After the last pure water of cleaning process cleans, in rinse bath, pass into O
31min, Ventilation Rate are 1000ml/min.Make the whole silicon wafer surface generate the SiO of one deck cleaning
2Oxide layer.Carry out conventional epitaxial growth afterwards.
The epitaxial wafer that said method obtains is through (NH
4)
2Cr
2O
7Show liquid processing 1min, observe no fog-shaped micro-defect, epitaxial wafer can directly use.
Although the disclosed method that relates to a kind of control and elimination fog-shaped micro-defect of silicon gas-phase epitaxial layer has been carried out special description with reference to embodiment, embodiment described above is illustrative and not restrictive, under the situation that does not break away from the spirit and scope of the present invention, all variations and modification are all within the scope of the present invention.
Claims (6)
1. the method controlling and eliminate fog-shaped micro-defect of silicon gas-phase epitaxial layer is characterized in that comprising the steps:
(1) adopts cmp method that silicon substrate film is carried out twin polishing and process the cleaning after polishing afterwards;
(2) after the last pure water of cleaning process cleans, in rinse bath, add oxidizer treatment 1～15min, make the whole silicon wafer surface generate the SiO of one deck cleaning
2Oxide layer, thickness of oxide layer are 3～5nm;
(3) this length there is the silicon chip of clean oxide layer put into epitaxial furnace and carries out epitaxial growth.
2. the method for control according to claim 1 and elimination fog-shaped micro-defect of silicon gas-phase epitaxial layer is characterized in that described oxidant is H
2O
2, H
2O
2The mass percent that accounts for pure water is 1-5%.
3. the method for control according to claim 1 and elimination fog-shaped micro-defect of silicon gas-phase epitaxial layer is characterized in that described oxidant is O
3, Ventilation Rate is 500-1000ml/min.
4. according to each the described control in the claim 1 to 3 with eliminate the method for fog-shaped micro-defect of silicon gas-phase epitaxial layer, it is characterized in that in the outer layer growth process, the growth thickness of control epitaxial loayer is greater than predetermined thickness 0.1～1 μ m, with hydrogen halide or halogen elementary gas epitaxial wafer is carried out the gas phase polishing again, remove the reservation thickness of 0.1～1 μ m.
5. the method for control according to claim 4 and elimination fog-shaped micro-defect of silicon gas-phase epitaxial layer is characterized in that used hydrogen halide is HCl or HBr.
6. the method for control according to claim 4 and elimination fog-shaped micro-defect of silicon gas-phase epitaxial layer is characterized in that used halogen elementary gas is Cl
2Or Br
2
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100140411A CN100401470C (en) | 2006-06-02 | 2006-06-02 | Method for controlling and removing fog-shaped micro-defect of silicon gas-phase epitaxial layer |
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|---|---|---|---|
| CNB2006100140411A CN100401470C (en) | 2006-06-02 | 2006-06-02 | Method for controlling and removing fog-shaped micro-defect of silicon gas-phase epitaxial layer |
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| CN100401470C true CN100401470C (en) | 2008-07-09 |
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| CN101740379B (en) * | 2008-11-27 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating surface defect of semiconductor device and semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5330876A (en) * | 1976-09-03 | 1978-03-23 | Akai Electric | Method of cleaning surface of semiconductor |
| JPH11329982A (en) * | 1998-05-07 | 1999-11-30 | Shin Etsu Handotai Co Ltd | Manufacture of epitaxial wafer and device for manufacturing semiconductor to be used for the same |
| CN1250224A (en) * | 1998-08-28 | 2000-04-12 | 三菱硅材料株式会社 | Method for cleaning semi-conductor substrate |
| CN1281588A (en) * | 1997-12-12 | 2001-01-24 | Memc电子材料有限公司 | Post-lapping cleaning process for silicon wafers |
| TW460965B (en) * | 2000-06-28 | 2001-10-21 | Taiwan Semiconductor Mfg | Cleaning method and device for silicon substrate |
-
2006
- 2006-06-02 CN CNB2006100140411A patent/CN100401470C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5330876A (en) * | 1976-09-03 | 1978-03-23 | Akai Electric | Method of cleaning surface of semiconductor |
| CN1281588A (en) * | 1997-12-12 | 2001-01-24 | Memc电子材料有限公司 | Post-lapping cleaning process for silicon wafers |
| JPH11329982A (en) * | 1998-05-07 | 1999-11-30 | Shin Etsu Handotai Co Ltd | Manufacture of epitaxial wafer and device for manufacturing semiconductor to be used for the same |
| CN1250224A (en) * | 1998-08-28 | 2000-04-12 | 三菱硅材料株式会社 | Method for cleaning semi-conductor substrate |
| TW460965B (en) * | 2000-06-28 | 2001-10-21 | Taiwan Semiconductor Mfg | Cleaning method and device for silicon substrate |
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