CN100449733C - Operation scheme for spectrum shift in charge trapping non-volatile memory - Google Patents

Abstract

A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles.

Description

Be used in the action design of the spectrum shift in the charge trap nonvolatile memory

Technical field

The invention relates to a kind of electrical erasable programmable nonvolatile memory, and more specifically, relevant for a kind of except promoting and reducing critical voltage (threshold voltage) action, still has a kind of bias arrangement (bias arrangement), to revise a kind of charge trap memory (charge trapping memory) of electric charge in the memory.

Background technology

Knowing the EEPROM and the flash memory (flash memory) of electrical erasable programmable nonvolatile memory (the electrically programmable and erasable non-volatile memory) technology of using electric charge (charge) memory structure, is to be widely used among the various modern Application.Wherein, in EEPROM and flash memory, be to use multiple memory cell (memory cells) structure.As integrated circuit (integrated circuits, during IC) volume-diminished, because expand its ability and simplify its processing procedure, so, just produce very big interest to the research of the memory cell structure that uses charge trap dielectric layer (charge trappingdielectric layers).For example, use the memory cell structure of charge trap dielectric layer, comprise the known NROM of industry, SONOS and PHINES.These memory cell structures are by electric charge is fallen into (trapping) in the charge trap dielectric layer as silicon nitride (silicon nitride), and store data.When negative electrical charge (negativecharge) was entrapped (trapped), the critical voltage of memory cell (threshold voltage) will increase.By negative electrical charge is removed, can reduce the critical voltage of memory cell from the charge trap layer.

Known SONOS device is to use extremely thin, for example less than at the bottom of the oxide of 3 nanometers (nanometers) (bottom oxide), and use a bias arrangement (biasarrangement) of directly wearing tunnel (direct tunneling) effect that can cause ditch track erasure (channelerase).Though use this technology can accelerate erasing speed, because pass through this influence of leaking (charge leakage) of electric charge at the bottom of oxide as thin as a wafer, so its electric charge confining force (chargeretention) is relatively poor.

It is a kind of as greater than 3 nanometers that the NROM device is to use, and generally be approximately at the bottom of the very thick oxide of 5 to 9 nanometers, to avoid charge loss.This technology is to use to bring to and wears tunnel and induce hot hole to inject that (band-to-band tunneling induced hot hole injection BTBTHH) comes eraseable memory unit, but not uses the above-mentioned tunnel of directly wearing.Yet hot hole injects and can damage oxide, and then is directed at the charge loss in the critical memory cell of height (high threshold cell), and the electric charge in low critical memory cell (low threshold cell) increases.In addition, (during (program and erase cycling),, can cause the erasing time to increase gradually in programming and erase cycles because the difficulty in the charge trap structure is wiped the accumulation of (hard-to-erase) electric charge.The accumulation of this electric charge is because hole decanting point (hole injection point) does not conform to each other with electronics decanting point (electroninjection point), so in erasing pulse (erase pulse) afterwards, still can lose portions of electronics.In addition, in wipe the sector of NROM flash memory device (sector), because the difference of handling procedure (for example channel length difference), so the erasing speed of each memory cell can be different.This different erasing speed can cause the distribution of a very big erase status Vt, and wherein the partial memory cell difficulty that can become is wiped, and partial memory cell can too be wiped (over-erased).Therefore, target critical value Vt window (object threshold Vt window) can be closed after a plurality of programmings and erase cycles, and can find that its endurance (endurance) is relatively poor.When this technology was applied on the more and more littler volume, it is more serious that this problem can become.

In addition, charge trap memory device can be caught (captures) electronics in the charge trap layer of two kinds of shallow and dark energy levels (shallow and deepenergy levels).The electronics of catching in shallow energy level can be than the electronics of catching in than deep energy level also run away easily (de-trap).So the electronics of shallow energy level is the major issue source of electric charge confining force.For keeping preferable electric charge confining force, the trapped electrons darker than preference.

Therefore, need a kind of can repeatedly the programming and wipe, be not used to delete the critical voltage that is increased after the erasing move of invalid storage unit and be not limited by, to improve the memory cell of electric charge confining force and reliability.

Summary of the invention

In view of this, the invention provides a kind of memory cell method of operating, and a kind of used framework of integrated circuit that comprises a memory cell, to improve its endurance and reliability.A charge trap type charge storing unit balance play below is described.The charge balance action comprises a bias arrangement, this bias arrangement comprises: to thin dielectric bottom (thin bottom dielectrics), can and/or directly wear tunnel from its grid (gate) to the raceway groove in hole, induce (inducing) electric field auxiliary electron to escape from (E-field assisted electron ejection), and it escape from institute's balance for the electric field auxiliary electron from grid to the charge trap structure; And apply a negative-gate voltage and (for example apply one-V with respect to substrate (substrate) _GOr positive underlayer voltage+V _SUB, or-V _GAnd+V _SUBCombination voltage), and apply an earthed voltage or low positive voltage is given its source electrode (source) and drain electrode (drain).For within the real time restriction, finish charge balance action of the present invention, in the raceway groove of memory cell, the voltage from the grid to the substrate, meeting is greater than-0.7 volt/nanometer, and in the example of following explanation, this voltage is for being lower than-1.0 volts/nanometer.Therefore, has a grid to one, oxide layer on one (top oxide layer), one charge trap layer (charge trapping layer), and one under on the raceway groove memory cell of oxide layer (bottom oxide layer), as the grid of charge balance action to substrate bias, be to approximate dielectric medium (top dielectric) greatly, charge trap dielectric medium (charge trapping dielectric), and the combination of dielectric medium (bottomdielectric) down, with the thickness of the represented effective oxide of nanometer, be multiplied by approximately-0.7 to-1.1 volts/nanometer again.

During charge balance action, grid inject (gate injection) and electronics run away (electron de-trapping) can operate together, to set up dynamic equilibrium or poised state (equilibrium state).From grid institute injected electrons, can eliminate and wipe the hole trap (hole traps) that a hot hole (hothole) is left over afterwards.Therefore, charge balance action can provide one very strong " electricity annealing " (electrical annealing), drop to minimum so that hot hole is injected the infringement that is produced.Reliability test shows the action of this charge balance simultaneously, can be reduced in greatly repeatedly to programme and wipe charge loss after (P/E) circulation.

According to a viewpoint of the present invention,, be to comprise: see through one first bias arrangement, reduce the critical voltage of memory cell in the method for this description technique; And, apply one the 3rd bias arrangement to the grid of memory cell, for example use a charge balance pulse relevant with first and second bias arrangement.If grid has a negative voltage with respect to substrate, then first of electronics to move be (injection of electronics grid) from grid to the charge trap structure, and electronics second to move be (electronics is injected into raceway groove) from the charge trap structure to substrate.On the other hand, if grid has a positive voltage with respect to substrate, then first of electronics move be from substrate to the charge trap structure, and electronics second to move be to grid from the charge trap structure.When critical voltage increased, first mobility of electronics can reduce, and when critical voltage reduced, first mobility of electronics can increase.In addition, when critical voltage increased, second mobility of electronics can increase, and when critical voltage reduced, second mobility of electronics also can reduce.These electronics move and can cause critical voltage to restrain towards a target critical value.This technology comprises a kind of bias arrangement more, this bias arrangement is the CHARGE DISTRIBUTION that is equilibrated in the charge trap layer, and when critical voltage during near target critical value, with be absorbed in a side of raceway groove or the electric charge on the opposite side different be, this bias arrangement can be fully across all length scope of memory cell channels.

According to another viewpoint of the present invention, the invention provides a kind of integrated circuit, this integrated circuit comprises a substrate, most memory cell on substrate and a control circuit that is connected to those memory cell.Wherein, each memory cell all has a critical voltage, and all comprises a charge trap structure, grid and source electrode in substrate and drain region.Control circuit comprises: a logic, with via one first bias arrangement, reduce critical voltage; One logic with via one second bias arrangement, promotes critical voltage; And a logic, be used for applying one the 3rd bias arrangement.The 3rd bias arrangement can cause one first electronics to move and one second electronics moves, and makes critical voltage towards the convergence of a convergence voltage.

Another embodiment of the present invention provides a kind of integrated circuit, and this integrated circuit comprises a substrate, most memory cell on substrate and a control circuit that is connected to those memory cell.Wherein, each memory cell all has a critical voltage, and all comprises a charge trap structure, grid and source electrode in substrate and drain region.Control circuit comprises: a logic with via one first bias arrangement, promotes critical voltage; And a logic, with via applying one second bias arrangement and one the 3rd bias arrangement, response one order reduces critical voltage.Via second bias arrangement, can reduce the critical voltage of memory cell.The 3rd bias arrangement can cause one first electronics to move and one second electronics moves, and makes critical voltage towards the convergence of a convergence voltage.

Another embodiment of the present invention provides a kind of integrated circuit, and this integrated circuit comprises a substrate, most memory cell on substrate and a control circuit that is connected to those memory cell.Wherein, each memory cell all has a critical voltage, and all comprises a charge trap structure, grid and source electrode in substrate and drain region.Control circuit comprises a logic, to apply one first bias arrangement.First bias arrangement can cause a hole to move, first electronics moves and one second electronics moves.In moved in the hole, the hole was to move to the charge trap structure, reduces the critical voltage of memory cell by this.Because movement of electric charges, so critical voltage can be towards the convergence of a convergence voltage.

In part embodiment of the present invention, the 3rd bias arrangement can remove the hole from the charge trap structure.For example, move to the electronics in the hole trap structure, can cause the electronics that falls into the hole and move in the charge trap structure to reconfigure.

In part embodiment of the present invention, can use a charge balance bias arrangement, with before all liftings or reducing the circulation of critical voltage,, be added to the charge trap structure with a balancing charge.For example, before all liftings or reducing the circulation of critical voltage, add the critical voltage that electronics can promote memory cell.In an embodiment of the present invention, in all liftings or reduce the critical voltage that is promoted before the circulation of critical voltage, be to be lower than to see through the minimum critical voltage that first bias arrangement and second bias arrangement can reach.In another embodiment of the present invention, the critical voltage that was promoted before the circulation of all liftings or reduction critical voltage is the programmed check voltage (program verify voltage) and erase check voltage (erase verify voltage) that is lower than memory cell.

According to one embodiment of the invention, the invention provides a kind of method of operating of memory cell, and this memory cell is to comprise a charge trap structure.This method comprises via one first bias arrangement, reduces the critical voltage of memory cell, and via one second bias arrangement, promotes the critical voltage of memory cell.After a period of time that the circulation of rising and descend through most critical voltages takes place, can apply one the 3rd bias arrangement again, with the CHARGE DISTRIBUTION of balancing charge structure of trap.When the charge balance action is applied on the time interval (intervals), charge balance action is to comprise a quite long pulse (be as in the following embodiments a length 1 second pulse), so that memory cell can reach poised state, or almost reach poised state.At the time interval that comprises between the charge balance action that applies the 3rd bias arrangement, be to be applicable to that by various the method for particular implementation example is determined.For example, can use a timer to decide time interval, use, carry out the charge balance action according to a regular time interval.Also can use the counter of the erase cycle that is used for programming to decide time interval.Moreover, also can use during device action, be used for indicating time lapse, comprise that various other key elements (factors) of start (power on) and shutdown (power off) decide time interval.

According to the embodiment of the invention, the invention provides a kind of memory cell method of operating.This method comprises: apply a program (procedure) (be generally and wipe), to set up a low critical condition, this state is to comprise that a meeting reduces by first bias arrangement of the negative electrical charge in the charge trap structure, and one second bias arrangement, and wherein second bias arrangement can be between grid and charge trap structure, and between the charge trap structure of raceway groove, induce balancing charge to wear tunnel.This method comprises one second program (being generally programming) more, and to set up a high critical condition in memory cell, this state is to comprise that a meeting increases the 3rd bias arrangement of the negative electrical charge in the charge trap structure.During being used for setting up the program of hanging down critical condition, apply among the embodiment of a charge balance pulse, this charge balance pulse length may fall short of, so that can't reach poised state, but than its length of preference to enough grow (as among the following embodiment used 50 to 100 milliseconds), so that it more can guarantee critical value, and the charge balance in the charge trap structure.

Charge balance described herein and scrub techniques can various different order be carried out.For example, can be from the erase command of response startup as the erasing move of sector erasing.By with charge balance action, as a part of wiping program, can be not that the short period interval that is bound to reach the charge balance pulse of poised state applies action, but still can be equilibrated at CHARGE DISTRIBUTION in the charge trap structure than preference.For example, before erasing move, can apply short comparatively speaking charge balance pulse, wherein because before hot hole injects, negative electrical charge influence in the charge trap structure, so charge balance pulse meeting causes bigger electron injection current, can strengthen erase status Vt by this and distribute, make the easier execution of erasing move.In addition, also can be after erasing move, just apply short comparatively speaking charge balance pulse, wherein because in charge balance structure, have more positive charge, so charge balance pulse meeting causes bigger electronics and injects, use neutralization (neutralize) hole trap, and improve the electric charge confining force.

For the flash memory device of NROM type, be to carry out sector erasing by the hot hole program of wiping.In embodiment of the present invention, can use a kind of new charge balance action of wiping program in conjunction with hot hole.Because the charge balance action has self-convergence property,, and reduce difficulty and wipe the critical voltage of (hard-to-erase)-memory cell so it helps to promote the critical voltage of wiping (over-erased)-memory cell.In addition, also the charge available balance play is strengthened the target critical voltage distribution of the low critical condition of crossing over memory cell array.For the memory cell of SONOS type, be in conjunction with the charge balance pulse, add FN and wear tunnel (FN tunneling) and carry out the program of wiping.

In conjunction with the another kind of method that charge balance and hot hole are wiped, be for during negative-gate voltage bias arrangement as charge balance, be open at the joint bias voltage (junctionbias) in source electrode and the drain electrode a little.In this example, hot hole injects, grid injects and electronics is run away and can be taken place simultaneously.Compared to known hot hole method for deleting, this hybrid-type method for deleting can preferable endurance of tool and preferable reliable characteristic.

The present invention proposes a kind of intelligent method for deleting.The user can design charge balance and the suitable order of wiping, to obtain good endurance and reliability.Charge balance action according to negative-grid is worn tunnel can be used in combination with hot hole injection or other bias arrangement, controls to obtain preferable erase status critical voltage, and acceptable erasing speed.Charge balance/hot hole is wiped and can be restrained the critical voltage that was used for eraseable memory unit and difficult eraseable memory unit simultaneously.

Charge balance action can be used to as an electric annealing steps, with in and hole trap, and improve the device reliability significantly.

During erasing move, can any order in conjunction with charge balancing method and method for deleting, also both can be opened simultaneously.

The embodiment of other method of the present invention uses the multiple bias configuration.Via first bias arrangement, promote the critical voltage of memory cell, and respond an order that reduces critical voltage, use second bias arrangement and the 3rd bias arrangement.Via second bias arrangement, reduce the critical voltage of memory cell.Wherein, the 3rd bias arrangement comprises a charge balance pulse, makes critical voltage towards a convergence voltage convergence.In part embodiment of the present invention, can after second bias arrangement, respond an order that reduces critical voltage, use the 3rd bias arrangement.In part embodiment of the present invention, can before second bias arrangement, respond an order that reduces critical voltage, use the 3rd bias arrangement.In part embodiment of the present invention, can respond the order of a reduction critical voltage after before second bias arrangement, use the 3rd bias arrangement.In the present invention again among other embodiment, the application time of charge balance the 3rd bias arrangement can with in conjunction with the time of second bias arrangement identical.

Another embodiment of the present invention provides an integrated circuit, and this integrated circuit comprises a substrate, most memory cell on substrate and a control circuit that is connected to those memory cell.Wherein, each memory cell all has a critical voltage, and all comprises a charge trap structure and the grid in substrate and source electrode and drain region.Control circuit comprises: a logic via one first bias arrangement, promotes critical voltage (programming); And a logic, response one order via using one second bias arrangement and one the 3rd bias arrangement, reduces critical voltage (wiping).Via second bias arrangement, can reduce the critical voltage of memory cell.The 3rd bias arrangement can move by balancing charge, so that critical voltage is restrained towards a target critical value.

In part embodiment of the present invention, can before promoting and reducing any circulation of critical voltage, use the charge balance bias arrangement, electric charge is added to the charge trap structure.For example, before promoting and reducing any circulation of critical voltage,, can promote the critical voltage of memory cell with the electronics in the equalitarian distribution method adding charge storing unit structure of trap.

According to a programmable method of the embodiment of the invention, be to comprise that one is heavily injected circulation (refillcycle), uses the electron trap frequency spectrum (spectrum) in the charge trap structure that changes storage arrangement.Heavily injecting circulation comprises: being used for making electronics after a short charge balance pulse of jumping out than shallow trap of charge trap structure, use a bias arrangement, to be increased in the negative electrical charge in the charge trap structure; And the repeated application bias arrangement, to increase the negative electrical charge in the charge trap structure.In addition, use one or more heavy injection circulation, increasing in the charge trap structure relative density, and keep high critical condition as programming action target than the electronics in the deep trap.The accurate electronics in shallow position can be than easier the escaping of the accurate electronics of deep-seated.After the charge balance pulse, critical voltage can descend a little, next uses the programming again (reprogram) of electric charge or heavily injects (refill), makes device get back to original programmed check critical potential standard.Repeat above-mentioned charge balance/heavily injection processing, the trap frequency spectrum is moved towards the direction of the accurate electronics of deep-seated.This phenomenon is called " the blue skew of frequency spectrum " (spectrumblue shift).Even for because of using a large amount of programmings and erase cycles to cause for the device of very big injury, this heavy injection is handled and also can be improved the electric charge confining force significantly.Therefore, heavily injecting to handle to provide a kind of effective action, to improve the electric charge confining force in charge trap memory device.Moreover, use heavy method for implanting, can be applied in end dielectric medium, charge trap structure and go up dielectric medium, and can not cause charge loss than thin dielectric layer.Help the device volume downsizing of charge trap memory device than thin dielectric layer.

Another embodiment of the present invention provides an integrated circuit, and this integrated circuit comprises a substrate, most memory cell on substrate and a control circuit that is connected to those memory cell.Wherein, each memory cell all has a critical voltage, and all comprises a charge trap structure and the grid in substrate and source electrode and drain region.Control circuit comprises a logic, with via an above-mentioned heavy injecting program, promotes critical voltage (programming).

The target critical value of charge balance action is to depend on following factors: via last dielectric medium, be tunnelled to the electric charge number of charge trap structure from grid, and via dielectric medium down, be tunnelled to the charge number purpose relative value of raceway groove from the charge trap structure.For a lower target critical value, be tunnelled to the injection current of raceway groove compared to electronics from the charge trap structure, can reduce electronics directly is tunnelled to the charge trap structure from grid injection current.In embodiments of the present invention, this reduction is by the grid material that uses the suitable high workload function of a kind of tool (work function), is limited in dielectric medium and wears tunnel and reach.

For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.

Description of drawings

Figure 1A is the reduced graph that illustrates a charge trap memory cell before carrying out any programming and erase cycles.

Figure 1B illustrated before carrying out any programming and erase cycles, and the electric charge tool that is added is evenly distributed, the reduced graph of a charge trap memory cell shown in Figure 1A.

Fig. 2 A is the reduced graph that illustrates a charge trap memory cell after a plurality of programmings and erase cycles.

Fig. 2 B illustrates after being evenly distributed electric charge, the reduced graph of a charge trap memory cell shown in Fig. 2 A.

Fig. 3 A is the reduced graph that illustrates the charge trap memory cell that electric charge is evenly distributed.

Fig. 3 B illustrates to be engaged in channel hot electron injection, the reduced graph of a charge trap memory cell as shown in Figure 3A.

Fig. 3 C illustrates to be engaged in to bring to wear tunnel and induce hot hole to inject, the reduced graph of a charge trap memory cell shown in Fig. 3 B.

Fig. 3 D illustrates to be engaged in electric charge and to be evenly distributed the reduced graph of a charge trap memory cell shown in Fig. 3 C.

Fig. 4 illustrates after a plurality of programmings and erase cycles, is used for changing a representational processing of the CHARGE DISTRIBUTION in the charge trap memory cell.

Fig. 5 illustrated before carrying out any programming and erase cycles, and electric charge is added a charge trap memory cell, and after a plurality of programmings and erase cycles, changed representative a processing of the CHARGE DISTRIBUTION in the charge trap memory cell.

Fig. 6 is the graph of a relation that illustrates a critical voltage and programming and erase cycles number, and relatively at the memory cell critical voltage that changes the CHARGE DISTRIBUTION front and back.

Fig. 7 is the graph of a relation that illustrates a critical voltage and programming and erase cycles number, and is presented at the consistency that changes CHARGE DISTRIBUTION memory cell critical voltage afterwards.

Fig. 8 is the graph of a relation that illustrates a critical voltage and programming and erase cycles number, and relatively changing and not changing under the situation of CHARGE DISTRIBUTION, reduces the erasing move effect of critical voltage.

Fig. 9 illustrates a threshold voltage variations and the graph of a relation of retention time, and does not carry out any programming and erase cycles, with the difference of the memory cells of carrying out a plurality of programmings and erase cycles.

Figure 10 illustrates a threshold voltage variations and the graph of a relation of retention time, and has relatively added electric charge before carrying out any programming and erase cycles, and after carry out the difference of the memory cell of a plurality of programmings and erase cycles again.

Figure 11 illustrated before carrying out any programming and erase cycles, electric charge is added a charge trap memory cell, and may programme and a time interval of erase cycles after, change representative a processing of the CHARGE DISTRIBUTION in the charge trap memory cell.

Figure 12 illustrates the simplification calcspar of an integrated circuit according to an embodiment of the invention.

Figure 13 illustrates a flow chart, is used for illustrating a method for deleting that comprises an equalizing pulse.

Figure 14 illustrates a flow chart, is used for illustrating another method for deleting that comprises an equalizing pulse.

Figure 15 illustrates a critical voltage and time relation figure, and different saturation factors when various different grid voltage relatively.

Figure 16 and Figure 17 illustrate critical voltage and time relation figure, and show that memory cell can respond the bias voltage convergence behavior that is used for changing the CHARGE DISTRIBUTION in the charge trap structure.

Figure 18 illustrates critical voltage and time relation figure, and shows the convergence behavior of the memory cell of the different channel lengths of tool.

Figure 19 illustrates tool rule to change the programming of multidigit unit memory cell of CHARGE DISTRIBUTION and the graph of a relation between erase cycles number and the critical voltage.

Figure 20 illustrates one not possess rule and change the programming of multidigit unit memory cell of CHARGE DISTRIBUTION and the graph of a relation between erase cycles number and the critical voltage.

Figure 21 illustrates relatively to possess or do not possess critical voltage difference and the graph of a relation between the retention time that rule changes the memory cell of CHARGE DISTRIBUTION.

Figure 22 is the reduced graph that illustrates the charge trap memory cell of a tool mixing bias voltage, and this mixing bias voltage can reduce the critical voltage and the CHARGE DISTRIBUTION that changes in the charge trap layer of memory cell simultaneously.

Figure 23 illustrates a critical voltage and time relation figure, is used for the different memory cell of mixing bias voltage of comparison tool.

Figure 24 and Figure 25 be illustrated before reducing the memory cell critical voltage and after, by the CHARGE DISTRIBUTION that changes in the charge trap layer, and the representativeness of action memory cell is handled.

Figure 26 illustrates ought reduce in the memory cell critical voltage, by mixing bias voltage that can change the CHARGE DISTRIBUTION in the charge trap layer simultaneously of application, and representative a processing of action memory cell.

Figure 27 illustrates a flow chart, is used for illustrating that a kind of tool according to the embodiment of the invention heavily injects the programming action of circulation.

Figure 28 illustrates critical voltage and heavily injects an embodiment of the programming action of circulation at tool, as the graph of a relation between the erasing time of charge balance pulse.

Figure 29 be illustrate critical voltage and be used for data shown in Figure 28 programming action embodiment heavily inject graph of a relation between the circulation.

Figure 30 is the graph of a relation that illustrates between charge balance pulsed erase time of programming action embodiment that critical voltage and tool heavily inject circulation.

Figure 31 be illustrate critical voltage and be used for data shown in Figure 30 programming action embodiment heavily inject graph of a relation between the circulation.

Figure 32 illustrates one to be used for illustrating that use heavily injects action and the device of programming, and need not heavily inject do action and the key diagram of the data retention performance of the device of programming.

Figure 33 is the simplification energy bitmap that illustrates a charge trap memory cell, is used for illustrating application idea in the present invention.

110: grid

120: oxide structure

130: the charge trap structure

131: electronics

140: end dielectric medium structure

The 150:n+ doped region

The 160:n+ doped region

The 170:p doped region

V _GATE: grid voltage

V _SOURCE: source voltage

V _SUBSTRATE: underlayer voltage

V _DRAIN: drain voltage

210: grid

220: oxide structure

230: the charge trap structure

231: electronics

232: electronics

240: oxide structure

The 250:n+ doped region

The 260:n+ doped region

The 270:p doped region

310: grid

311: electronics

320: oxide structure

330: the charge trap structure

331: electronics

332: electronics

333: the hole

334: the hole

335: electronics

340: oxide structure

The 350:n+ doped region

The 360:n+ doped region

The 370:p doped region

410: new memory cell

420: memory cells

430: eraseable memory unit

Do 440: programming and erase cycles finish?

450: apply bias arrangement as charge balance

510: new memory cell

515: apply bias arrangement as charge balance

520: memory cells

530: eraseable memory unit

Do 540: programming and erase cycles finish?

550: apply bias arrangement as charge balance

610: material point

620: material point

630: data set

640: data set

650: data set

660: data set

680: straight line

710: material point

720: material point

810: material point

820: material point

910: trajectory

920: data set

930: data set

1000: material point

1010: data set

1020: data set

1030: data set

1110: new memory cell

1115: apply bias arrangement as charge balance

1120: beginning wherein may be programmed and the time interval of erase cycles

Does 1140: time interval finish?

1150: apply bias arrangement as charge balance

1200: the charge trap memory cell array

1201: column decoder

1202: the character line

1203: row decoder

1204: the bit line

1205: bus

1206: sensing amplifier/data input structure

1207: bus

1208: bias arrangement supply voltage

1209: formula, wipe and charge balance bias arrangement state machine (possessing timer and programming and erase cycle counter)

1211: the data input line

1212: the data output line

1250: integrated circuit

1300: erase command (n=0)

1301: apply bias arrangement and inject to induce hot hole

1302: by check?

1303：n＝n+1

1304：n＝N？

1305: failure

1306: apply bias arrangement as charge balance

1307: by check?

1308: wipe and finish

1400: erase command (n=0)

1401: apply bias arrangement as charge balance

1402: apply bias arrangement and inject to induce hot hole

1403: by check?

1404：n＝n+1

1405：n＝N？

1406: failure

1407: apply bias arrangement as charge balance

1408: by check?

1409: wipe and finish

1505: common saturation voltage

1510,1520,1530,1540: material point

1610,1620,1630,1640,1650,1710,1720,1725,1730,1735,1740,1810,1820,1830,1840,1850,1910,1920,1930,1940,1950,1960,2010,2020,2030,2040,2050,2060,2110,2120,2125,2130,2140,2145: trajectory

2210: grid

2220: oxide structure

2230: the charge trap structure

2233: electronics

2240: oxide structure

The 2250:n+ doped region

2253: the hole

The 2260:n+ doped region

2263: the hole

The 2270:p doped region

2273: electronics

2310,2320,2330,2340,2350: trajectory

2410: new memory cell

2420: memory cells

2430: eraseable memory unit

2440: apply bias arrangement as charge balance

2510: new memory cell

2520: memory cells

2525: apply bias arrangement as charge balance

2530: eraseable memory unit

2610: new memory cell

2620: memory cells

2630: apply bias arrangement as charge balance

2700: program command (n=0, m=0)

2701: apply the bias arrangement that to induce electronics to inject

2702: by check?

2703：n＝n+1

2704：n＝N？

2705: failure

2706：m＝M？

2707: apply bias arrangement as charge balance

2708：m＝m+1

2709: programming is finished

2800,2801,2802,2803,2804,3000,3001,3002,3003,3004,3200,3201: trajectory

3300: raceway groove

3301: end oxide

3302: the trap layer

3303: go up oxide

3304: grid

3305: electronics

3306: inject barrier

3307: work functions

3308,3309: electronics

Embodiment

Figure 1A is the reduced graph that illustrates a charge trap memory cell.Substrate among the figure comprises n+ doped region (doped regions) 150 and 160 and a p doped region 170 between n+ doped region 150 and 160.Other parts of memory cell are included in dielectric medium structure (bottom dielectric structure) 140 at the bottom of on the substrate one, be positioned at a charge trap structure 130 on the end dielectric medium structure (end oxide), be positioned on the charge trap structure 130 one goes up dielectric medium structure (top dielectric structure) 120 (going up oxide) and is positioned at a grid (gate) 110 on the oxide structure 120.Wherein, the representative dielectric medium of going up comprises that thickness is approximately silicon dioxide of 5 to 10 nanometers (silicon dioxide) and silicon oxynitride (silicon oxynitride), or the similar material of other tool high-ks, for example Al ₂O ₃Representative dielectric medium down comprises that thickness is approximately the silicon dioxide and the silicon oxynitride of 3 to 10 nanometers, or the similar material of other tool high-ks.Representative charge trap structure comprises that thickness is approximately the silicon nitride of 3 to 9 nanometers (silicon nitride), or the similar material of other tool high-ks, for example similarly is Al ₂O ₃With HfO ₂Metal oxide.The charge trap structure can be one group of discontinuous charge trap material parcel (pockets) or particle (particles), or pantostrat as shown in the figure.Charge trap structure 130 has the sunken electric charge (trapped charge) by electronics 131 representatives.

For example, the memory cell of NROM type comprises that a thickness is approximately the end oxide of 3 to 10 nanometers, thickness and is approximately the charge trap layer of 3 to 10 nanometers and the last oxide that thickness is approximately 5 to 10 nanometers.The memory cell of SONOS type comprises that a thickness is approximately the end oxide of 1 to 3 nanometer, thickness and is approximately the charge trap layer of 3 to 5 nanometers and the last oxide that thickness is approximately 3 to 10 nanometers.

In part embodiment of the present invention, grid is to comprise having than the also high work functions of n type silicon essence work functions, or greater than the about material of 4.1eV, and can be greater than the material of 4.25eV than preference, for example, this grid is to comprise the material with 5eV.Representative grid material comprises the metal and the material of p type polyethylene (poly), TiN, Pt and other high workload functions.The other materials that is applicable to the higher work functions of embodiment of the invention tool comprises: as Ru, Ir, Ni, and the metal of Co; The metal alloy of Ru-Ti and Ni-T, metal nitride and the metal oxide of RuO2 for example, but be not limited to this.Compared to typical n type polysilicon (polysilicon)-grid, the grid material of high workload function can produce higher electrons tunnel and inject barrier (injection barrier).Be approximately 3.15eV with silicon dioxide as the injection barrier of the n type polysilicon bar utmost point of last dielectric medium.Therefore, the embodiment of the invention makes apparatus be higher than the material of the injection barrier of about 3.15eV, for example uses the material that is higher than about 3.4eV, and can reach the manufacturing materials that goes up dielectric medium as grid with the material that is higher than about 4.0eV than preference.For the p type polysilicon bar utmost point of dielectric medium on the tool silicon dioxide, it injects barrier and is approximately 4.25eV, and on the tool silicon dioxide memory cell of the n type polysilicon bar utmost point of dielectric medium, the convergence critical value of the memory cell that it produced can reduce about 2 volts.

Shown in Figure 1A, this memory cell is not carried out any programming and erase cycles, and sunken electric charge wherein is the result for manufacture of semiconductor.In this memory cell array, be trapped in the amount of charge in the memory cell because manufacture of semiconductor relation, in whole array, have sizable difference.

As general custom, used at this " programming " (programming), be the critical voltage that representative promotes a memory cell, " wipe " (erase) then representative reduces the critical voltage of a memory cell.Yet, the present invention comprises two kinds of products and method, one of them is to be the critical voltage of a memory cell of representative lifting for programming, and wiping is the critical voltage that representative reduces a memory cell, another is the critical voltage that representative reduces a memory cell for programming then, and to wipe be the critical voltage that representative promotes a memory cell.

Figure 1B illustrated before carrying out any programming and erase cycles, and the electric charge tool that is added is evenly distributed, the reduced graph of a charge trap memory cell shown in Figure 1A.On source electrode 150, drain electrode 160 and substrate 170, can apply 0 volt current potential.On grid 110, can apply-20 volts current potential, this current potential enough on the whole end oxide that is approximately 0.7 to 1.0 volt/nanometer or higher volt/nanometer, is induced an electric field (E-field).

This bias arrangement can be by the electron injection current of inducing from grid to the charge trap layer, and the electronics from the charge trap structure to raceway groove is jumped out electric current, make it reach a dynamic equilibrium or after grace time, reach balance, be equilibrated at the CHARGE DISTRIBUTION in the charge trap structure 130 by this, memory cell critical voltage wherein can converge to a target critical value, therefore can within whole channel length scope, reach electric charge and be evenly distributed.This bias arrangement is complete symmetry on the whole memory unit raceway groove.When before the applied bias voltage configuration, during memory cell tool a little charge, this bias arrangement can be with electric charge, and for example electronics 132, add charge trap structure 130.Yet, in the memory cell array of a whole single IC for both, before in being installed on the field, being programmed and wiping,, and be trapped in amount of charge in the charge trap structure because of pressure or other factors that processing procedure produced, have sizable difference.The bias arrangement meeting balance of Figure 1B has been trapped in the amount of charge in the whole storage cell array, makes it within a reasonable permissible range, and sets up a stable state.The target critical value of the bias arrangement shown in Figure 1B is to depend on that electron injection current and electronics jump out the equilibrium condition that electric current is reached balance.When under bias condition, the amount of charge in the charge trap structure of whole raceway groove reaches balance, and keeps being completely fixed when motionless, and this poised state will produce.When reaching the dynamic equilibrium condition, the critical voltage of-memory cell, just the function of the amount of charge in the charge trap structure is to depend on that oxide reaches the characteristic of oxide, grid and charge trap structure down.The electronics of jumping out from grid than preference is jumped out electric current and can be higher than institute's injected electrons injection current, uses the reduction target critical value.Than the reason of preference reduction target critical value, be because it can allow to use low voltage action memory cell during reading.Therefore, the embodiment of memory cell can use high workload function grid material, p+ doped polycrystalline silicon for example, or oxide material on the high-k, for example Al ₂O ₃, or both adopt together, to reach one than the low target critical value.

The size from the grid to the substrate bias according to charge balance pulse embodiment, be effective oxide thickness (the effective oxide thickness that depends on reference to the dielectric medium lamination, EOT), wherein the dielectric medium lamination is to comprise dielectric medium, charge trap structure and following dielectric medium, and EOT is the actual thickness after a dielectric constant at silicon dioxide (permittivity) normalization.For example, when the material of last dielectric medium, charge trap structure and following dielectric medium, when being respectively silicon dioxide, silicon nitride and silicon dioxide, this structure is called an ONO lamination again.For an ONO lamination, its EOT equals oxide thickness, adds up and down oxide thickness, adds nitride thickness and is multiplied by oxide dielectric constant again divided by the value of nitride dielectric constant gained.This moment, be used for the bias arrangement of charge balance pulse, can be defined as NROM type as described below and SONOS type memory cell:

1, in this illustrated NROM type memory cell, be for having memory cell greater than the following oxide thickness of 3 nanometers.For example, the EOT of dielectric medium lamination is 10 to 25 nanometers, and the thickness of following oxide is greater than 3 nanometers, directly wear tunnel to avoid the hole from substrate, grid wherein is-12 to-24 volts to substrate bias, divided by the voltage after the EOT is greater than 0.7 volt/nanometer, is approximately 1.0 volts/nanometer than preference, adds and subtracts the error of 10 percentages again.

The EOT of ONO in the NROM type memory cell calculates:

The minimum value maximum

Last oxide (dielectric constant=3.9) 5 nanometers 10 nanometers

SIN (dielectric constant=7) 3 nanometers 9 nanometers

Following oxide (dielectric constant=3.9) 3 nanometers 10 nanometers

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Summation 5+3*3.9/7+3=10 nanometer 10+9*3.9/7+10= 25 nanometers

2, in this illustrated SONOS type memory cell, be for having memory cell less than the following oxide thickness of 3 nanometers.For example, the EOT of dielectric medium lamination is 5 to 16 nanometers, and the thickness of following oxide is less than 3 nanometers, directly wear tunnel to allow the hole from substrate, grid wherein is-5 to-15 volts to substrate bias, divided by the voltage after the EOT is greater than 0.3 volt/nanometer, is approximately 1.0 volts/nanometer than preference, adds and subtracts the error of 10 percentages again.

The EOT of ONO in the SONOS type memory cell calculates:

The minimum value maximum

Last oxide (dielectric constant=3.9) 3 nanometers 10 nanometers

SIN (dielectric constant=7) 3 nanometers 5 nanometers

Following oxide (dielectric constant=3.9) 1 nanometer 3 nanometers

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Summation 3+3*3.9/7+1=5.7 nanometer 10+5*3.9/7+3=15.8 nanometer

For for the other materials of non-silicon dioxide in the lamination and non-silicon nitride, be with the same procedure of a dioxide dielectric constant divided by the thickness of the factor normalization material of nitride dielectric constant, calculate its EOT.

Fig. 2 A is the reduced graph that illustrates a charge trap memory cell after a plurality of programmings and erase cycles.Substrate among the figure comprises n+ doped region 250 and 260 and a p doped region 270 between n+ doped region 250 and 260.Other parts of memory cell are included in a oxide structure (oxide structure) 240 on the substrate, be positioned at a charge trap structure 230 on the oxide structure 240, be positioned at another oxide structure 220 on the charge trap structure 230 and be positioned at a grid 210 on the oxide structure 220.Most individual programmings and erase cycles can make electric charge, and for example electronics 231 and 232 has been trapped in the charge trap structure 230, and this is because the difference that is used for reaching in the bias arrangement of programming and wiping causes.Therefore, by using channel hot electron to inject, portions of electronics can be trapped in some position of charge trap structure, and as bring to and wear tunnel and induce hot hole injection (band-to-band tunneling induced hot hole injection, BTBTHH) method for deleting can not impact it.

Fig. 2 B illustrates changing CHARGE DISTRIBUTION, and uses after the bias arrangement shown in Figure 1B the reduced graph of a charge trap memory cell shown in Fig. 2 A.On source electrode 250, drain electrode 260 and substrate 270, can apply 0 volt current potential.On grid 210, can apply-20 volts current potential.This bias arrangement can be by set up electronics during programming and erase cycles, for example in the zone of electronics 232, removed polyelectron, and induce electron injection current to jump out electric current with electronics from the charge trap structure to raceway groove from grid to the charge trap layer, make it reach a dynamic equilibrium or after the enough long time, reach balance, and be equilibrated at the CHARGE DISTRIBUTION in the charge trap structure.Wherein, the critical voltage of-memory cell can converge to a target critical value, thereby can be evenly distributed electric charge within the whole length range of raceway groove.This bias arrangement is complete symmetry on the raceway groove of whole memory unit.

The method according to this invention is to comprise: via one first bias arrangement, reduce the critical voltage of memory cell; Via one second bias arrangement, promote the critical voltage of memory cell; And on the grid of memory cell, use three bias arrangement relevant with first and second bias arrangement.The 3rd bias arrangement can cause one first electronics to move and one second electronics moves.If grid has a negative voltage with respect to substrate, then this first electronics move be from grid to the charge trap structure, and second electronics to move be to substrate from the charge trap structure.If grid has a positive voltage with respect to substrate, then this first electronics move be from substrate to the charge trap structure, and second electronics to move be to grid from the charge trap structure.When critical voltage increased, this first electronics mobility can reduce, and when critical voltage reduced, this first electronics mobility can raise.When critical voltage increased, this second electronics mobility can raise, and when critical voltage reduced, this second electronics mobility can reduce.These electronics move and can cause critical voltage to restrain towards a target critical value.When critical voltage during near target critical value, this bias arrangement can be equilibrated at the CHARGE DISTRIBUTION in the charge trap layer within the whole memory unit channel length scope, but not only is absorbed on raceway groove one side or opposite side.

Fig. 3 A-3D illustrates a meeting after changing CHARGE DISTRIBUTION, stays the programming and the erase cycles of electric charge in a charge storing unit trap layer.

Fig. 3 A is the reduced graph that illustrates the charge trap memory cell that electric charge is evenly distributed.Substrate among the figure comprises n+ doped region 350 and 360 and a p doped region 370 between n+ doped region 350 and 360.Other parts of memory cell are included in a oxide structure 340 on the substrate, be positioned at a charge trap structure 330 on the oxide structure 340, be positioned at another oxide structure 320 on the charge trap structure 330 and be positioned at a grid 310 on the oxide structure 320.

Fig. 3 B and Fig. 3 C illustrate respectively to be used for programming and the example of the bias arrangement of eraseable memory unit.

Fig. 3 B illustrates to be engaged in channel hot electron (CHE) injection, the reduced graph of a charge trap memory cell as shown in Figure 3A.On source electrode 350, can apply 0 volt current potential.In drain electrode 360, can apply 5.5 volts current potential.On grid 310, can apply 8 volts current potential.This bias arrangement can make the channel hot electron as electronics 332, from the raceway groove p doped region 370, moves in the charge trap structure 330 near among the drain region that positive voltage applied.Electronics 331 is for after electronics injects, and is trapped in the electric charge example in the charge trap structure.Other bias arrangement able to programme (be used for setting up the bias arrangement of a high critical condition, or be used for the bias arrangement of the multiple high critical condition of multidigit metaaction) also can be applicable in the other embodiments of the invention.Wherein, representative program bias configuration comprises: second electronics that is started by raceway groove injects (channel initiatedsecondary electron injection, CHISEL), source terminal is injected (source sideinjection, SSI), the drain charge Avalanche Hot-Electron is injected (drain avalanche hotelectron injection, DAHE), the exciting substrate hot electron injection of pulse (pulse agitatedsubstrate hot electron injection, PASHEI), the postivie grid electric field is auxiliary wears tunnel (positive gate E-field assisted) (Fowler-Nordheim), and other bias arrangement.

Fig. 3 C illustrates to be engaged in to bring to wear tunnel and induce hot hole to inject, the reduced graph of a charge trap memory cell shown in Fig. 3 B.On grid 310, can apply-3 volts current potential.On source electrode 350, can apply 0 volt current potential.In drain electrode 360, can apply 5.5 volts current potential.This bias arrangement can make via bringing to the hole and wear the hot hole that tunnel injects, and as hole 334, the district near drain electrode 360 moves to charge trap structure 330.Wherein, hole 333 is after injecting, and is trapped in the electric charge example in the charge trap structure 330.Injected hole to be reducing the zone of the electron density in the charge trap layer therein, and incomplete regional identical with the injection electronics.Therefore therefore, through after repeatedly programming and the erase cycles, electron density can be accumulated in the charge trap structure, can influence the ability that it reaches low critical condition, and the endurance of restraint device.Other wipe bias arrangement (being used for setting up the bias arrangement of a low critical condition) is to comprise: do not have great electronics and inject, and can cause the performed auxiliary tunnel of wearing of negative voltage electric field under the voltage conditions that electronics runs away; At thin end oxide embodiment, the electronics of running away out from charge trap layer structure is directly worn tunnel, and tunnel is directly worn in the hole in the iunjected charge structure of trap; And other modes.

Fig. 3 D is the reduced graph that illustrates a charge trap memory cell shown in Fig. 3 C, and not illustrating among the figure to be influenced by institute's injected holes 333, but can influence the density that falls into electronics of attainable lowest critical value.Be similar to charge balance bias arrangement with reference to above-mentioned Figure 1B by application class, can change the CHARGE DISTRIBUTION in the charge trap layer, reduce by this or eliminate the too much electric charge that falls into.In this example, on grid, can apply one-20 volts current potential.Memory cell for the NROM type, it is the current potential from the grid to the substrate in raceway groove, numerical value divided by after the EOT that is made up of last dielectric medium, charge trap structure and following dielectric medium is greater than 0.7 volt/nanometer, and is approximately 1.0 volts/nanometer than preference.For the memory cell of SONOS type, its value is greater than 0.3 volt/nanometer, and is approximately 1.0 volts/nanometer than preference.One 0 volt current potential can be applied to source electrode 350, drain electrode 360 and in this example on the zone of the substrate 370 of shaping raceway groove.This bias arrangement can change the CHARGE DISTRIBUTION in charge trap structure 330.During changing CHARGE DISTRIBUTION, can remove too much electric charge, and/or add electronics.As the electric charge of electronics 311, can move to charge trap structure 330 from grid via a kind of as the auxiliary electric charge travel mechanism of wearing tunnel of electric field.This electric charge can remove the sunken hole in charge trap structure 330, and for example the hole 333.Be trapped in away from the electronics in the zone of hot hole injection region,, can have moved to p type district 370 from charge trap structure 330 via a kind of as the auxiliary electric charge travel mechanism of wearing tunnel of electric field as electronics 335.In fact, the electric field from the charge trap layer to raceway groove is auxiliary wears tunnel, can occur within the whole raceway groove scope length under the condition of this bias arrangement.This bias arrangement can be by set up electronics during programming and erase cycles, for example in the zone of electronics 333, removed polyelectron, and induce electron injection current to jump out electric current with electronics from the charge trap structure to raceway groove from grid to the charge trap layer, make it reach a dynamic equilibrium or after the enough long time, reach balance, and be equilibrated at the CHARGE DISTRIBUTION in the charge trap structure 330.Wherein, the critical voltage of memory cell can converge to a target critical value, thereby can be evenly distributed electric charge within the whole length range of raceway groove.This bias arrangement is complete symmetry on the raceway groove of whole memory unit.If bias arrangement is to be applied in a long pulse, continue 0.5 to 1.0 second, next reach stable or almost stable again, then its CHARGE DISTRIBUTION is can reach balance as shown in Figure 3A.If bias arrangement is to be applied in a short pulse, continue 1 to 50 millisecond, next CHARGE DISTRIBUTION can be inclined to balance, but possibly can't reach stable state.

Fig. 4 illustrates after a plurality of programmings and erase cycles, is used for changing a representational processing of the CHARGE DISTRIBUTION in the charge trap memory cell.New memory cell 410 and without any programming and erase cycles.In step 420 and 430, can be via first and second bias arrangement, programming and eraseable memory unit.In step 440, whether the time cycle of decision programming and erase cycles finishes.Time cycle wherein is the number of times that depends on programming and erase cycles.If the time cycle also finishes, can in step 420 and 430, can programme once more and eraseable memory unit.If the time cycle finishes, then in step 450, can change the CHARGE DISTRIBUTION in memory cell via one the 3rd bias arrangement.Wherein, for the memory cell of NROM type, it is the current potential from the grid to the substrate in raceway groove, divided by the numerical value after the EOT that is made up of last dielectric medium, charge trap structure and following dielectric medium, be greater than 0.7 volt/nanometer, and be approximately 1.0 volts/nanometer than preference.For the memory cell of SONOS type, its value is greater than 0.3 volt/nanometer, and is approximately 1.0 volts/nanometer than preference.

In various embodiments of the present invention, first bias arrangement and second bias arrangement, the both can cause that second electronics (CHISEL) that the auxiliary hot electron of wearing tunnel, injecting as channel hot electron (CHE) of one or more electric field injects, started by raceway groove injects and/or as bring to and wear the hot hole injection that tunnel hot hole (BTBTHH) injects.Various different bias arrangement may be used identical or different electric charge travel mechanism.Yet, even in different bias arrangement, there is one or more identical electric charge travel mechanism to exist, in first bias arrangement, second bias arrangement, all can on memory cell, apply different bias arrangement with each bias arrangement among the 3rd bias arrangement, and each bias arrangement all can have different voltage combinations on the end points of memory cell.

Partly have among the embodiment of particular bias voltage configuration in the present invention, its bias arrangement is as follows: the 3rd bias arrangement is with a negative potential with respect to cell source, drain electrode and substrate, is applied on the grid of memory cell; First bias arrangement can cause hot hole to inject, and second bias arrangement can cause hot electron to inject; First bias arrangement can cause hot hole to inject, and second bias arrangement can cause hot electron to inject, and the 3rd bias arrangement can cause the auxiliary tunnel of wearing of electric field; First bias arrangement can cause hot hole to inject, second bias arrangement can cause hot electron to inject, and the 3rd bias arrangement can be with one with respect to cell source, drain electrode, an and negative potential of substrate, be applied on the grid of memory cell, and memory cell for the NROM type, the size of this negative potential is greater than the 0.7 volt/nanometer that is approximately dielectric medium lamination EOT, and memory cell for the SONOS type, the size of this negative potential is greater than the 0.3 volt/nanometer that is approximately dielectric medium lamination EOT, and is about 1.0 volts/nanometer than preference.

Fig. 5 illustrated before carrying out any programming and erase cycles, and electric charge is added a charge trap memory cell, and after a plurality of programmings and erase cycles, changed representative a processing of the CHARGE DISTRIBUTION in the charge trap memory cell.This processing is similar to processing shown in Figure 4.Yet, carrying out any programming and erase cycles (step 520 and 530) before, in step 515, use an above-mentioned charge balance pulse, electric charge is added memory cell, can and/or wipe via formula by this, be lifted at the critical voltage in the memory cell.After the adding electric charge of execution in step 515, the critical voltage of this moment can be lower than the critical voltage in memory cell after wiping or programming, and is lower than the programmed check and the erase check voltage of memory cell.

Fig. 6 is the graph of a relation that illustrates a critical voltage and programming and erase cycles number, and relatively at the memory cell critical voltage that changes the CHARGE DISTRIBUTION front and back.Before the CHARGE DISTRIBUTION in changing the charge trap structure, memory cell can be carried out the programming and the erase cycles of different numbers earlier.Material point (datapoint) (hollow dots) 610 comprises data set 630,640,650 and 660.In data set 630, before each changed the CHARGE DISTRIBUTION action, memory cell can once be done 500 programmings and erase cycles.In data set 640, after through primary 1000 programmings and erase cycles, before each changed the CHARGE DISTRIBUTION action, memory cell can once be done 1000 programmings and erase cycles.In data set 650, after through primary 1000 programmings and erase cycles, before each changed the CHARGE DISTRIBUTION action, memory cell can once be done 10000 programmings and erase cycles.In data set 660, after through primary 10000 programmings and erase cycles, before each changed the CHARGE DISTRIBUTION action, memory cell can once be done 50000 programmings and erase cycles.Via data set 630,640,650 and 660, and increase after the number of programming and erase cycles, the critical voltage of the memory cell before an action that changes CHARGE DISTRIBUTION also can increase.Material point 620 (solid dot) is that representative is being used with reference to above-mentioned bias arrangement shown in Fig. 3 D, carries out CHARGE DISTRIBUTION memory cell afterwards.Illustrate among the figure except that data set 630, surpass all material points 610 of 3.8 volts the erase check voltage that is indicated by straight line 670.Data set 660 in fact is to surpass 5.3 volts the programmed check voltage that is indicated by straight line 680.Data set 630,640,650 and 660 is the different annoyance levels that are presented at the minimum critical voltage in the memory cell.Material point 620 is actions of display change CHARGE DISTRIBUTION, can be successfully with the critical voltage of the memory cell except carrying out the memory cell that surpasses 1000000 programmings and erase cycles, roll back and be lower than erase check voltage straight line 670.Show among the figure that if the number of programming and erase cycles increases, then the interference of the minimum critical voltage in memory cell also can increase before the action that is changing CHARGE DISTRIBUTION.Therefore, for producing the embodiment of data as shown in Figure 6, than preference in the time interval that about 1000 times programming and erase cycles take place, charge balance bias arrangement shown in the application drawing 3D, to guarantee the critical voltage that bias arrangement is reached of wiping, can be lower than the target critical value that sets by erase check current potential (straight line 670) by memory cell.

Fig. 7 is the graph of a relation that illustrates a critical voltage and programming and erase cycles number, and be presented at after each time 1000 programmings and erase cycles of using CHE and BTBTHH, on grid, apply a high negative voltage than long pulse 0.5 second, carry out the charge balance bias arrangement, the consistency of retainable memory cell critical voltage.Material point 720 (hollow dots) is the critical voltage of the memory cell of representative after an erasing move.As shown in FIG., in this example for the memory cell of nearly 1000000 times programming and erase cycles, the critical value after the program of wiping can keep below and be approximately 3.7 volts target critical value.

Fig. 8 is the graph of a relation that illustrates a critical voltage and programming and erase cycles number, and relatively changing and not changing under the situation of CHARGE DISTRIBUTION, reduces the erasing move effect of critical voltage.Material point 810 (solid dot) is the memory cell of representative before using negative electrical charge balance play change CHARGE DISTRIBUTION.Before the negative electrical charge balance play, even after repeatedly applying erasing pulse, also can't be with the critical voltage of memory cell, drop to and be lower than erasing pulse.Material point 820 (hollow dots) is the same memory cell of representative after a negative electrical charge balance play.Demonstration negative electrical charge balance play can be eliminated the influence by programming and the minimum critical voltage that erase cycles caused apace among the figure.

Fig. 9 illustrates a threshold voltage variations and the graph of a relation of retention time, and does not carry out any programming and erase cycles, with the difference of the memory cells of carrying out a plurality of programmings and erase cycles.Trajectory (trace) the 910th is represented a memory cells without any programming and erase cycles, and it is to have good electric charge confining force.Data set 920 and 930 is that representative is a negative electrical charge balance play with per 900 programmings and erase cycles, through a programming of 150000 times and a memory cell after the erase cycles.Data set 920 is that representative is closelyed follow after the negative electrical charge balance play, and the execution data keeps a cyclic test memory cell (cycled memorycell) of test (data retention test).Opposite, data set 930 is to represent before the negative electrical charge balance play, the execution data keeps a cyclic test memory cell of test.For the acceleration data keeps test, can on grid, apply one-10 volts current potential, can quicken the running away of sunken electronics in the charge storing unit structure of trap by this.Because it is the relatively poor data confining force of representative that bigger critical value changes, so illustrate the data confining force that the negative electrical charge balance play can improve memory cell among the figure.

Figure 10 illustrates a threshold voltage variations and the graph of a relation of retention time, and has relatively added electric charge before carrying out any programming and erase cycles, and after carry out the difference of the memory cell of a plurality of programmings and erase cycles again.Material point 1000 (solid dot) is to represent a memory cells of never carrying out any programming and erase cycles.Data set 1010 (hollow triangle), data set 1020 (square hollow) and data set 1030 (open diamonds) are to represent respectively through 150000 times programming and erase cycles, 200000 times programming and erase cycles and 1000000 times programming and the memory cell after the erase cycles.By the memory cell of data set 1010,1020 and 1030 representatives, can carry out a change CHARGE DISTRIBUTION action that comprises 1000 programmings and erase cycles each time.Data keeps the test meeting immediately following carrying out after one changes the CHARGE DISTRIBUTION action.As shown in FIG., by the periodic negative electrical charge balance play of using, through for the programming and the memory cell after the erase cycles of 150000 times programming and erase cycles, 200000 times programming and erase cycles and 1000000 times, can produce the data retention performance of quite stable for respectively.

Figure 11 illustrated before carrying out any programming and erase cycles, electric charge is added a charge trap memory cell, and may programme and a time interval of erase cycles after, change representative a processing of the CHARGE DISTRIBUTION in the charge trap memory cell.A new memory cell 1110 is not passed through any programming and erase cycles.In step 1115,, electric charge is added memory cell by applying a charge balance pulse.In step 1120, may programme and from then on the time interval of erase cycles begins for one.Programming wherein and erase cycles are performed by first and second bias arrangement.In step 1140, whether the decision time interval finishes.If time interval does not also finish, then proceed this time interval.If time interval finishes, then in step 1150,, change the CHARGE DISTRIBUTION in memory cell via one the 3rd bias arrangement.The 3rd bias arrangement is to comprise the pulse of tool with respect to the negative-gate voltage of substrate in the raceway groove territory, and can be by electron injection current from grid to the charge trap structure, and between charge trap structure and raceway groove, jump out electric current, and within whole channel length scope, balancing charge distributes.In part embodiment of the present invention, the pulse length of the pulse that applies is enough long, makes the memory cell critical voltage in memory cell array can converge to a target critical value, as continue 0.5 to 1.0 second in this example, is approximately-20 volts pulse height.In various embodiments of the present invention, time interval can be after the programming and erase cycles of any number, and/or finishes when memory cell can't be wiped free of.In another embodiment of the present invention, time interval is to be included in as comprising the machine of memory cell from power supply to, to closing this device, and opens time between the various power operation incidents of this device once more.By this way, can after opening machine, use the 3rd bias arrangement.

Figure 12 illustrates the simplification calcspar of an integrated circuit according to an embodiment of the invention.Integrated circuit 1250 comprises that one is positioned on the Semiconductor substrate, the memory cell array 1200 of using local (localized) charge trap memory cell to be realized.A column decoder (row decoder) the 1201st is connected to most the character lines of arranging along each row in memory cell array 1200 (wordlines) 1202.A row decoder (column decoder) the 1203rd is connected to most the bit lines of arranging along each row in memory cell array 1200 (bitlines) 1204.On bus 1205, have address and be supplied to row decoder 1203 and column decoder 1201.Sensing amplifier in step (block) 1206 and data input structure (sense amplifiers anddata-in structures) are to connect row decoder 1203 via bus 1207.Data can be via data input line (data-in line) 1211, from being positioned at the I/O port (input/output port) on the integrated circuit 1250, or from other inside or the outside data source of integrated circuit 1250, the data input structure of input in step 1206.Data can be via data output line (data-outline) 1212, and the sensing amplifier from step 1206 exports the I/O port that is positioned on the integrated circuit 1250 to, or other inside of integrated circuit 1250 or outside data destination.Bias arrangement state machine (bias arrangement state machine) 1209 can be controlled the bias arrangement supply voltage of how using as erase check voltage and programmed check voltage (bias arrangement supplyvoltages) 1208; Be used for formula and reduce first and second bias arrangement of memory cell critical voltage; And the 3rd bias arrangement that is used for changing the CHARGE DISTRIBUTION in the charge storing unit structure of trap.

As Figure 13 and shown in Figure 14, application of the present invention can be wiped program in conjunction with one, or in conjunction with being applicable to other programs of in memory cell, setting up a low critical condition.In Figure 13, start one by an erase command and wipe program (step 1300).An index (index) n that deducibility this moment is used to the program of wiping can be set to 0.In part embodiment of the present invention, erase command is corresponding to the flash memory device of related art techniques " quickflashing " (flash) sector erasing action.Biasing procedure can respond erase command and entry into service.In an embodiment of the present invention, the action of first in the biasing procedure is to use to comprise a bias arrangement hot hole being injected sector of memory cells (step 1301).For example, this action comprises: when the substrate zone ground connection of shaping memory cell channels, with about-3 to-7 volts bias voltage, be applied on the character line of sector; , be applied on the bit line that is connected to the memory cell drain electrode to+7 volts bias voltage with approximately+3; And, be applied on the source electrode line (source lines) that is connected to the sector storage cell source with the bias voltage of ground connection (ground).This action can be induced hot hole, and it is infused on one side near the charge trap structure of the drain terminal that is about to be wiped free of the sector storage unit.Whether using after hot hole injects bias arrangement, state machine or other logics can be carried out an erase check action, complete successfully with the erasing move of each memory cell of decision sector.Therefore, in next step, can determine memory cell whether by check action (step 1302).If by check, then index n can not increase progressively (step 1303) to memory cell, and can determine whether index has reached a predetermined maximum retry value N (step 1304).If index has reached maximum retry value, and not by check, then declaration proceeding failure (step 1305).If the decision index does not surpass maximum retry value in step 1304, then return step 1302, inject bias arrangement at this retry hot hole.If in step 1302 ,-memory cell then can be used one as the above-mentioned Fig. 1 of reference by check, can cause electron injection current and electronics to escape the charge balance bias voltage action (step 1306) of electric current simultaneously.The action of charge balance bias voltage comprises that a length is 10 to 100 milliseconds, for example is approximately 50 milliseconds negative-gate voltage pulse.CHARGE DISTRIBUTION and neutralization that this pulse can be equilibrated in the memory cell have fallen into the hole, and as mentioned above, are enough to improve memory cell endurance and reliability.After the action of charge balance bias voltage, can repeat erase check action (step 1307).If memory cell by check, is not then returned step 1303, increase progressively index n at this, and should retry or count out according to whether having reached that maximum retry value determines.If the decision memory cell is by check in step 1307, then the declaration program of wiping is finished (step 1308).

In Figure 14, start one by an erase command and wipe program (step 1400).The index n that deducibility this moment is used to the program of wiping can be set to 0.In part embodiment of the present invention, erase command is corresponding to the flash memory device of related art techniques " quickflashing " the sector erasing action.Biasing procedure can respond erase command and entry into service.In this example, after erase command, can use a charge balance bias arrangement, this bias arrangement can induce above-mentioned electron injection current and electronics to escape electric current (step 1401).The action of charge balance bias voltage comprises that a length is 10 to 100 milliseconds, for example is approximately 50 milliseconds negative-gate voltage pulse.When balancing charge distributes, this charge balance bias arrangement can make the amount of charge that is stored in the sector storage unit, converges to a target critical value.In other embodiments of the invention, for during each erase cycles, reach or almost reach the poised state that falls into electric charge, the charge balance bias arrangement can comprise that a length is 500 to 1000 milliseconds negative-gate voltage pulse.The pulse length of negative-gate voltage pulse is to decide according to following parameters: the permission time restriction of the embodiment of memory array, sector erasing program, applied hot hole inject bias arrangement length and other factors.The next one action of biasing procedure is to use one can induce hot hole, makes it inject the bias arrangement (step 1402) of sector of memory cells.For example, this action comprises: when the substrate zone ground connection of shaping memory cell channels, with about-3 to-7 volts bias voltage, be applied on the character line of sector; , be applied on the bit line that is connected to the memory cell drain electrode to+7 volts bias voltage with approximately+3; And, be applied on the source electrode line that is connected to the sector storage cell source with the bias voltage of ground connection.This action can be induced hot hole, and it is infused on one side near the charge trap structure of the drain terminal that is about to be wiped free of the sector storage unit.Because of the previous charge balance bias arrangement in the applying step 1401, thus hot hole inject bias arrangement can consistent result.Whether using after hot hole injects bias arrangement, state machine or other logics can be carried out an erase check action, complete successfully with the erasing move of each memory cell of decision sector.Therefore, in next step, can determine memory cell whether by check action (step 1403).If by check, then index n can not increase progressively (step 1404) to memory cell, and can determine whether index has reached a predetermined maximum retry value N (step 1405).If index has reached maximum retry value, and not by check, then declaration proceeding failure (step 1406).If the decision index does not surpass maximum retry value in step 1405, then return step 1402, inject bias arrangement at this retry hot hole.If in step 1403, memory cell then can be used one as mentioned above by check, can cause electron injection current and electronics to escape the second charge balance bias arrangement (step 1407) of electric current simultaneously.The action of charge balance bias voltage comprises that a length is 10 to 100 milliseconds, for example is approximately 50 milliseconds negative-gate voltage pulse.CHARGE DISTRIBUTION and neutralization that this pulse can be equilibrated in the memory cell have fallen into the hole, and as mentioned above, are enough to improve memory cell endurance and reliability.In part embodiment of the present invention, do not use the second charge balance bias arrangement of step 1407.The pulse length of charge balance bias voltage in step 1401 action, and the pulse length of the charge balance pulse action in step 1407, both may can be less than only using a pulse length among the charge balance bias voltage action embodiment.After the charge balance bias voltage action of execution in step 1407, can repeat erase check action (step 1408).If memory cell by check, is not then returned step 1404, increase progressively index n at this, and should retry or count out according to whether having reached that maximum retry value determines.If the decision memory cell is by check in step 1408, then the declaration program of wiping is finished (step 1409).

Figure 15 illustrates a critical voltage and time relation figure, wherein this time is for negative-grid charge balance bias pulse being applied to a low critical memory cell, for example one shown in Figure 1A and Figure 1B, the time span of brand-new memory cell (fresh cell) before programming and erase cycles.Four trajectories among the figure are material point 1510 (hollow triangle), material point 1520 (black triangle), material point 1530 (hollow dots) and the material points 1540 (solid dot) that comprise comparison tool different critical value convergency factor under various grid voltages.The length and width size ratio of the memory cell that this experiment is used is 0.5 micron/0.38 micron, and ONO (oxide-nitride thing-oxide) lamination size is 55 dusts

/ 60 dusts/90 dusts, and it has a p+ polysilicon gate (poly gate).Before any programming and erase cycles, can apply the pulse of a negative-grid charge balance, it is to comprise when source electrode, substrate and when draining all ground connection, a negative voltage on grid.Wherein, material point 1510 is corresponding to the voltage that applies-21 volts on grid; Material point 1520 is corresponding to the voltage that applies-20 volts on grid; Material point 1530 is corresponding to the voltage that applies-19 volts on grid; And material point 1540 is corresponding to the voltage that applies-18 volts on grid.Material point 1510,1520,1530 and 1540 critical voltage all can converge to a common saturation voltage 1505 that is approximately 3.8 volts.Higher negative-gate voltage can make critical voltage comparatively fast saturated.When the voltage that applies-21 volts on grid, an available pulse that is approximately 0.1 to 1.0 second allows critical value restrain fully.Other embodiments of the invention are to use a higher grid voltage, are saturated to the convergence required time of voltage to reduce critical voltage, or use a lower grid voltage, are saturated to the convergence required time of voltage to increase critical voltage.Thicker ONO lamination or thicker end oxide can increase critical voltage and be saturated to the convergence required time of voltage, maybe need use a higher negative-gate voltage in this example, make it make critical voltage saturated within the identical time.In like manner, thin ONO lamination or thin end oxide can reduce critical voltage and be saturated to the convergence required time of voltage, maybe need use a lower negative-gate voltage in this example, make it make critical voltage saturated within the identical time.

Figure 16 and Figure 17 illustrate critical voltage and time relation figure, and show that memory cell can respond the bias voltage convergence behavior that is used for changing the CHARGE DISTRIBUTION in the charge trap structure.Length and width size ratio in this used memory cell is 0.5 micron/0.38 micron.

Please refer to shown in Figure 16, wear tunnel via Fowler-Nordheim, the electronics of varying number is added the charge trap layer, can allow the critical voltage that does not also carry out the memory cell of any programming and erase cycles, rise to as shown in FIG. five trajectories 1610,1620,1630,1640 and 1650 startup critical potential standard indicate in various degree.After adding these electronics, the critical voltage of trajectory 1610 memory cell is approximately 5.3 volts, the critical voltage of trajectory 1620 memory cell is approximately 3.0 volts, the critical voltage of trajectory 1630 memory cell is approximately 2.4 volts, the critical voltage of trajectory 1640 memory cell is approximately 2.0 volts, and the critical voltage of trajectory 1650 memory cell is approximately 1.5 volts.Illustrate among the figure under the situation of source electrode, substrate and the ground connection all of draining, when applying one-21 volts negative voltage on grid, the critical voltage of these memory cell is to the variation relation of time.Applying a negative-gate voltage that is approximately a second,, all can converge to a common saturation voltage that is approximately 3.9 volts corresponding to the memory cell of trajectory 1610,1620,1630,1640 and 1650 with after inducing the charge balance action.

Please refer to shown in Figure 17ly, the critical voltage of the memory cell in four trajectories 1710,1720,1730 and 1740 all is to inject the hot carrier wave that injects with the raceway groove hot hole and do not have electricity (hot carrier charging) and set up with comprising channel hot electron.Wherein, the critical voltage of the memory cell in the trajectory 1710 can be promoted to and be approximately 4.9 volts.The critical voltage of the memory cell in the trajectory 1720 can be promoted to and be approximately 4.4 volts.The critical voltage of the memory cell in the trajectory 1730 can be promoted to and be approximately 3.3 volts.The critical voltage of the memory cell in the trajectory 1740 can be promoted to and be approximately 3.1 volts.Illustrate among the figure under the situation of source electrode, substrate and the ground connection all of draining, when applying one-21 volts negative voltage on grid, the critical voltage of the memory cell in these trajectories 1710,1720,1730 and 1740 is to the variation relation of time.Applying a negative-grid FN bias voltage that is approximately a second,, all can converge to a common saturation voltage that is approximately 3.7 volts corresponding to the memory cell of trajectory 1710,1720,1730 and 1740 with after inducing the charge balance action.

Figure 16 and Figure 17 illustrate pipe only to have the critical voltage of memory cell to be changed for the various dissimilar electric charge of different numerical value and move, applied bias voltage is enough when reduction causes very difficult eraseable memory unit and allows the unsettled sunken hole of memory cell reach sunken electronics, induce electron injection current and electronics to escape electric current and balancing charge distribution, make the critical voltage of memory cell, can fall back its convergence voltage.Other embodiments of the invention are to use a higher grid voltage, are saturated to the convergence required time of voltage to reduce critical voltage, or use a lower grid voltage, are saturated to the convergence required time of voltage to increase critical voltage.

Figure 18 illustrates critical voltage and time relation figure, and shows the convergence behavior of the memory cell of the different channel lengths of tool.Channel length corresponding to the memory cell of trajectory 1810 and 1820 is 0.38 micron, and is 0.50 micron corresponding to the channel length of the memory cell of trajectory 1830 and 1840.Channel hot electron is added the charge trap structure, can promote the critical voltage of the memory cell of trajectory 1810 and 1820.The critical voltage of the memory cell of trajectory 1820 can be promoted to and be approximately 5.2 volts.The critical voltage of the memory cell of trajectory 1840 can be promoted to and be approximately 5.6 volts.Memory cell corresponding to trajectory 1810 and 1830 is not passed through any programming and erase cycles.Illustrate among the figure under the situation of source electrode, substrate and the ground connection all of draining, when applying one-21 volts negative voltage on grid, the critical voltage of the memory cell in these trajectories 1810,1820,1830 and 1840 is to the variation relation of time.Corresponding to the memory cell of trajectory 1830 and 1840, can converge to a common saturation voltage that is approximately 3.8 volts.Corresponding to the memory cell of trajectory 1810 and 1820, can converge to a common saturation voltage that is approximately 3.5 volts.Figure 18 is the memory cell that illustrates the different channel lengths of tool, after response changes the bias voltage of CHARGE DISTRIBUTION, and the situation of the different convergence of trend voltage saturation.Yet the difference of channel length is not the main contributor for convergence voltage, so the difference on the whole storage cell array channel length can cause negative effect to the target critical value voltage that is distributed in the memory cell array.

Producing influence (channel roll-off effect) as the raceway groove that is illustrated on 1850, is the main contributor who has low critical voltage and low convergence voltage for tool than the memory cell of short channel length.Therefore, the channel length of dwindling memory cell can reduce critical voltage and the convergence voltage of memory cell when response changes the bias voltage of CHARGE DISTRIBUTION.In like manner, the channel length of lengthening memory cell can promote critical voltage and the convergence voltage of memory cell when response changes the bias voltage of CHARGE DISTRIBUTION.Other embodiments of the invention are to use a higher grid voltage, are saturated to the convergence required time of voltage to reduce critical voltage, or use a lower grid voltage, are saturated to the convergence required time of voltage to increase critical voltage.In addition, also can select the grid material of tool different operating function, to change target convergence critical value, wherein the material of higher work functions can reduce the convergence critical value.In addition, also optionally be used in oxide and more easily wear down the last oxide of tunnel in one of them of oxide and oxide material down, restrain critical value to change.Wherein, in last oxide, more easily wear the material of tunnel, can reduce the convergence critical value, and in last oxide, more can not wear the material of tunnel, then can promote the convergence critical value.

Figure 19 and Figure 20 are the key diagrams that illustrates a bias voltage validity jointly, and this bias voltage can be reached electric charge under the memory cell critical voltage and be evenly distributed keeping.

Figure 19 illustrates tool rule to change the programming of multidigit unit memory cell of CHARGE DISTRIBUTION and the graph of a relation between erase cycles number and the critical voltage.First bit can be programmed, and in trajectory 1910 (solid dot), can read first bit, and in trajectory 1920 (hollow dots), can read second bit.Second bit can be programmed, and in trajectory 1930 (black triangle), can read first bit, and in trajectory 1940 (hollow triangle), can read second bit.In trajectory 1950 (solid squares), can wipe and read first bit.In trajectory 1960 (square hollow), can wipe and read second bit.When programming a bit, in the time of a microsecond ,-grid voltage is 11.5 volts, and one of them drain voltage/source voltage is 5 volts, and another drain voltage/source voltage is 0 volt, and underlayer voltage is-2.5 volts.When carrying out programming, raceway groove can take place in the charge trap structure start second electronics and move (CHISEL).When wiping a bit, in one millisecond time, grid voltage is-1.8 volts, and one of them drain voltage/source voltage is 6 volts, and another drain voltage/source voltage is 0 volt, and underlayer voltage is 0 volt.When carrying out when wiping, hot hole can take place in the charge trap structure move.During erase cycles, use have source electrode, 50 milliseconds pulse of one-21 volts grid voltage of drain electrode and substrate ground connection, on memory, apply a negative gate bias that can be equilibrated at electric charge in the charge trap layer.As shown in FIG., critical voltage can be maintained within the well distributed scope that is approximately 100000 programmings and erase cycles.

Figure 20 illustrates the programming of a multidigit unit memory cell similar to Figure 19 and the graph of a relation between erase cycles number and the critical voltage.Yet different with Figure 19 is during erase cycles, not apply a negative-grid FN bias voltage that changes CHARGE DISTRIBUTION on memory cell.Therefore, repeatedly the programming and erase cycles after, also can increase by the interference that electric charge caused in the charge trap structure, and repeatedly the programming and erase cycles after, critical voltage also can increase.First bit can be programmed, and in trajectory 2010 (solid dot), can read first bit, and in trajectory 2020 (hollow dots), can read second bit.Second bit can be programmed, and in trajectory 2030 (black triangle), can read first bit, and in trajectory 2040 (hollow triangle), can read second bit.In trajectory 2050 (solid squares), can wipe and read first bit.In trajectory 2060 (square hollow), can wipe and read second bit.During being less than 10 programmings and erase cycles, wipe with stylized movements after critical voltage can significantly promote, and after 500 programmings and erase cycles, memory cell critical voltage after the erasing move of not using charge balance described herein action can be promoted to and is higher than 1 volt.

Figure 19 and Figure 20 illustrate to use a bias voltage that is used for being equilibrated at the CHARGE DISTRIBUTION in the memory cell jointly, reduce or eliminate wipe with stylized movements after memory cell in the key diagram of interference of accessible critical voltage.Other embodiments of the invention are to use a higher grid voltage, are saturated to the convergence required time of voltage to reduce critical voltage, or use a lower grid voltage, are saturated to the convergence required time of voltage to increase critical voltage.Other embodiments of the invention are increases or reduce the time that applies negative gate bias, to change the degree of critical voltage convergence convergence voltage.

Figure 21 illustrates relatively to possess or do not possess threshold voltage variations and the graph of a relation between the retention time that rule changes the memory cell of CHARGE DISTRIBUTION.Memory cell on trajectory 2110,2120,2130 and 2140 is all through 10000 times programming and erase cycles.Yet, be during the erase cycles of the memory cell on the trajectory 2110 and 2120 of trajectory 2125 at nominal, can apply a negative-grid pulse that is used for changing the CHARGE DISTRIBUTION in memory cell.And be on the memory cell on the trajectory 2130 and 2140 of trajectory 2145, can't apply the negative-grid pulse at nominal.Because it is the relatively poor data confining force of representative that bigger critical value changes, so illustrate the data confining force that balancing charge distribution action can improve memory cell among the figure.Keep test period, can on the grid of the memory cell of trajectory 2110 and 2130, apply one-7 volts negative-gate voltage, and on the grid of the memory cell of trajectory 2120 and 2140, applying one-9 volts negative-gate voltage.Because increase the influence of voltage, so between trajectory 2125, the memory cell of trajectory 2120 can be than the memory cell of trajectory 2110, the data confining force that tool is relatively poor.In addition, between trajectory 2145, the memory cell of trajectory 2140 can be than the memory cell of trajectory 2130, the data confining force that tool is relatively poor.

Figure 22 is the reduced graph that illustrates the charge trap memory cell of a tool mixing bias erase program, this mixing bias voltage can be by injecting in conjunction with hot hole injection current and electric field auxiliary electron and jumping out electric current, reduce the critical voltage of memory cell, and change the CHARGE DISTRIBUTION in the charge trap layer.This substrate comprise n+ doped region 2250 and 2260 and the substrate between n+ doped region 2250 and 2260 in a p doped region 2270.Other parts of memory cell are included in a oxide structure 2240 on the substrate, be positioned at a charge trap structure 2230 on the oxide structure 2240, be positioned at another oxide structure 2220 on the charge trap structure 2230 and be positioned at a grid 2210 on the oxide structure 2220.On grid 2210, can apply one-21 volts current potential.At source electrode 2250 and drain on 2260, can apply one 3 volts current potential, and substrate 2270 is a ground connection.During this mixes bias arrangement, have a plurality of electric charges and move generation.During a kind of electric charge therein moved, hot hole can and drain 2260 from source electrode 2250, moves to charge trap structure 2230, can reduce the critical voltage of memory cell by this.In another electric charge moved, electronics 2233 can move to charge trap structure 2230 from grid 2210.In another electric charge moved, electronics 2273 can move to source electrode 2250, substrate 2270 and drain 2260 from the charge trap structure.Electronics 2233 from grid 2210 to charge trap structure 2230 moves, and from charge trap structure 2230 to source electrode 2250, substrate 2270 and 2260 the electronics 2273 of draining move, both are for moving example from grid electronics outward.The potential voltage that is applied is to consider memory cell size and memory cell structure, institute's materials used and target critical value voltage or the like factor, becomes with practical embodiments.Above-mentioned electronics from the charge trap layer to substrate is jumped out electric current, and meeting be extended on whole channel length, and can be equilibrated at the CHARGE DISTRIBUTION in the charge trap structure.With the auxiliary tunnel of wearing of electric field, the hot hole injection current near the substrate of source electrode and drain region can increase the change rate of memory cell critical value, and reach by this erasing time faster compared to only.

Figure 23 illustrates a critical voltage and time relation figure, is used for the different memory cell of mixing bias voltage of comparison tool.One allows source electrode and drain electrode at the negative-grid charge balance bias voltage of earthing potential, can be applied on the memory cell of trajectory 2310.The critical voltage that can reduce memory cell simultaneously mixes bias voltage with of CHARGE DISTRIBUTION in being equilibrated at the charge trap layer, can be applied on the memory cell of trajectory 2320,2330,2340 and 2350.For the memory cell in trajectory 2320,2330,2340 and 2350, one-21 volts negative-gate voltage can be applied on its grid, and its substrate is a ground connection.In the memory cell of trajectory 2310, one 0 volt current potential can be applied in its source electrode and the drain electrode.In the memory cell of trajectory 2320, one 2.5 volts current potential can be applied in its source electrode and the drain electrode.In the memory cell of trajectory 2330, one 3 volts current potential can be applied in its source electrode and the drain electrode.In the memory cell of trajectory 2340, one 4 volts current potential can be applied in its source electrode and the drain electrode.In the memory cell of trajectory 2350, one 5 volts current potential can be applied in its source electrode and the drain electrode.Figure 23 illustrates when big voltage is applied to source electrode and drain upward, has than multi-hole and moves to the charge trap structure from source electrode and drain electrode, so can reduce critical voltage quickly.Therefore, applying impulse duration, zygotic induction hot hole injection current, electron injection current and electronics are jumped out the mixing bias voltage of electric current, and the erasing time is faster reached in available short erasing pulse.For example,, then must use a pulse of 0.5 to 1.0 second, could allow the critical voltage in memory cell as shown in figure 23 restrain if without the hot hole injection current.Use symmetry to be applied to the hot hole injection current that 3 volts current potential in source electrode and the drain electrode is induced, can within about 1 to 50 millisecond time, allow the critical voltage in memory cell as shown in figure 23 restrain.Other embodiments of the invention are to use a higher grid voltage, are saturated to the convergence required time of voltage to reduce critical voltage, or use a lower grid voltage, are saturated to the convergence required time of voltage to increase critical voltage.Other embodiments of the invention are increases or reduce the time that applies negative gate bias, to change the degree of critical voltage convergence convergence voltage.Other embodiments of the invention are to change source electrode and drain voltage, reduce the memory cell required time of critical voltage to change.

Figure 24 and Figure 25 be illustrated before reducing the memory cell critical voltage and after, by the CHARGE DISTRIBUTION that changes in the charge trap layer, and the representativeness of operation store unit is handled.

Representativeness processing meeting shown in Figure 24 is since a brand-new memory cell (step 2510) of also not passing through any programming and erase cycles.In step 2420 and 2430, memory cell can be programmed and wipe.In part embodiment of the present invention, before first programming and erase cycles, can carry out an action that is used for being equilibrated at the CHARGE DISTRIBUTION in the charge trap layer earlier.In step 2440, after programming and erase cycles, can carry out the action that is used for being equilibrated at the CHARGE DISTRIBUTION in the charge trap layer.Next, can repeat other programmings and erase cycles handles.Therefore, in representative shown in Figure 24 is handled, can after a programming and erase cycles, carry out an action that is used for being equilibrated at the CHARGE DISTRIBUTION in the charge trap layer.In part embodiment of the present invention, can after programming and erase cycles each time, carry out the action that is used for being equilibrated at the CHARGE DISTRIBUTION in the charge trap layer.

It is similar to processing shown in Figure 24 that representativeness shown in Figure 23 is handled.It also is the brand-new memory cell (step 2510) of also not passing through any programming and erase cycles since that representativeness shown in Figure 25 is handled.Yet, be used for changing and being equilibrated at the action (step 2525) of the CHARGE DISTRIBUTION in the charge trap layer, be to occur between memory cells (step 2520) and the eraseable memory unit (step 2530), but not in memory cells (step 2520) afterwards.In part embodiment of the present invention, before first programming and erase cycles, can carry out an action that is used for changing and being equilibrated at the CHARGE DISTRIBUTION in the charge trap layer earlier.

Figure 26 illustrates ought reduce in the memory cell critical voltage, by mixing bias voltage that can change the CHARGE DISTRIBUTION in the charge trap layer simultaneously of application, and operates a representative processing of a charge trap memory cell.It also is the brand-new memory cell (step 2610) of also not passing through any programming and erase cycles since that representativeness shown in Figure 26 is handled.In step 2610, memory cell can be programmed.In step 2630, after the programming action, can on memory cell, apply one and mix bias voltage.This mixing bias voltage can reduce the critical voltage and the CHARGE DISTRIBUTION that changes in the charge trap layer of memory cell simultaneously.In part embodiment of the present invention, before first programming and erase cycles, can carry out an action that is used for changing and being equilibrated at the CHARGE DISTRIBUTION in the charge trap layer earlier.

In part embodiment of the present invention, can the representativeness of bound fraction shown in Figure 24,25 and 26 handle.In an embodiment of the present invention, the CHARGE DISTRIBUTION in memory cell all can change after can reaching before eraseable memory unit.In various embodiments of the present invention, can before or after eraseable memory unit, apply the mixing bias voltage to memory cell.In another embodiment of the present invention, can before or after memory cell being applied the mixing bias voltage, change the CHARGE DISTRIBUTION in memory cell.

The present invention proposes the method for deleting of a kind of charge trap memory device (for example NROM or SONOS device).At first using a grid injecting voltage (gate injection) (is erase status with this device replacement (reset) Vg).Programming can be finished by several different methods, and for example channel hot electron (CHE), raceway groove start second hot electron (CHISEL) injection, FN wears tunnel, pulse excitation substrate hot electron (PASHEI) or other programs.Wipe and to finish by several different methods, for example bring to and wear that tunnel induces hot hole (BTBTHH) to inject (generally being used for the NROM device), the negative FN that is used for the SONOS device wears tunnel or other programs, and is to carry out in the mode of sector erasing action.During sector erasing action, can use an extra raceway groove erasing move (using negative-gate voltage, positive underlayer voltage or both to use together), to be equilibrated at the CHARGE DISTRIBUTION in the charge trap structure.This raceway groove method for deleting can provide a kind of mechanism of wiping of oneself's convergence.

And can be with it as a kind of charge balancing method, to compensate eraseable memory unit and difficult eraseable memory unit simultaneously.By using this charge balance technique, can strengthen the distribution of erase status target critical voltage Vt.Moreover, can be with the electronics of running away from grid, neutralization has been trapped in the hole in oxide or the nitride.Therefore, this charge balancing method can reduce the hot hole that causes memory cell to damage easily.By in conjunction with the charge balance technique of using the hot hole method for deleting, can get good endurance and reliability characteristic.

Charge balance/erasing move can be applicable to any time, or during the sector erasing action, carries out with random order, wipes performance with improvement.Another kind method is to open the contact bias voltage a little, and between the raceway groove erasing period, imports hot hole and inject, that is represent ditch track erasure and hot hole to wipe and can carry out simultaneously.Hot hole wiped with the ditch track erasure combine, can effectively improve programming and erase cycles window and reliability characteristic.

Charge balance/method for deleting described herein, the thickness that can be applicable to oxide under it is enough thick in the NROM type device that can prevent that electric charge from leaking.Charge balance/erasing characteristic shows with respect to only having a kind of consistent trend that raceway groove because of Vt produces the various channel lengths that open beginning Vt difference that influence causes.Wear tunnel because be used for the negative-grid FN raceway groove of charge balance action, be for a kind of space once wear tunnel mechanism, and can be on whole raceway groove symmetry fully, so it is not the widthwise size that depends on memory cell.Therefore, the purpose that by applying charge balance/method for deleting described herein,, can reach reduced volume, improve reliability and strengthen endurance for NROM type device.Application of the present invention can be applicable to other programs that are based upon a high critical condition in the memory cell in conjunction with a program or other as shown in figure 27.This program comprises heavily injects action, and this heavily injects action and comprises earlier the memory cell bias voltage, produce a high critical condition to induce, next apply a charge balance pulse again, allow electronics from the charge trap structure, run away in the more shallow trap, reducing critical value, and next use one second pulse again, with negative electricity loading iunjected charge structure of trap, to induce electronics iunjected charge structure of trap.In Figure 27, start program (step 2700) by a program command.The index n that retry removes program that is used to programme of deducibility this moment can be set to 0, and an index m who is used to calculate heavy injecting program number also can be set to 0.Program command in part embodiment of the present invention is the bit group action (byteoperation) corresponding to the flash memory device of related art techniques.Biasing procedure can respond program command and entry into service.In an embodiment of the present invention, the action of first in the biasing procedure is in the programming action, and application can induce electronics to inject a bias arrangement (step 2701) of memory cell.For example, in one first bias arrangement, can induce raceway groove to start second electronics and inject.And induced current injects one side of the charge storing unit structure of trap that is being programmed.Whether after using electric charge injection bias arrangement, state machine or other logics can be carried out a programmed check action, complete successfully with the programming action that determines each memory cell.Therefore, in next step, can determine memory cell whether by check action (step 2702).If by check, then index n can not increase progressively (step 2703) to memory cell, and can determine whether index has reached a predetermined maximum retry value N (step 2704).If index has reached maximum retry value, and not by check, then declaration proceeding failure (step 2705).If the decision index does not surpass maximum retry value in step 2704, then return step 2702, inject bias arrangement in this retry hole.If in step 2702, memory cell can determine then by check whether exponent m has reached its maximum M (step 2706), and judges the heavily injection circulation whether predetermined number is crossed in executed.If exponent m also is not equal to M, then can apply a charge balance pulse that is applicable to heavy method for implanting, to cause as jumping out electric current with reference to the described electronics of in shallow trap, more easily jumping out of above-mentioned Figure 1B.The action of charge balance bias voltage comprises that a length less than about 10 milliseconds, for example is approximately 1 millisecond negative-gate voltage pulse.This pulse can make the electronics that is limited in the shallow energy trapping jump back out in the raceway groove.Because heavily injecting cycle period, memory cell has quite highdensity negative electrical charge, so can induce the electronics of considerably less (if any) to inject.After the action of charge balance bias voltage, exponent m can be increased progressively (step 2708), and return step 2701, can import the bias arrangement that electronics injects to use once more.If the heavily injection action of predetermined number is crossed in the memory cell executed, then declare this EP (end of program) (step 2709).

The embodiment of the invention comprises a charge balance pulse, and this charge balance pulse is described with reference to Figure 27, before carrying out any programming and erase cycles, be applied on the device, or as described in reference Figure 27, institute applies before carrying out a programming action.In addition, the embodiment of the invention is included in during the programming action more, carry out as above-mentioned Fig. 4,5,11 and 24-26 shown in method, and this method is to comprise as with reference to a heavy injecting program shown in Figure 27.

Figure 28 and Figure 29 are the heavily injection actions that illustrates as shown in figure 27, and wherein the program bias configuration can induce raceway groove to start second electronics (CHISEL) injection current.At first, by having on the NROM type memory cell of a p type polysilicon bar utmost point, carry out a charge balance pulse and (on grid, apply-21 volts voltage, and on drain electrode, source electrode and substrate, when the voltage that applies 0 volt is 1 second), and produce a critical voltage that is approximately 3.8 volts.Next, apply most again and heavily inject circulation and the generation data.Wherein, each heavily injects circulation and comprises bias arrangement that can cause raceway groove to start second electronics (CHISEL) injection current of application, with the critical value setting with memory cell is about 5.3 volts, and apply a short charge balance pulse again and (on grid, apply-21 volts voltage, and on drain electrode, source electrode and substrate, 1 microsecond when the voltage that applies 0 volt is).

Figure 28 is the continuous cycle period that illustrates heavily injecting action, the critical voltage of five charge balance pulses and time relation figure.Critical voltage after the charge balance pulse in primary 1 microsecond on the trajectory 2800 can be approximately 4.9 volts from being approximately 5.3 volts, dropping to.Second on trajectory 2801 is heavily injected circulation, and the critical voltage after the charge balance pulse of secondary 1 microsecond can be approximately 5.1 volts from being approximately 5.3 volts, dropping to.On trajectory 2802 the 3rd heavily injects circulation, and the critical voltage after the charge balance pulse of for the third time 1 microsecond can be approximately 5.2 volts from being approximately 5.3 volts, dropping to.The 4th on trajectory 2803 is heavily injected circulation, and the critical voltage after the charge balance pulse of the 4th time 1 microsecond can be approximately 5.22 volts from being approximately 5.3 volts, dropping to.The 5th on trajectory 2804 is heavily injected circulation, and the critical voltage after the charge balance pulse of the 5th time 1 microsecond can be approximately 5.23 volts from being approximately 5.3 volts, dropping to.

Figure 29 has the data identical with Figure 28, and illustrates each continuous critical voltage decline situation of heavily injecting circulation.Primary heavy injection cycle period, critical voltage can be approximately 4.9 volts from being approximately 5.3 volts, dropping to.In secondary heavy injection cycle period, critical voltage can drop to and is approximately 5.1 volts.Before the 5th time heavily injection circulation,,, can be reduced in the charge loss of short charge balance impulse duration by this so can begin saturatedly in the threshold voltage variations of heavily injecting the charge balance impulse duration of circulation because fall into the blue skew of the frequency spectrum of electron energy state.

Figure 30 and Figure 31 illustrate to be used for the data of heavily injecting action shown in Figure 27 is described, wherein program bias configuration meeting induces raceway groove FN to wear the tunnel electric current with a negative-gate voltage injection current.At first, by having on the NROM type memory cell of a p type polysilicon bar utmost point, carry out a charge balance pulse and (on grid, apply-21 volts voltage, and on drain electrode, source electrode and substrate, when the voltage that applies 0 volt is 1 second), and produce a critical voltage that is approximately 3.8 volts.Next, apply most again and heavily inject circulation and the generation data.Wherein, each heavily injects circulation and comprises bias arrangement that can cause raceway groove FN to wear the tunnel electric current of application, 00 is about 5.3 volts with the critical value setting with memory cell, and apply a short charge balance pulse again and (on grid, apply-21 volts voltage, and on drain electrode, source electrode and substrate, 4 microseconds when the voltage that applies 0 volt is).

Figure 30 is the continuous cycle period that illustrates heavily injecting action, the critical voltage of five charge balance pulses and time relation figure.Critical voltage after the charge balance pulse in primary 4 microseconds on the trajectory 2800 can be approximately 5.05 volts from being approximately 5.3 volts, dropping to.Second on trajectory 2801 is heavily injected circulation, and the critical voltage after the charge balance pulse of secondary 4 microseconds can be approximately 5.16 volts from being approximately 5.3 volts, dropping to.On trajectory 2802 the 3rd heavily injects circulation, and the critical voltage after the charge balance pulse of for the third time 4 microseconds can be approximately 5.22 volts from being approximately 5.3 volts, dropping to.The 4th on trajectory 2803 is heavily injected circulation, and the critical voltage after the charge balance pulse of the 4th time 4 microseconds can be approximately 5.22 volts from being approximately 5.3 volts, dropping to.The 5th on trajectory 2804 is heavily injected circulation, and the critical voltage after the charge balance pulse of the 5th time 4 microseconds can be approximately 5.25 volts from being approximately 5.3 volts, dropping to.

Figure 31 has the data identical with Figure 30, and illustrates each continuous critical voltage decline situation of heavily injecting circulation.Primary heavy injection cycle period, critical voltage can be approximately 5.05 volts from being approximately 5.3 volts, dropping to.In secondary heavy injection cycle period, critical voltage can drop to and is approximately 5.16 volts.Before the 5th time heavily injection circulation,,, can be reduced in the charge loss of short charge balance impulse duration by this so can begin saturatedly in the threshold voltage variations of heavily injecting the charge balance impulse duration of circulation because fall into the blue skew of the frequency spectrum of electron energy state.

Figure 32 illustrates one to be used for illustrating through the key diagram of overweight injection processing with the data retention performance of the memory cell of handling without overweight injection.Data among the figure is representative causes the device of hot hole damage after through 10000 times programming and erase cycles a performance.As shown on the trajectory 3200 without heavily injecting the device of handling, corresponding to be approximately 1 millisecond retention time the stoving times (baking time) that are approximately 150 degree Celsius afterwards, the loss of critical value can be above 0.5 volt.As the device of handling through overweight injection shown on the trajectory 3201, after identical stoving time, the loss meeting of critical value is less than 0.3 volt.

Figure 33 is the simplification energy bitmap that illustrates a charge trap memory cell, with explanation application idea in the present invention.In this energy bitmap, first district 3300 is corresponding to the raceway groove in substrate.Second district 3301 is corresponding to the end dielectric medium that generally comprises silicon dioxide.The 3rd district 3302 is corresponding to the charge trap floor that generally comprises silicon nitride.The 4th district 3303 is corresponding to the last dielectric medium that generally comprises silicon dioxide.The 5th district 3304 is corresponding to a grid, and this grid generally comprises the material of p type polysilicon or the higher work functions of other tools in embodiments of the present invention.As mentioned above, grid is made by the material of the higher work functions of tool, so that the injection barrier 3306 of electronics 3305 can be higher than the injection barrier that has by the n type polysilicon bar utmost point of the made last dielectric medium of silicon dioxide.The described work functions 3307 of Figure 33 is corresponding to the conduction band (conductionband) of an electronics from grid material, moves to an energy that the free electron current potential is required.Figure 33 illustrates the electronics 3308 in the shallow trap of charge trap structure more respectively, and than the electronics in the deep trap 3309.Allow jump out than the electronics in the deep trap 3309 before, the above-mentioned short charge balance pulse with reference to shown in Figure 27 can make the electronics 3308 in shallow trap jump out earlier.Can resist the electric charge leakage than the electronics in the deep trap 3309, and have preferable charge-retention property.For using the embodiment that heavily injects action, can be than the thickness of its end oxide of preference greater than 3 nanometers, to avoid directly wearing tunnel.In addition, also can use and comprise Al ₂O ₃And HfO ₂Other high dielectric constant materials, dielectric medium and end dielectric medium in the shaping.In like manner, also can use other materials shaping charge trap structure.

The negative electrical charge balance play has a kind of oneself's convergence critical voltage characteristic, can keep stable critical voltage and distribute on an array through a large amount of programmings and erase cycles by this.Moreover, because of its hot hole that can be reduced in the end dielectric medium damages, so can get splendid reliability characteristic.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.

Claims (39)

1, a kind of memory cell operation method, this memory cell comprises a grid, in the one source pole district within the substrate zone and a drain region and the raceway groove between this source area and this drain region in this substrate, and comprise dielectric medium on, a charge trap structure and the dielectric medium once between this grid and this raceway groove, it is characterized in that this memory cell operation method comprises:

Use a program, to set up a state in this memory cell, it is to comprise: provide one first bias arrangement, in order to this memory cell of programming; Provide one second bias arrangement, in order to wipe this memory cell; And, provide one three bias arrangement relevant with this first bias arrangement and this second bias arrangement in this memory cell,

Wherein the 3rd bias arrangement provides a bias pulse and causes one first electric charge to move and one second electric charge moves, when this grid has a negative voltage with respect to substrate, then this first electric charge moves between this grid and this charge trap structure, and this second electric charge moves between this charge trap structure and this substrate, when this grid has a positive voltage with respect to substrate, then this first electric charge moves between this substrate and this charge trap structure, and this second electric charge moves between this charge trap structure and this grid, this first electric charge moves, this second electric charge moves and can cause a critical voltage to restrain towards a target critical value, when this critical voltage during near this target critical value, the 3rd bias arrangement is equilibrated at the CHARGE DISTRIBUTION in this charge trap structure within the whole memory unit channel length scope.

2, memory cell operation method according to claim 1 is characterized in that wherein said first bias arrangement is to induce the channel hot electron injection current.

3, memory cell operation method according to claim 1 is characterized in that wherein said first bias arrangement is to induce raceway groove to start second electron injection current.

4, memory cell operation method according to claim 1 is characterized in that wherein said first bias arrangement is to induce the auxiliary tunnel electron injection current of wearing of electric field.

5, memory cell operation method according to claim 1 is characterized in that wherein said second bias arrangement is the electrons tunnel of inducing between this charge trap structure and this raceway groove.

6, memory cell operation method according to claim 1 is characterized in that wherein said program comprises at least three those circulations.

7, memory cell operation method according to claim 1, it is characterized in that wherein said dielectric medium, this charge trap structure and the end dielectric medium gone up, have one in conjunction with effective oxide thickness, and this second bias arrangement comprises this grid of this memory cell this substrate in this district of this raceway groove, apply a negative voltage, and the size of this negative voltage to this combination effectively the ratio of each nanometer of oxide thickness more than or equal to 0.7 volt/nanometer.

8, memory cell operation method according to claim 1, it is characterized in that the wherein said dielectric medium of going up, this charge trap structure, an and end dielectric medium, have one in conjunction with effective oxide thickness, and this second bias arrangement comprises to be worked as this substrate in this district of this raceway groove, apply an approximate earthing potential, and to this source electrode and this drain electrode, when applying an approximate earthing potential, on this grid of this memory cell, apply a negative voltage, and the size of this negative voltage to this combination effectively the ratio of each nanometer of oxide thickness more than or equal to 0.7 volt/nanometer.

9, memory cell operation method according to claim 1, it is characterized in that wherein said dielectric medium, this charge trap structure and the end dielectric medium gone up, have one in conjunction with effective oxide thickness, and this second bias arrangement comprises this grid of this memory cell this substrate in this district of this raceway groove, apply a negative voltage, and the size of this negative voltage to this combination effectively the ratio of each nanometer of oxide thickness be 1.0 ± 10% volts/nanometer.

10, memory cell operation method according to claim 1 is characterized in that wherein said grid comprises having the material that the work functions that produces electrons tunnel injection barrier is higher than n type polysilicon.

11, memory cell operation method according to claim 1 is characterized in that wherein said grid comprises having the material that the work functions that produces electrons tunnel injection barrier is higher than 4.25eV.

12, memory cell operation method according to claim 1 is characterized in that wherein said grid comprises having the material that the work functions that produces electrons tunnel injection barrier is higher than 5eV.

13, memory cell operation method according to claim 1 is characterized in that wherein said grid comprises the polysilicon of doped p type impurity.

14, memory cell operation method according to claim 1 is characterized in that wherein said dielectric medium, this charge trap structure and the end dielectric medium gone up, and have one in conjunction with effective oxide thickness, and this memory cell operation method comprises more:

Before any circulation of this program of execution, to this grid of this memory cell this substrate in this district of this raceway groove, apply a negative voltage, and the size of this negative voltage to this combination effectively the ratio of each nanometer of oxide thickness more than or equal to 0.7 volt/nanometer.

15, memory cell operation method according to claim 1, it is characterized in that wherein said second bias arrangement comprises that applying one can induce electronics to jump back out to the pulse of this raceway groove from this charge trap structure, and a time interval that applies this pulse is less than 10 milliseconds.

16, memory cell operation method according to claim 1, it is characterized in that wherein said second bias arrangement comprises that applying one can induce electronics to jump back out to the pulse of this raceway groove from this charge trap structure, and a time interval that applies this pulse is less than or equal to 1 millisecond.

17, memory cell operation method according to claim 1, it is characterized in that wherein said program comprises applies first pulse that can induce electronics to inject, and carry out a high critical condition check action, if by this high critical condition check action, then apply one second pulse again, to induce the electric charge between this charge trap structure and this raceway groove to wear tunnel, wherein this high critical condition check action is meant that this is brought out electronics injects the high critical voltage that produces after this charge trap structure action of testing.

18, memory cell operation method according to claim 1, it is characterized in that wherein said program comprises applies first pulse that can induce electronics to inject, and carry out a high critical condition check action, if by this high critical condition check action, then apply one second pulse again, wear tunnel to induce the electric charge between this charge trap structure and this raceway groove, next apply the pulse that another can induce electronics to inject again, and carry out a high critical condition check action, if by this high critical condition check action, then apply another pulse again, to induce the electric charge between this charge trap structure and this raceway groove to wear tunnel, wherein this high critical condition check action is meant that this is brought out electronics injects the high critical voltage that produces after this charge trap structure action of testing.

19, a kind of integrated circuit (IC) apparatus is characterized in that it comprises:

One substrate;

Most memory cell on this substrate, wherein each those memory cell all has a critical voltage, and all comprise a charge trap structure, a grid and an one source pole district of in this substrate, separating and a drain region, and comprise dielectric medium on, a charge trap structure and the end dielectric medium between this grid and this raceway groove by a raceway groove; And

One control circuit is to be connected to those memory cell, and comprises a logic, and this logic comprises:

Use a program, to set up a state in this memory cell, it is to comprise: provide one first bias arrangement, in order to this memory cell of programming; Provide one second bias arrangement, in order to wipe this memory cell; And, provide one three bias arrangement relevant with this first bias arrangement and this second bias arrangement in this memory cell,

Wherein the 3rd bias arrangement provides a bias pulse and causes one first electric charge to move and one second electric charge moves, when this grid has a negative voltage with respect to substrate, then this first electric charge moves between this grid and this charge trap structure, and this second electric charge moves between this charge trap structure and this substrate, when this grid has a positive voltage with respect to substrate, then this first electric charge moves between this substrate and this charge trap structure, and this second electric charge moves between this charge trap structure and this grid, this first electric charge moves, this second electric charge moves and can cause a critical voltage to restrain towards a target critical value, when this critical voltage during near this target critical value, the 3rd bias arrangement is equilibrated at the CHARGE DISTRIBUTION in this charge trap structure within the whole memory unit channel length scope.

20, integrated circuit (IC) apparatus according to claim 19 is characterized in that wherein said first bias arrangement is to induce the channel hot electron injection current.

21, integrated circuit (IC) apparatus according to claim 19 is characterized in that wherein said first bias arrangement is to induce raceway groove to start second electron injection current.

22, integrated circuit (IC) apparatus according to claim 19 is characterized in that wherein said first bias arrangement is to induce the auxiliary tunnel electron injection current of wearing of electric field.

23, integrated circuit (IC) apparatus according to claim 19 is characterized in that wherein said second bias arrangement is the electrons tunnel of inducing between this charge trap structure and this raceway groove.

24, integrated circuit (IC) apparatus according to claim 19 is characterized in that wherein said program comprises at least three those circulations.

25, integrated circuit (IC) apparatus according to claim 19, it is characterized in that the wherein said dielectric medium, this charge trap structure and should end dielectric medium gone up, have one in conjunction with effective oxide thickness, and this second bias arrangement comprises this grid of this memory cell this substrate in this district of this raceway groove, apply a negative voltage, and the size of this negative voltage to this combination effectively the ratio of each nanometer of oxide thickness more than or equal to 0.7 volt/nanometer.

26, integrated circuit (IC) apparatus according to claim 19, it is characterized in that the wherein said dielectric medium of going up, this charge trap structure, and should end dielectric medium, have one in conjunction with effective oxide thickness, and this second bias arrangement comprises to be worked as this substrate in this district of this raceway groove, apply an approximate earthing potential, and to this source electrode and this drain electrode, when applying an approximate earthing potential, on this grid of this memory cell, apply a negative voltage, and the size of this negative voltage to this combination effectively the ratio of each nanometer of oxide thickness more than or equal to 0.7 volt/nanometer.

27, integrated circuit (IC) apparatus according to claim 19, it is characterized in that the wherein said dielectric medium, this charge trap structure and should end dielectric medium gone up, have one in conjunction with effective oxide thickness, and this second bias arrangement comprises this grid of this memory cell this substrate in this district of this raceway groove, apply a negative voltage, and the size of this negative voltage to this combination effectively the ratio of each nanometer of oxide thickness be 1.0 ± 10% volts/nanometer.

28, integrated circuit (IC) apparatus according to claim 19 is characterized in that wherein said grid comprises having the material that the work functions that produces electrons tunnel injection barrier is higher than n type polysilicon.

29, integrated circuit (IC) apparatus according to claim 19 is characterized in that wherein said grid comprises having the material that the work functions that produces electrons tunnel injection barrier is higher than 4.25eV.

30, integrated circuit (IC) apparatus according to claim 19 is characterized in that wherein said grid comprises having the material that the work functions that produces electrons tunnel injection barrier is higher than 5eV.

31, integrated circuit (IC) apparatus according to claim 19 is characterized in that wherein said grid comprises the polysilicon of doped p type impurity.

32, integrated circuit (IC) apparatus according to claim 19 is characterized in that the wherein said dielectric medium, this charge trap structure and should end dielectric medium gone up, and have one in conjunction with effective oxide thickness, and this memory cell operation method comprises more:

Before any circulation of this program of execution, to this grid of this memory cell this substrate in this district of this raceway groove, apply a negative voltage, and the size of this negative voltage to this combination effectively the ratio of each nanometer of oxide thickness more than or equal to 0.7 volt/nanometer.

33, integrated circuit (IC) apparatus according to claim 19, it is characterized in that wherein said second bias arrangement comprises that applying one can induce electronics to jump back out to the pulse of this raceway groove from this charge trap structure, and a time interval that applies this pulse is less than 10 milliseconds.

34, integrated circuit (IC) apparatus according to claim 19, it is characterized in that wherein said second bias arrangement comprises that applying one can induce electronics to jump back out to the pulse of this raceway groove from this charge trap structure, and a time interval that applies this pulse is less than or equal to 1 millisecond.

35, integrated circuit (IC) apparatus according to claim 19, it is characterized in that wherein said program comprises applies first pulse that can induce electronics to inject, and carry out a high critical condition check action, if by this high critical condition check action, then apply one second pulse again, to induce the electric charge between this charge trap structure and this raceway groove to wear tunnel, wherein this high critical condition check action is meant that this is brought out electronics injects the high critical voltage that produces after this charge trap structure action of testing.

36, integrated circuit (IC) apparatus according to claim 19, it is characterized in that wherein said program comprises applies first pulse that can induce electronics to inject, and carry out a high critical condition check action, if by this high critical condition check action, then apply one second pulse again, wear tunnel to induce the electric charge between this charge trap structure and this raceway groove, next apply the pulse that another can induce electronics to inject again, and carry out a high critical condition check action, if by this high critical condition check action, then apply another pulse again, to induce the electric charge between this charge trap structure and this raceway groove to wear tunnel, wherein this high critical condition check action is meant that this is brought out electronics injects the high critical voltage that produces after this charge trap structure action of testing.

37, a kind of memory cell operation method, this memory cell comprises a grid, in the one source pole district within the substrate zone and a drain region and the raceway groove between this source area and this drain region in this substrate, and comprise dielectric medium on, a charge trap structure and the dielectric medium once between this grid and this raceway groove, it is characterized in that this memory cell operation method comprises:

Use a program, to set up a high critical condition in this memory cell, it is to comprise: provide one first bias arrangement, in order to this memory cell of programming; Provide one second bias arrangement, in order to wipe this memory cell; And

After this a program generation or a contingent time interval, in this memory cell, one three bias arrangement relevant with this first bias arrangement and this second bias arrangement is provided, wherein the 3rd bias arrangement provides a bias pulse and causes one first electric charge to move and one second electric charge moves, when this grid has a negative voltage with respect to substrate, then this first electric charge moves between this grid and this charge trap structure, and this second electric charge moves between this charge trap structure and this substrate, when this grid has a positive voltage with respect to substrate, then this first electric charge moves between this substrate and this charge trap structure, and this second electric charge moves between this charge trap structure and this grid, this first electric charge moves, this second electric charge moves and can cause a critical voltage to restrain towards a target critical value, when this critical voltage during near this target critical value, the 3rd bias arrangement is equilibrated at the CHARGE DISTRIBUTION in this charge trap structure within the whole memory unit channel length scope.

38, according to the described memory cell operation method of claim 37, it is characterized in that wherein said second bias arrangement comprises that applying one can induce between this charge trap structure and this raceway groove electric charge to wear the pulse of tunnel, and a time interval of carrying out this pulse is less than 10 milliseconds; And this charge balance bias arrangement comprises that applying one can induce between this grid and this charge trap structure, and the balancing charge between this charge trap structure and this raceway groove wears the pulse of tunnel, and a time interval of carrying out this pulse is greater than 500 milliseconds.

39, according to the described memory cell operation method of claim 37, it is characterized in that wherein said second bias arrangement comprises that applying one can induce between this charge trap structure and this raceway groove electric charge to wear the pulse of tunnel, and a time interval of carrying out this pulse is less than 5 milliseconds; And this charge balance bias arrangement comprises that applying one can induce between this grid and this charge trap structure, and the balancing charge between this charge trap structure and this raceway groove wears the pulse of tunnel, and a time interval of carrying out this pulse is greater than 500 milliseconds.

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