CN1400603A - High-speed induction amplifier with automatic shutoff precharging path - Google Patents
High-speed induction amplifier with automatic shutoff precharging path Download PDFInfo
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- CN1400603A CN1400603A CN 01125079 CN01125079A CN1400603A CN 1400603 A CN1400603 A CN 1400603A CN 01125079 CN01125079 CN 01125079 CN 01125079 A CN01125079 A CN 01125079A CN 1400603 A CN1400603 A CN 1400603A
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Abstract
An inductive amplifier can reverse the output signal which is from transmittal transistor to control a charged transistor. The device and the transistor charges the output signal to the voltage, the voltage is a little low to the reversal voltage of data latch circuit. If the accessing data cell is a low critical voltage data cell, it will be opened or digital signal is "1", now, the voltage of output signal isn't change obviously, and the data can be locked quickly and accessed. If the accessing data cell is a high critical voltage data cell, it can't open or digital signal is "0", the transmittal transistor shuts up and the output signal voltage will rise up over the reversal voltage of data latch circuit through a load. The charged votlage approaches the reversal voltage, thus the output signal voltage needn't to rise too high, so the access of digital "0" is very quick.
Description
Technical field
The present invention can read the integrated circuit storage array of (Sensing) electric current about a kind of integrated circuit storage array (Memory Array) during particularly about a kind of logic voltage in the memory cell that reads storage array (Logic Level).
Background technology
Induction amplifier often is used to read the data storing state of the memory cell of storage array, and storage array comprises read-only storage (ROM) array, the read-only storage of erasable programmable (PROM) array and electric read-only storage able to programme (EPROM) array.The common store charge of memory cell is to distinguish its logic state.Logic state is generally binary bit " 0 " or " 1 " or the multilevel logic state.One typical read-only storage array may comprise millions of memory cell, and these memory cell are embarked on journey into row usually and arranged.Some storage array is as memory cell with the gate field effect transistor of floating (Floating Gate Field Effect Transistor), the source electrode of each memory cell of same delegation (Column) all is connected to one source pole line (Source-ColumnLine), when a memory cell is selected and sensed amplifier when reading, the source electrode line of this memory cell promptly is applied in a reference voltage or a ground voltage.
Drain electrode with each memory cell of delegation then is connected to a bit line or drain electrode line (Drain-ColumnLine), and is selected and sensed amplifier when reading when a memory cell, and the line that drains just transmits an input signal to induction amplifier.The control grid of the memory cell of same row then is connected to the character line, and when a memory cell was selected and is read, the character line then was applied in a selection voltage (SelectVoltage) that is predetermined.When a memory cell was read, the electric current of this memory cell of flowing through just compared with a reference current, to determine the stored data of this memory cell was " 0 " or " 1 ".
In some traditional element, reference circuit is to be connected to an induction by current amplifier input terminal and its output terminal is an input end that is connected to a differential amplifier or differentiating amplifier (Differential Amplifier).The voltage output and one of differentiating amplifier comparison induction by current amplifier is connected to the voltage output of another induction by current amplifier of a memory cell that is read.Reference current can show the data storing state of the memory cell that is read.
However, reading of the data storing state of memory cell can be made a mistake.A problem utilizing induction amplifier to meet with is that the electric capacity of drain electrode line can influence the primary current from induction amplifier.If the no enough time allows the drain electrode line recover stable, electric current is uprushed and can be caused the mistake that memory cell data storing state reads.Provide the enough time to allow the drain electrode line recover stable and can drag slow storage array running speed, this is receivedly to sacrifice, especially for the storage array that must together operate with high speed microprocessor.
Pre-charge drain electrode line is one can be avoided because of the electric current of uprushing needs the answer method of stabilization time, produces but pre-charge drain electrode line also has disadvantageous effect.When using pre-charging circuit to reduce time for reading, traditional pre-charging circuit can exhaust a large amount of electric currents from the voltage source of supply.Pre-charge also can cause the problem of time for reading.Pre-charge must reach for a long time with the line of guaranteeing to drain fully charged avoiding data read errors, but should not drag slow storage array running speed too for a long time.
Be used for the differentiating amplifier of two-part sensor circuit by omission, the electric current of employed part chip area of pre-charging circuit and consumption can partly offset.In the one-level induction amplifier, the output of induction amplifier is set at a preset value, for example " 0 " data storing state.Output only just need be set when differing from default output valve when it, therefore reads and tolerates that the limit can increase.When the preset data storing state is " 0 ", reading speed can be stored the restriction of born of the same parents' electric current.If the memory cell electric current is big, data storing state " 1 " access speed fast, but if the memory cell electric current is little, data storing state " 1 " access speed slower.Different memory cell can cause different memory cell electric currents when reading, and therefore is necessary to provide a time for reading can satisfy the slowest memory cell electric current.
The pre-charge round-robin can be oversimplified opportunity, and pre-charge stops automatically when reaching preset value.One pre-charging circuit uses the field effect transistor of pair of series between forward bias supply and data line, and is connected the field effect transistor between the output of read-out amplifier.Field effect transistor is to reverse with gate (Gated) by input value, in other words, when input value is low, the gate voltage height, and field effect transistor is opened and be supplied to the output terminal supply of current from voltage.However, when the field effect transistor of pair of series is opened, the transistorized limit voltage value of first (pre-charge) make its have one for second (transmission) transistor the lower passage of electric conductivity.When input value was low, field effect transistor was opened and the output valve reduction.When input value was high, a gate connects output terminal and be positioned at the forward voltage source of supply to be used to provide from the forward voltage source of supply with the depletion type of induction amplifier output terminal or shortage transistor npn npn (Depletion-Mode Transistor) drew high paramount output valve to the electric current of induction amplifier output terminal and with output.
However, the field effect transistor of serial connection can drag and operate speed slowly.The output of the load-sensing of depletion mode transistor meeting simultaneously amplifier.In this kind circuit, the induction amplifier output end voltage is approximately higher than data voltage 200mV.This is not the appropriate voltage value for next stage, and for example a phase inverter and just like unsuitable bias off can cause the CMOS transistor of leakage current.
About the problem of using the end depletion mode transistor between forward voltage source of supply and induction amplifier output is solved, this is the P channel fet that is connected to diode by use, and the gate of this P channel fet is connected to the output of induction amplifier.Output voltage fluctuation can reduce, but output voltage still may be unsuitable for next stage, and electric current may flow through next stage.Therefore the utmost point is necessary to develop a kind of induction amplifier with pre-charge path, and this pre-charge path can cut off automatically when reaching the appropriate voltage value, and produces the magnitude of voltage of a suitable induction amplifier next stage.Need a kind of induction amplifier that possesses low-power, little layout area and high reading speed simultaneously.
Summary of the invention
The purpose of this invention is to provide a kind of high-speed induction amplifier that can cut off pre-charging circuit automatically that has, it can cut off the pre-charge path to control a pre-charge path automatically by the counter-rotating output signal before reading place value.
For achieving the above object, a kind of induction amplifier of the input utmost point that is connected to the bit line of storage array that has is provided according to an aspect of the present invention, be characterized in, at least comprise: a transistor, described transistor have second conducting end that first conducting end and that is connected to the described input utmost point is connected to an output stage; One phase inverter, described phase inverter have a phase inverter that is connected to described output stage and phase inverter output and import; And a precharge transistor, it comprises: a pre-charge control end, described pre-charge control end are connected to described phase inverter output; One first pre-charge conducting end, the described first pre-charge conducting end is connected to a voltage source of supply, and described voltage source of supply provides a bias voltage, and one second pre-charge conducting end, and the described second pre-charge conducting end is connected to described output stage.
For achieving the above object, a kind of induction amplifier of the input utmost point that is connected to the bit line of storage array that has is provided according to a further aspect of the invention, be characterized in, described induction amplifier comprises at least: a transmission transistor, described transmission transistor comprises at least: one first transmission conducting end, and the described first transmission conducting end is connected to the described input utmost point; One second transmission conducting end, the described second transmission conducting end is connected to described output stage; Reach a transmission control end; One first phase inverter, described first phase inverter have first phase inverter output that first phase inverter input and that is connected to the described input utmost point is connected to described transmission control end; One second phase inverter, described second phase inverter have second phase inverter that is connected to described output stage to be imported, and described second phase inverter can provide a pre-charge bias to export in one second phase inverter; One precharge transistor, described precharge transistor comprises a control end at least, described control end is connected to described second phase inverter output; One first conducting end, described first conducting end is connected to a voltage supply, and described voltage supply provides a bias voltage, and one second conducting end, and described second conducting end is connected to described output stage; One load transistor, described load transistor comprises at least: one first load conducting end, the described first load conducting end is connected to described voltage supply, and one second load conducting end, and the described second load conducting end is connected to described output stage.
For achieving the above object, provide a kind of induction amplifier of the input utmost point that is connected to the bit line of storage array that has according to another aspect of the invention, be characterized in, described induction amplifier comprises at least: a transmission transistor, described transmission transistor comprise at least one be connected to the described input utmost point first the transmission conducting end, with one be connected to described output stage second the transmission conducting end; One phase inverter, described phase inverter have a phase inverter that is connected to described output stage and phase inverter output and import; One precharge transistor, which comprises at least: a control end, described control end is connected to described phase inverter output, one first conducting end, described first conducting end is connected to a voltage source of supply, described voltage source of supply provides a bias voltage, and one second conducting end, and described second conducting end is connected to described output stage; One load transistor, described load transistor comprises at least: one first load conducting end, the described first load conducting end is connected to described voltage supply; One second load conducting end, the described second load conducting end is connected to described output stage; And a gate terminal, described gate terminal is connected to an earthing potential; And an exclusive circuit, described exclusive circuit comprises at least: a locking phase inverter, and described locking phase inverter has a complementary pair transistor, and described complementary pair transistor has a common gate, and described common gate is connected to described phase inverter output; And a diode connects, connect described complementary pair transistor and between described voltage supply and described earthing potential of described diode.
For achieving the above object, provide a kind of method of operating induction amplifier according to a further aspect of the present invention, be characterized in that described method comprises at least: one first output voltage of an output stage of the described induction amplifier that reverses is to produce a counter-rotating output; The described counter-rotating that is coupled exports a control end of a precharge transistor to; The described output stage to of pre-charge is lower than second output voltage of a limit voltage of a data locking level, and described data locking level has a locking that is connected to described output stage and imports; Close a transistor, described transistor has second conducting end that first conducting end and that is connected to described output stage is connected to a data line; And the described output stage to of load is higher than the 3rd output voltage of the described limit voltage of described data locking level.
For achieving the above object, a kind of induction amplifier is provided according to a further aspect of the invention, be characterized in, described induction amplifier comprises at least: a transmission transistor, and described transmission transistor comprises at least: one first transmission conducting end, the described first transmission conducting end is connected to a bit line, one second transmission conducting end, the described second transmission conducting end is connected to a DOL Data Output Line, and a transmission control end, and described transmission control end is connected to one and shifts the bias voltage network;
One pre-charging circuit, described pre-charging circuit is connection and is positioned between voltage supply input and described DOL Data Output Line, described pre-charging circuit comprises a negative-feedback circuit at least, and described negative-feedback circuit is set up a precharge voltage in described DOL Data Output Line; And
One load transistor, described load transistor comprises at least: one first load conducting end, the described first load conducting end are connected to described voltage supply input; One second load conducting end, the described second load conducting end is connected to described DOL Data Output Line; And a load control sluice is extreme, and described gate terminal is connected to a ground-electrode.
Because the preset value state is a low limit voltage state, therefore when reading low limit voltage born of the same parents, before the voltage reduction, avoid bitline precharge to high voltage.In an embodiment, the P channel mos field effect transistor of a gate ground connection provides a load paths to avoid through the direct current electric leakage of CMOS transistor under standby.Gate ground connection also provides a stable voltage V
GSAnd unlike connecting diode load transistor (Diode-Connected Pull-Up Transistor).Induction amplifier has an output stage (Input Node), and this output stage can be connected in the bit line that the transmission transistor of importing between the utmost point (data line) and the output stage (0utput Node) is connected to a storage array by one.The signal of phase inverter counter-rotating output stage also provides the gate of the signal of this counter-rotating to precharge transistor.This pre-charge action is from feed end V
DDTo the output stage supply of current.To magnitude of voltage, this magnitude of voltage just is lower than the reversal voltage that reads phase inverter to phase inverter in conjunction with precharge transistor pre-charge output terminal.If data cell is to be in the data storing state " 1 ", transmission transistor is opened and output terminal is maintained at precharge voltage.If data cell is to be in the data storing state " 0 ", transmission transistor is closed and the output terminal load be higher than read phase inverter (Sense Inverter) reversal voltage (Flip Level) by being connected to output stage to V
DDTransmission transistor.This transmission time is short in the reversal voltage of precharge voltage near next stage.
The invention provides a kind of non-clock pulse timing pre-charge (Un-Clocked Pre-Charge) circuit read-out amplifier that has, this non-timing pre-charging circuit can reduce and reads the required power of action, and simplifies circuit.Pre-charging circuit utilizes an intelligent feedback path, but this feedback path biasing reads output voltage and cuts off automatically.Default data value be " 1 ", this data value provides a wide read range and allows and because of default data value is " 0 " time low memory cell current problems, can be biased to the limit voltage value of next stage in addition, but so pulling speed.
Be clearer understanding purpose of the present invention, characteristics and advantage, below in conjunction with accompanying drawing to of the present invention preferable
Embodiment is elaborated.
Description of drawings
Figure 1A is the simplified electrical circuit diagram of a part of induction amplifier circuit of a demonstration transmission transistor bias voltage;
Figure 1B is for being connected to the simplified electrical circuit diagram of a part of storage array of transmission transistor by a switch;
Fig. 1 C is that a part of induction amplifier of a high limit voltage memory cell and the simplified electrical circuit diagram of storage array are read in a demonstration;
Fig. 1 D is that a part of induction amplifier of a low limit voltage memory cell and the simplified electrical circuit diagram of storage array are read in a demonstration;
Fig. 2 A is the simplified electrical circuit diagram that tradition is used the induction amplifier of timing pre-charge (Clocked Pre-charge) technology;
Fig. 2 B is the simplification generalized schematic of traditional induction amplifier;
Fig. 2 C is the simplification generalized schematic of traditional induction amplifier;
Fig. 3 A is the rough schematic view of induction amplifier of the present invention;
Fig. 3 B answers the rough schematic view of phase inverter with the induction amplifier of control pre-charge for usability of the present invention;
Fig. 3 C shifts the rough schematic view of phase inverter with the induction amplifier of control pre-charge for the present invention uses;
Fig. 4 A is the locking simplified electrical circuit diagram partly of induction amplifier circuit of the present invention;
Fig. 4 B is another the locking simplified electrical circuit diagram partly of induction amplifier circuit of the present invention;
Fig. 5 is the simplified electrical circuit diagram as the precharge transistor of current mirror;
Fig. 6 is the simplified flow chart with the induction amplifier reading of data; And
Fig. 7 is for comparing regularly the signal voltage of the induction amplifier of pre-charging circuit and the simplification clock pulse figure of the signal voltage of induction amplifier of the present invention when reading high limit voltage memory cell and low limit voltage memory cell.
Embodiment
In order to understand the difference of the present invention and prior art, read-out amplifier will be with the circuit diagram explanation of simplifying with the part running of relevant memory cell.The part running of traditional read-out amplifier then will be described.
Figure 1A is the simplified electrical circuit diagram of the transfer bias circuit (Transfer Bias Circuit) 10 of an induction amplifier 12.Only show among the figure and partly shift bias circuit and induction amplifier.Other shift bias circuit especially has also can be used as of other elements to shift bias circuit 10.One electric current source of supply, 14 supply of current to data line DL through transmission transistor 16.Transmission transistor 16 is by shifting bias voltage (Transfer BiasVol tage) V
xThe control Push And Release.An one P channel mos field effect transistor (P-ChannelMOSFET) 18 and a N channel mos field effect transistor 20 are for shifting the part of bias voltage network (Transfer Bias Network), shift the bias voltage network and can produce the transfer bias voltage, and, and provide reverse signal (Inverted Signal) V with the voltage reversal of data line DL
xControl end (gate) 17 to transmission transistor 16.Therefore if the voltage of data line DL rises, shift bias voltage and descend, then transmission transistor 16 is closed.A small amount of electric leakage to ground connection 24 can cause that data line DL voltage descends to data line DL from electric current supply 22.If data line DL voltage descends, shift bias voltage V
xRise and unlatching transmission transistor 16.The electric current that the flows through transmission transistor 16 data line DL voltage that can raise, so data line DL is biased to the little voltage of an amplitude of fluctuation.
Figure 1B is the simplified electrical circuit diagram of storage array 28 somes, among the figure and show a bit line 30.Bit line (BL) 30 is connected to the data line DL among Figure 1A and then is connected to transmission transistor 16 by switch 32, and switch 32 is by switching signal Y
sControl.One first character line WL0 control linkage is the memory cell of the first character line so far, and for example storage data is " 1 " memory cell 34.When this memory cell 34 was started by the first character line WL0, this memory cell 34 is conduction current between bit line (BL) 30 and ground connection.This kind memory cell is called low limit voltage memory cell.
One second character line WL1 controls another memory cell 36.This memory cell be non-conduction or high limit voltage memory cell and be in data value for " 0 " and state.Enumerate at this " 1 " with " 0 " only discuss for convenient, as the example of circuit running.The data value that is started by the character line is " 1 " memory cell of state can the conducting bit line to the electric current of ground connection.The memory cell that other character lines WLn control is other, and memory cell 38 is connected between the bit line BL ground connection 24.
Many memory cell all are connected to bit line BL, and memory cell load bit line and its initial voltage are low, but must not be ground voltage.Read when a memory cell is selected, this memory cell meeting pre-charge bit line to a voltage is to produce a memory cell electric current.For instance, if a low limit voltage memory cell is selected, and bit line is to be positioned at a low-voltage state (not by pre-charge), because small voltage difference makes indivisible memory cell electric current can flow through memory cell to ground connection between bit line and the ground connection.Such low current can make and must correctly read the necessary long time of memory cell.Bitline precharge can be improved the running speed of circuit.Some traditional circuits utilize clock signal (Clock Signal) with bitline precharge before reading memory cell.Sort circuit will further be discussed in according to Fig. 1 C, Fig. 1 D and Fig. 2 A following.
The a part of induction amplifier of a high limit voltage memory cell 36 (no current) and the simplified electrical circuit diagram of storage array are read in Fig. 1 C demonstration.Be positioned at the phase inverter 40 control transmission transistors of 42 of the gates of data line DL and transmission transistor 16.Therefore shift bias voltage V
xAnti-phase (Inverse) for data line voltage.When character line WL1 startup, high limit voltage memory cell is open circuit (Open Circuit) between bit line BL ground connection 24.Data line is precharged to a voltage, since high limit voltage memory cell does not import electric current from bit line, data line is precharged to high voltage slightly, makes to shift bias voltage V
xDescend, close transmission transistor 16.Therefore data are exported V
zBe high voltage, and data line DL keep its voltage.
Fig. 1 D is that a part of induction amplifier of a low limit voltage memory cell 34 and the simplified electrical circuit diagram of storage array are read in a demonstration.Data line DL is precharged to a voltage.If memory cell 34 conductings are from the electric current of bit line BL to ground connection 24, data line DL voltage descends (with reference to Figure 1B, showing to connect the switch 32 of bit line to data line).But the electric current of about 20 micromicroamperes of memory cell conducting.When data line DL voltage descends, shift bias voltage V
xRise, and transmission transistor 16 unlatchings are flow through the electric current of memory cell to ground connection with supply.Data output V
zReduce to a low voltage.Data are exported V
zReduce to a voltage that is lower than next stage reversal voltage (FlipPoint) (phase inverter that does not show is with reference to figure number 92 among the figure 3) in this figure and can read the data value of memory cell.
Fig. 2 A is the simplified electrical circuit diagram that tradition is used the induction amplifier 50 of timing pre-charge (Clocked Pre-charge) technology.Many memory cell (not shown) are connected to data line DL as shown in above-mentioned Figure 1B to Fig. 1 D.One bias circuit (Bias Network) 52 comprises a P-MOSFET54 and a N-MOSFET56, is similar to the bias circuit among Figure 1A, and the other FETs58 and 60 by induction amplifier control produces clock signal DE2.Clock signal DEA, DE1 and DE2 are shown in the upper right corner of Fig. 2 A, so that the running of this circuit can be understood easilier.These clock signals will more go through in Fig. 7.
Circuit uses pre-charge cycle clock signal (Pre-Charge Period ClockSignal) DEA by connecting switch (the reference symbol Y of data line DL to bit line among Fig. 2 A
s, Figure 1B) with pre-charge bit line (not shown).Pre-charge cycle clock signal DEA puts on the gate 64 of precharge transistor 62.Similarly situation is used for video data block signal DE1, reversal data block signal DE1B and induction amplifier enabling signal DE2.
In the pre-charge cycle, data output V
zBe set to a high voltage.If the memory cell that is read is a low limit voltage memory cell, electric current from switch (with reference to Figure 1B, switch 32) to bit line to ground connection, and data line DL voltage descends.When data line DL voltage descends, shift bias voltage V
x, transmission transistor 16 is opened, and makes the data output voltage descend.
If the memory cell that is read is a high limit voltage memory cell, not conducting of memory cell is from the electric current of data line DL (through bit line), and data line DL voltage is high a little, shifts bias voltage V
xDescend, transmission transistor 16 is closed.Therefore the data output voltage is kept higher relatively.
However, pre-charge cycle and cycle clock signal DEA synchronous (Timing) is very important.The gate 64 of clock signal DEA control precharge transistor 62.Opening the time of precharge transistor 62 must enough grow with pre-charge data line DL from V
DD(positive supply voltage), but can not be oversize.If the pre-charge cycle is oversize, circuit running speed can reduce.If the pre-charge cycle is too short, pre-charge may not finished, and the data of read error.Yet processing procedure change (Process Variation) can make and suitably control the pre-charge cycle difficulty that becomes in each processing procedure corner.
In this kind circuit, preset data voltage is " 0 ", also be the data output V of the gate 64 of precharge transistor 62
zHigh (V
zRising is higher than the rollback point of next phase inverter 68).In a typical storage array, when storing data " 1 " when (low limit voltage or conducting state), the size of current that different memory cell is introduced is all different.Terminal position (Tail Bit) or minimum memory born of the same parents electric current can be difficult to read, this be because flow through the low current of memory cell make the data output voltage keep the relative long period (with respect to the storage data of high electric current or average current " 1 " memory cell).This meaning reads terminal position to be needed long-time.In addition, the gate 64 with clock signal DEA unlatching precharge transistor 62 can cause a big pre-charge electric current and cause bit line overshoot (Overshoot).
Because preset data is output as " 0 ", setting data output V
zTo a high voltage, and data output V
zIn ground voltage, read a low limit voltage memory cell (when clock pulse signal DEA drops to carry out pre-charge) and cause data output V at first
zElder generation raises and then is reduced by the memory cell electric current.When reading a high limit voltage memory cell, the data output voltage V
zHeight, and data output V
zOnly due to leakage current descends a little.Therefore read storage data " 1 " the memory cell ratio read storage data " 0 " and memory cell need the long period, particularly if terminal position needs the relative long period produce data " 1 " output.Similarly, if data line DL by pre-charge De Taigao, shifts bias voltage V
xDescend, transmission transistor 16 is closed.When reading a low limit voltage memory cell, just must wait for that little memory cell electric current reduces data line voltage so that shift bias voltage V
xRaise, and data output V
zDescend.Therefore if data line DL by pre-charge De Taigao or overshoot (0vershoot), the running speed of circuit will reduce.
Fig. 2 B is the simplification generalized schematic of traditional induction amplifier 40, some problems that this traditional induction amplifier 40 has the induction amplifier among Fig. 2 A to have.In this circuit, a depletion type P-MOS transistor is used as a load transistor 70.This pre-charge path cuts off automatically, therefore just no longer need be with clock signal (with reference to the DEA among the figure 2A) the control pre-charge cycle.Omission can be saved used chip area and the required power consumption of clock pulse with the clock signal control pre-charge cycle.But in order to want abundant pre-charge data output V
z, transmission transistor 76 ' is relatively large with precharge transistor 72.For instance, precharge transistor 72 may have about 0.6 micron gate length and about 20 microns gate width, and transmission transistor 76 ' has about 0.6 micron gate length and about 6 microns gate width.These megacryst pipe load transfer bias voltages V
x, and the running speed of dragging slow induction amplifier.
This circuit has preset data output " 1 ", therefore avoiding when reading a low limit voltage memory cell, the V that discharges then at first charges
zProblem.Depletion type P-MOS load transistor 70 has the data of being connected to output V
zGate 74.For instance, export when bias circuit provides a high pressure, N type precharge transistor 76 is opened (transmission transistor 76 ' is also opened) and self-bias potential source V
DDSupply of current to data are exported V
z, pressure drop is through P type precharge transistor 72.When shifting bias voltage V
xWhen low, N type precharge transistor 76 is closed, and blocking-up is from V
DDTo V
zElectric current.But the limit voltage of precharge transistor is in shifting bias voltage V
xOnly can produce low electric conductivity passage (with respect to transmission transistor 76 ') when high.
But the data output voltage is higher than the about 200mV of data line DL voltage, and is not the reversal voltage (Flip Point) of next stage (induced inversion device 52).The gate of depletion load transistor 70 is connected to its source electrode, and as a load transistor, load data output V
zAnd drag induction slowly to move.Respond to a high limit voltage memory cell (" 0 " or no current) time, enough big electric current must be arranged, but this may cause a low limit voltage memory cell induced failure that is positioned at fast clock pulse angle (Fast Clock Corner).Pre-charge began action (with reference to the DEA among the figure 2A) when induction amplifier started.Data output V
zBe relative low-voltage.When reading low limit voltage memory cell, the memory cell electric current makes data line DL keep low-voltage and data are output as " 1 ".When reading high limit voltage memory cell, stop to move transmission transistor 76 ' in pre-charge and close, and data output V
zReversal voltage (Flip Point) and data that load transistor 70 loads are higher than next stage phase inverter 68 are output as " 0 ".When the data output voltage is increased to the demand voltage value, the pre-charge action stops automatically; But this demand voltage needn't be near the reversal voltage (Flip Point) of next stage phase inverter.
Fig. 2 C is the simplification generalized schematic of traditional induction amplifier 80.Load transistor 82 is an enhancement mode P-MOS transistor, is not depletion type P-MOS transistor, shown in Fig. 2 B, and depletion load transistor 70.Load transistor 82 also connects (its source electrode is connected to its gate) for diode.When induction amplifier did not start, even induction amplifier is in still producing the transistor 84 and 86 of electric current in next stage phase inverter 68 under the armed state, diode connection this moment made data output V
zBe about V
DD-V
TPSuch electric current is unfavorable for the element of battery operation.
Fig. 3 A is the rough schematic view of induction amplifier 90 of the present invention.In this circuit, one is positioned at data output V
zAnd the phase inverter 92 that the gate of precharge transistor 96 is 94 is set precharge voltage, and this precharge voltage is near the rollback point of phase inverter.Phase inverter 92 reversal datas output V
zTo induction amplifier output SA.When shifting bias voltage V
xOpen the data output V that transmission transistor 116, descends
zRising induction amplifier output SA, and open precharge transistor 96 and cause the data output voltage V
zRise.On the contrary, if the data output voltage V
zRise, SA descends then, closes precharge transistor 96 and makes the data output voltage V
zDescend.Therefore data are exported V
zBe biased into rollback point a little less than phase inverter 92.When reading high limit voltage memory cell, data line DL voltage rises, and reduces and shifts bias voltage V
xAnd close transmission transistor 116.Load transistor 98 rising data output voltage V
z, order about induction amplifier output SA and descend.Because precharge voltage is near the rollback point of phase inverter, load transistor only need be supplied small size voltage to be increased, and this load transistor can be relatively less than precharge transistor and transmission transistor.
Fig. 3 B answers the rough schematic view of phase inverter with the induction amplifier of control pre-charge for usability of the present invention.Phase inverter 92, one complementary pair transistors (Complementary pair oftransistors) 100 and 102 with reference to figure 3A form an induced inversion device 92 ', this phase inverter 92 ' reversal data output V
zTo induction amplifier output SA and provide the reversal data output voltage to precharge transistor 96.Induction amplifier only uses little layout area and can low-power operate.Induction amplifier does not need a pre-charge clock pulse, so the power consumption beyond chip area and the clock pulse can be saved.
Fig. 3 C shifts the rough schematic view of phase inverter with the induction amplifier of control pre-charge for the present invention uses.This induction amplifier also has a complementary pair transistor (Complementary pair oftransistors) 100 ' and 102 ', and this complementary pair transistor forms an induced inversion device 192, this induced inversion device 192 reversal datas output V
zTo induction amplifier output SA, but have transfer phase inverter (Trahsfer Inverter) 104 simultaneously, this shifts phase inverter 104 according to data output voltage control precharge transistor 106.Precharge voltage is to depend on the limit voltage that shifts phase inverter 104 and precharge transistor 106.Shifting phase inverter 104 is in transition zone (Transition Region) operation, and the bias point (Bias Point) of setting up precharge transistor 106 feeds back to data output V to provide
zThough use is independently shifted phase inverter and can be taken the chip area of sub-fraction and exhaust some power, can make the design of operating point (Operating Point) be independent of induced inversion device 192.Too not low V
DDThe power consumption that voltage increases is unlikely too high.Utilize CMOS induced inversion device to control precharge transistor, shown in Fig. 3 B, simple and consumption less power, but speed increases a little.
Induction amplifier output SA is that the gate of output transmission earlier (Pass Gate) 110 is then to exclusive circuit (Latching Circuit) 112.Exclusive circuit 112 comprises a phase inverter 114, and this phase inverter 114 is that second phase inverter 116 in loop or loop configuration is controlled by clock signal DE1 and DE1B and.Therefore export 118 (S
AB) be from the data value (not shown, with reference to Figure 1B to Fig. 1 D) of memory cell induction with locking.
The pre-charge level combines feasible induction action beginning after pre-charge is finished with the induction level.In other words, precharge transistor 106 is also as induction amplifier.Transmission transistor 116 ' is similar to the transmission transistor in other circuit in running, but specify a different reference symbol, because the characteristic of this transmission transistor, for example the length of its active region and width can suitably be adjusted to meet the performance requirement at the various induction amplifiers of operation condition design.
The circuit of Fig. 3 B and Fig. 3 C does not need a pre-charge clock signal (with reference to the DEA among the figure 2A).In data output V
zValue " 1 " time pre-charge cut off automatically.Opening pre-charge when induction amplifier promptly begins.Data output V
zMagnitude of voltage is a little less than the rollback point (figure number 192 of figure number 92 ' Fig. 3 C of Fig. 3 B) of next stage phase inverter.When reading a low limit voltage memory cell, electric current flows through memory cell, and transmission transistor 116 ' is opened, data output V
zMagnitude of voltage is the identical magnitude of voltage that starts from the pre-charge cycle.When reading a high limit voltage memory cell, electric current does not flow through memory cell, and transmission transistor 116 ' is closed, and data output V
zMagnitude of voltage is exported V by rollback point to the data that load transistor 98 ' is higher than next stage phase inverter (induced inversion device 192)
zValue " 0 ".Because primary data output V
zMagnitude of voltage is near the rollback point of next stage phase inverter, and the load of boosting is very fast and to read a high limit voltage memory cell also very quick.
The pre-charge path connects for feedback, no matter be to shift phase inverter by induced inversion device or, pre-charge slows down gradually, can avoid the generation of overshoot (Overshoot) when the timing of pre-charge clock pulse.Reading of terminal position is then more unimportant, because the preset data output valve be " 1 ", and the terminal position memory cell that is in low limit voltage state only need flow through by little electric current.
Fig. 4 A is the locking simplified electrical circuit diagram partly of induction amplifier circuit of the present invention.Wherein exclusive circuit 112 comprises a phase inverter 116, and phase inverter 116 is made of PMOS transistor 120 and nmos pass transistor 122.This exclusive circuit 112 can be used for the circuit of Fig. 3 B and Fig. 3 C.Even but be in non-operating state (not clock pulse timing or be ready) when exclusive circuit, also have electric current and flow through PMOS transistor 120.When reading a low limit voltage memory cell, data output V
zMagnitude of voltage is to be relative low voltage value, but is not ground voltage, and induction amplifier output SA is relative high-voltage value, but is not V
DDTherefore the DC electric current may flow through nmos pass transistor 122 and PMOS transistor 120.Such DC electric current is for 1.8V or more the circuit design of low-voltage may be able to accept, but then can not be accepted for the circuit with 3V or more high voltage running.
Fig. 4 B is another the locking simplified electrical circuit diagram partly of induction amplifier circuit of the present invention, and wherein exclusive circuit 112 ' is avoided the DC current problems of the circuit among Fig. 4 A.The PMOS transistor 124 that connects diode reduces the rollback point of phase inverter 116 ', so only there is very little electric current can flow through phase inverter to be hit.Under some operational scenario, the DC power consumption that this circuit can be saved induction amplifier circuit 25% with respect to the circuit among Fig. 4 A only need slightly gather way.Compare with the amplifier circuit among Fig. 4 A, induction speed may increase about 2nS.
Fig. 5 is the simplified electrical circuit diagram as the precharge transistor of current mirror, wherein mainly is load part 130.The gate 132 of load transistor 198 is connected to the gate 134 of another PMOS transistor 136, but not as the ground connection shown in Fig. 3 B and Fig. 3 C.This 2nd PMOS transistor 136 is connected with a memory cell, or a current source 138.PMOS transistor 136 is to be connected to diode.The electric current that flows through PMOS transistor 136 is because of connecting (Common GateConnection) by the common gate of the transistorized voltage drop bias voltage of PMOS.Can open load transistor 198 like this so that a part of electric current of memory cell electric current to be provided.Therefore load transistor can effectively be recalled tracking (Track) memory cell electric current and be formed a current mirror.One mini array can be used to provide with reference to memory cell.
By and large, flowing through the electric current of load transistor should be less than the on off state in slow corner and fast corner (Slow Cornerand Faster Corner) to avoid the locking misdata.Because the memory cell electric current may be unknown, so can calculate the worst situation; But this can not the optimization load paths.The electric current that flows through load transistor should be the some of memory cell electric current, and for example 70%.This can make and allow the memory cell electric current recall to follow the tracks of and improve inductive spacing and be weak (Weak) load.
Transmission transistor should be enough greatly keeping induction speed, but can not be greatly to making data output V
zDecay is because so may influence induction speed.The size of transmission transistor should select suitably to make that the clock pulse state in slow corner and fast corner all can obtain acceptable speed.If the character wire delay increases, the size of pre-charge/induction transistor and transmission transistor can reduce to reduce V
zDecay.If the character wire delay reduces, the size of pre-charge/induction transistor and transmission transistor is scalable to improve induction speed.
Induction amplifier of the present invention can be realized the irrealizable speed advantage of induction amplifier among Fig. 2 A, for instance, if character line earlier closing.With the induction amplifier among Fig. 2 B, in low V
DDDuring value, if work as Y
sThe character line can off switch speed improvement amplitude can reach 40ns during reduction.With reference to Figure 1B, Y
sBe the switching signal of the switch of a connection DL utmost point and a memory cell, switching signal Y
sControl data line DL is connected to bit line or memory cell.
Fig. 6 is the simplified flow chart 600 with the induction amplifier reading of data.Induction amplifier start (step 602) and data line (or bit line) before reading a memory cell by pre-charge (step 604).If memory cell is in a low limit voltage state, data promptly are read (step 606).If memory cell is in a high limit voltage state, data line voltage rises (step 608), reduces and shifts bias voltage (step 610), and this will close transmission transistor (step 612).When transmission transistor is closed, data output voltage load rise (step 614) is higher than the rollback point of induced inversion device, is read (step 606) preceding reduction induction amplifier output SA (step 616) in data.Therefore higher and data line is higher for a high limit voltage memory cell data output voltage, and lower and data line is lower for a low limit voltage memory cell data output voltage.
Fig. 7 is for comparing regularly the signal voltage of the induction amplifier of pre-charging circuit and the simplification clock pulse figure of the signal voltage of induction amplifier of the present invention when reading high limit voltage memory cell and low limit voltage memory cell.Simplify the simulation of reading of the running of the clock pulse timing induction amplifier of reading speed Figure 70 0 comparative example shown in Fig. 2 A and the induction amplifier shown in Fig. 3 B or Fig. 3 C.Clock signal DEA, DE1 and DE2 are shown in Fig. 7 top for your guidance.Showed for two clock pulse cycles among the figure, first clock pulse cycle 702 is more various reads a voltage when hanging down the limit voltage memory cell, and more various voltages when reading a high limit voltage memory cell of second clock pulse cycle 704.The a plurality of magnitudes of voltage of clock pulse timing induction amplifier of first sets of curves, 706 presentation graphs 2A.The 708 expression the present invention shown in Fig. 3 B or Fig. 3 C of second sets of curves have a plurality of magnitudes of voltage of the induction amplifier in automatic cut-out pre-charge path.Show among the figure and shift bias voltage V
x, data output V
z, induction amplifier output SA exports S with the locking data
ABFor more simple and clear, omit the numerical value of voltage, and relative magnitude of voltage is obvious and be easy to comparison, when a signal is inverted to another state from a state.
Data output V
zInitial voltage difference be stem from the preset data value (curve 706 " 0 " with curve 708 " 1 ").Before the induction amplifier of curve 706 is finished its charge cycle, the sensed (S of the data of the induction amplifier of curve 708
ABThe signal counter-rotating).This analog result shows the enhancement of the reading speed of the pre-interim 40ns of surpassing.
In the embodiment of the invention shown in above-mentioned Fig. 3 B and Fig. 3 C, data output is preset as " 1 " compared to data output is preset as " 0 " can save time.The latter may need bit-line voltage rising earlier to descend again, shown in Fig. 2 A.Data output is preset as " 1 " bias voltage data output V
zTo a reversal voltage (Flip Point) that just is lower than next stage, this next stage is generally a CMOS induced inversion device, also can improve speed.
Gate by connecting weak load transistor is to ground connection, but not with weak load transistor as a diode FET, avoided flowing through the DC leakage current of the CMOS phase inverter of data locking level.The gate ground connection of weak load transistor also can be reduced the load of DOL Data Output Line.Generally speaking, utilize induction amplifier of the present invention, the MROM component speeds of one 128 megabits is in low V
DDCan be promoted to 100ns by 200ns during value (as 1.8V), and need not waste arrangement space and unnecessary power consumption.
The present invention is according to the detailed description of the foregoing description.The various corrections that do not depart from spirit of the present invention and scope must be included in the present invention with change.For instance, use a positive bias V in the foregoing description
DD, but negative bias also can use, as long as suitably adjust the transistor kind.Similarly, an extra phase inverter can add the feedback path of the precharge transistor with P pass element.The element that uses in the foregoing description mostly is the element made from silicon, but also can use with the element of other different semiconductor material manufacturings." MOS " and transistor also can comprise use mix polysilicon or silicide and not necessarily metal as the element of conductor layer.Instructions only is explanation usefulness with diagram, but not should be restrictive condition, and the present invention is subject to the patent claim that claims are determined.
Claims (10)
1. one kind has an induction amplifier of the input utmost point that is connected to the bit line of storage array, it is characterized in that, comprises at least:
One transistor, described transistor have second conducting end that first conducting end and that is connected to the described input utmost point is connected to an output stage;
One phase inverter, described phase inverter have a phase inverter that is connected to described output stage and phase inverter output and import; And
One precharge transistor, it comprises:
One pre-charge control end, described pre-charge control end are connected to described phase inverter output;
One first pre-charge conducting end, the described first pre-charge conducting end is connected to a voltage source of supply, and described voltage source of supply provides a bias voltage, and
One second pre-charge conducting end, the described second pre-charge conducting end is connected to described output stage.
2. induction amplifier as claimed in claim 1 is characterized in that, described phase inverter is an induced inversion device, and described induced inversion device is to connect and transmit between the gate with one at described output stage.
3. the described induction amplifier of claim 1 is characterized in that, also comprises an induced inversion device, and described induced inversion device is to connect and transmit between the gate with one at described output stage.
4. the described induction amplifier of claim 1 is characterized in that, also comprises:
One data exclusive circuit, described data exclusive circuit comprises at least:
One data locking phase inverter, described data locking phase inverter has a complementary pair transistor, and described complementary pair transistor has a common gate, and described common gate is connected to an induced inversion device by a transmission gate; And
One diode connects, and described diode connects and between described voltage source of supply and described complementary pair transistor.
5. the described induction amplifier of claim 1, it is characterized in that, also comprise an induced inversion device, described induced inversion device is connected to described output stage and has a limit voltage, wherein, the described output stage of described precharge transistor is set a precharge voltage that is lower than the described limit voltage of described induced inversion device.
6. one kind has an induction amplifier of the input utmost point that is connected to the bit line of storage array, it is characterized in that described induction amplifier comprises at least:
One transmission transistor, described transmission transistor comprises at least: one first transmission conducting end, the described first transmission conducting end is connected to the described input utmost point; One second transmission conducting end, the described second transmission conducting end is connected to described output stage; Reach a transmission control end;
One first phase inverter, described first phase inverter have first phase inverter output that first phase inverter input and that is connected to the described input utmost point is connected to described transmission control end;
One second phase inverter, described second phase inverter have second phase inverter that is connected to described output stage to be imported, and described second phase inverter can provide a pre-charge bias to export in one second phase inverter;
One precharge transistor, described precharge transistor comprises a control end at least, described control end is connected to described second phase inverter output; One first conducting end, described first conducting end is connected to a voltage supply, and described voltage supply provides a bias voltage, and one second conducting end, and described second conducting end is connected to described output stage;
One load transistor, described load transistor comprises at least: one first load conducting end, the described first load conducting end is connected to described voltage supply, and one second load conducting end, and the described second load conducting end is connected to described output stage.
7. one kind has an induction amplifier of the input utmost point that is connected to the bit line of storage array, it is characterized in that described induction amplifier comprises at least:
One transmission transistor, described transmission transistor comprise at least one be connected to the described input utmost point first the transmission conducting end, with one be connected to described output stage second the transmission conducting end;
One phase inverter, described phase inverter have a phase inverter that is connected to described output stage and phase inverter output and import;
One precharge transistor, which comprises at least: a control end, described control end is connected to described phase inverter output, one first conducting end, described first conducting end is connected to a voltage source of supply, described voltage source of supply provides a bias voltage, and one second conducting end, and described second conducting end is connected to described output stage;
One load transistor, described load transistor comprises at least: one first load conducting end, the described first load conducting end is connected to described voltage supply; One second load conducting end, the described second load conducting end is connected to described output stage; And a gate terminal, described gate terminal is connected to an earthing potential; And
One exclusive circuit, described exclusive circuit comprises at least: a locking phase inverter, described locking phase inverter has a complementary pair transistor, and described complementary pair transistor has a common gate, and described common gate is connected to described phase inverter output; And
One diode connects, connect described complementary pair transistor and between described voltage supply and described earthing potential of described diode.
8. induction amplifier as claimed in claim 7, it is characterized in that, described induction amplifier comprises that at least one connects and the circuit between the control end of the input utmost point and at described transmission transistor, described circuit makes the electric conductivity of described transmission transistor when one first input pole tension lower, and making the electric conductivity of described transmission transistor when one second input pole tension higher, the described first input pole tension is higher than the described second input pole tension.
9. a method of operating induction amplifier is characterized in that, described method comprises at least:
Reverse one first output voltage of an output stage of described induction amplifier to produce a counter-rotating output;
The described counter-rotating that is coupled exports a control end of a precharge transistor to;
The described output stage to of pre-charge is lower than second output voltage of a limit voltage of a data locking level, and described data locking level has a locking that is connected to described output stage and imports;
Close a transistor, described transistor has second conducting end that first conducting end and that is connected to described output stage is connected to a data line;
And the described output stage to of load is higher than the 3rd output voltage of the described limit voltage of described data locking level.
10. an induction amplifier is characterized in that, described induction amplifier comprises at least:
One transmission transistor, described transmission transistor comprises at least: one first transmission conducting end, the described first transmission conducting end is connected to a bit line, one second transmission conducting end, the described second transmission conducting end is connected to a DOL Data Output Line, reach a transmission control end, described transmission control end is connected to one and shifts the bias voltage network;
One pre-charging circuit, described pre-charging circuit is connection and is positioned between voltage supply input and described DOL Data Output Line, described pre-charging circuit comprises a negative-feedback circuit at least, and described negative-feedback circuit is set up a precharge voltage in described DOL Data Output Line; And
One load transistor, described load transistor comprises at least: one first load conducting end, the described first load conducting end are connected to described voltage supply input; One second load conducting end, the described second load conducting end is connected to described DOL Data Output Line; And a load control sluice is extreme, and described gate terminal is connected to a ground-electrode.
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| CNB011250798A CN1154112C (en) | 2001-08-07 | 2001-08-07 | High-speed induction amplifier with automatic shutoff precharging path |
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|---|---|---|---|
| CNB011250798A CN1154112C (en) | 2001-08-07 | 2001-08-07 | High-speed induction amplifier with automatic shutoff precharging path |
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| CN1400603A true CN1400603A (en) | 2003-03-05 |
| CN1154112C CN1154112C (en) | 2004-06-16 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100449733C (en) * | 2004-04-26 | 2009-01-07 | 旺宏电子股份有限公司 | Operation scheme for spectrum shift in charge trapping non-volatile memory |
| CN100530437C (en) * | 2005-02-04 | 2009-08-19 | 冲电气工业株式会社 | Semiconductor memory device |
| CN1937071B (en) * | 2005-09-22 | 2010-10-13 | 中芯国际集成电路制造(上海)有限公司 | High-performance read-out amplifier for memory system and corresponding method |
| CN101866688A (en) * | 2009-04-14 | 2010-10-20 | 台湾积体电路制造股份有限公司 | Keeper, integrated circuit, and access method |
| CN101930791A (en) * | 2009-06-24 | 2010-12-29 | 索尼公司 | Storer and data processing method |
| CN104979000A (en) * | 2014-04-09 | 2015-10-14 | 力旺电子股份有限公司 | Sensing device and data sensing method thereof |
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2001
- 2001-08-07 CN CNB011250798A patent/CN1154112C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100449733C (en) * | 2004-04-26 | 2009-01-07 | 旺宏电子股份有限公司 | Operation scheme for spectrum shift in charge trapping non-volatile memory |
| CN100463138C (en) * | 2004-04-26 | 2009-02-18 | 旺宏电子股份有限公司 | Operation scheme with charge balancing erase for charge trapping non-volatile memory |
| CN100530437C (en) * | 2005-02-04 | 2009-08-19 | 冲电气工业株式会社 | Semiconductor memory device |
| CN1937071B (en) * | 2005-09-22 | 2010-10-13 | 中芯国际集成电路制造(上海)有限公司 | High-performance read-out amplifier for memory system and corresponding method |
| CN101866688A (en) * | 2009-04-14 | 2010-10-20 | 台湾积体电路制造股份有限公司 | Keeper, integrated circuit, and access method |
| CN101866688B (en) * | 2009-04-14 | 2013-07-24 | 台湾积体电路制造股份有限公司 | Keeper, integrated circuit, and access method |
| CN101930791A (en) * | 2009-06-24 | 2010-12-29 | 索尼公司 | Storer and data processing method |
| CN101930791B (en) * | 2009-06-24 | 2014-03-12 | 索尼公司 | Memory and data processing method |
| CN104979000A (en) * | 2014-04-09 | 2015-10-14 | 力旺电子股份有限公司 | Sensing device and data sensing method thereof |
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| Publication number | Publication date |
|---|---|
| CN1154112C (en) | 2004-06-16 |
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