TWI788987B - Memory cell for analog content-addressable memory and analog content-addressable memory device - Google Patents

Abstract

A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current magnitude control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current magnitude control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current magnitude control circuit is configured to output a passing current. When the input voltage of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.

Description

Memory cell for analog content addressable memory and analog content addressable memory device

The present invention relates to a memory cell for a content-addressable memory and a content-addressable memory device, and more particularly to a memory cell for an analog content-addressable memory and an analog content-addressable memory device.

With the development of memory technology, a Content-Addressable Memory (CAM) system is proposed. CAM is a special memory used for in-memory search, and can compare the input search word with the stored words in all columns in the array in a highly parallel manner. CAM provides very powerful functions in many applications of image (pattern) matching and searching.

Compared with the traditional ternary CAM (ternary CAM), analog CAM significantly increases the data density, and reduces the energy consumption and the area of the processing circuit in the memory. Analog CAM requires good memory cell stability and high array density. With the development of big data, a high-density analog CAM is required when searching and comparing data in a huge database. How to avoid misjudgment in data comparison when judging whether the search range matches the storage range is one of the directions that the industry is working on.

The present invention relates to a memory cell used for an analog content addressable memory and an analog content addressable memory device, which uses a current control circuit to fix the current levels corresponding to different input signals within the matching range, reducing data comparison misjudgment situation.

According to a first aspect of the present invention, a memory cell for an Analog Content-Addressable Memory (analog CAM) is proposed. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The N-type transistor has a first gate. The first gate of the N-type transistor is used for receiving a first input signal. The P-type transistor has a second gate. The second gate of the P-type transistor is used for receiving a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor for generating a conduction current. Wherein, when the input voltage of the first input signal and the input voltage of the second input signal are within a matching range, both the N-type transistor and the P-type transistor are turned on, and the corresponding conduction current is substantially a fixed current value . The matching range is related to the critical voltage of the N-type transistor, the critical voltage of the P-type transistor, and the fixed current value.

According to another aspect of the present invention, an analog content addressable memory device is proposed, comprising a word line driver circuit, a plurality of memory cells, a plurality of matching signal lines, a plurality of source lines, and a source line driver circuit , and a sense amplifier circuit. The word line driving circuit is used for providing a plurality of first input signals and a plurality of second input signals. Each memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The N-type transistor has a first gate. The first gate of the N-type transistor is used for receiving the corresponding first input signal. The P-type transistor has a second gate. The second gate of the P-type transistor is used for receiving the corresponding second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor for generating a conduction current. Each matching signal line is coupled to the corresponding memory cell. Each source line is coupled with the corresponding current control circuit. The source line driving circuit is coupled to the source lines. The sense amplifier circuit is coupled to the matching signal lines. Wherein, for a specific memory cell among the memory cells, when the input voltage corresponding to the first input signal of the specific memory cell and the input voltage corresponding to the second input signal of the specific memory cell are located in one of the specific memory cells When within the range, both the N-type transistor and the P-type transistor of the specific memory cell are turned on, and the conduction current of the specific memory cell is essentially a fixed current value. The matching range of a specific memory cell is related to the threshold voltage of the N-type transistor of the specific memory cell, the threshold voltage of the P-type transistor of the specific memory cell, and the fixed current value.

According to still another aspect of the present invention, an analog content addressable memory device is proposed, including a first word line driver circuit, a second word line driver circuit, a first N-channel NAND series group, a first A P-channel NAND series group, a plurality of first sense amplifier circuits, a plurality of second sense amplifier circuits, and a plurality of first and logic gates. The first word line driving circuit is used for providing a plurality of first input signals, and the second word line driving circuit is used for providing a plurality of second input signals. The first N-channel NAND series group includes a plurality of first N-channel NAND series. Each first N-channel NAND series is used for receiving the first input signals. Each first N-channel NAND series is further used to generate a first current. The first P-channel NAND series group includes a plurality of first P-channel NAND series. Each first P-channel NAND series is used to receive the second input signals, and each first P-channel NAND series is further used to generate a second current. The first sense amplifier circuits are respectively coupled to the first N-channel NAND series of the first N-channel NAND series group. The second sense amplifier circuits are respectively coupled to the first P-channel NAND series of the first P-channel NAND series group. Each of the first sense amplifier circuits and the second sense amplifier circuits has a critical current value. Each of the first and logic gates is coupled to a corresponding first sense amplifier circuit and a corresponding second sense amplifier circuit. One of the first and logic gates is a selected first and logic gate. When the currents of the first current and the second current corresponding to the selected first and logic gates are greater than or equal to the critical current value, the selected first and logic gates output a first logic value.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:

Please refer to FIG. 1 , which shows an operation diagram of an analog content-addressable memory (analog CAM) 100 . The analog content addressable memory 100 includes several analog CAM memory cells CL1. The analog CAM memory cells CL1 are arranged in rows R(1), R(2), R(3), R(4) to store several analog content. For example, the content stored in row R(1) is "0.00-1.00, 0.48-0.76, 0.00-0.15". "0.00~1.00" means that any value can match. The contents stored in row R(2) are "0.62-1.00, 0.25-0.63, 0.25-1.00". The contents stored in row R(3) are "0.26-0.61, 0.12-0.40, 0.00-1.00". The contents stored in row R(4) are "0.00-0.43, 0.00-0.28, 0.58-1.00". Several input signals S1 are input to the analog content addressable memory 100 . The content of the first input signal S1 is "0.81", the content of the second input signal S1 is "0.62", and the content of the third input signal S1 is "0.12".

These input signals S1 are compared with the contents stored in row R(1). "0.00~1.00, 0.48~0.76, 0.00~0.15" stored in column R(1) is a match. Since "0.81", "0.62" and "0.12" fall into "0.00-1.00", "0.48-0.76" and "0.00-0.15" respectively, the successful matching result Ry is output accordingly.

After these input signals S1 are compared with the contents stored in the row R(2), a result of unsuccessful matching Rn is output. After these input signals S1 are compared with the contents stored in the column R(3), a result of unsuccessful matching Rn is output. After these input signals S1 are compared with the contents stored in the column R(4), the result of unsuccessful matching Rn is output. That is to say, the analog content addressable memory 100 can store analog content, and any analog content matching the input signal S1 can be searched out.

Please refer to FIG. 2, which shows the analog CAM memory cell CL1. The analog CAM memory cell CL1 includes a first floating gate device MSn and a second floating gate device MSp. The first floating gate device MSn has an N-type channel, and the second floating gate device MSp has a P-type channel. The second floating gate device MSp is connected in series to the first floating gate device MSn. The first floating gate device MSn is an N-type metal oxide semiconductor (NMOS), and the second floating gate device MSp is a P-type metal oxide semiconductor (PMOS). The drain of the first floating gate device MSn is connected to a matching signal line ML, and the source of the first floating gate device MSn is connected to the source of the second floating gate device MSp. The drain of the second floating gate device MSp is connected to a source line SL. The input signal S1 is simultaneously input to the gates of the first floating gate device MSn and the second floating gate device MSp.

Please refer to FIG. 3, which shows the matching range MR of the analog CAM memory cell CL1. Curve CN is the characteristic curve of the first floating gate device MSn, and curve CP is the characteristic curve of the second floating gate device MSp. The steep slope of curve CN and curve CP is greater than 0.01 mV/dec. For example, the steep curves of curve CN and curve CP in Fig. 3 are 0.015 mV/dec. The first floating gate device MSn and the second floating gate device MSp are super steep slope devices.

In the analog CAM memory cell CL1, the threshold voltage of the first floating gate device MSn is lower than the threshold voltage of the second floating gate device MSp, so that the threshold voltage of the first floating gate device MSn and the second floating gate device The threshold voltages of MSp form a matching range MR. In the analog CAM memory cell CL1, the lower limit LB of the matching range MR is the critical voltage of the first floating gate device MSn, and the upper limit UB of the matching range MR is the critical voltage of the second floating gate device MSp.

As shown in Figure 2 and Figure 3, when the input signal S1 falls within the matching range MR, the first floating gate device MSn is turned on and the second floating gate device MSp is also turned on, thus forming a conduction current Ip. When the input signal S1 is not within the matching range MR, the first floating gate device MSn is not turned on or the second floating gate device MSp is not turned on, so the conduction current Ip will not be formed.

Please refer to FIG. 4 , which shows a circuit diagram of a memory cell 202 of an analog content addressable memory 200 according to an embodiment of the present disclosure. The analog content addressable memory 200 includes, for example, memory cells 202 and matching signal lines 204 . The memory cell 202 includes an N-type transistor 206 , a P-type transistor 208 and a current control circuit 210 . The N-type transistor 206 has a gate G1, and the gate G1 of the N-type transistor 206 is used for receiving the input signal B(i). The P-type transistor 208 has a gate G2, and the gate G2 of the P-type transistor 208 is used for receiving the input signal A(i). The current control circuit 210 is coupled to at least one of the N-type transistor 206 and the P-type transistor 208, such as being coupled to the P-type transistor 208, and the current control circuit 210 is used to generate at least one conduction current, such as Turn-on current I _pass . Wherein, when the input voltage of the input signal B(i) and the input voltage of the input signal A(i) are within the matching range, both the N-type transistor 206 and the P-type transistor 208 are turned on, and the corresponding conduction current I _{pass is} substantially The upper line is a fixed current value. The matching range is related to the threshold voltage 206 of the N-type transistor, the threshold voltage of the P-type transistor 208, and the fixed current value.

In this way, by using the current control circuit 210, the magnitude of the current flowing through the N-type transistor 206 and the P-type transistor 208 when the N-type transistor 206 and the P-type transistor 208 are turned on is fixed to the current magnitude of the current control circuit 210 . In this way, even though the input voltage of the input signal A(i) or B(i) may have multiple different levels, it still makes the N-type transistor 206 and the P-type transistor 208 flow through the N-type transistor 206 and the P-type transistor 208 when they are turned on. The current magnitudes of the transistors 208 are substantially the same. In this way, even though the input voltage of the input signal A(i) or B(i) may have multiple different levels, the discharge time on the matching signal line 204 connected to the memory cell 202 can still be made the same, so that the matching signal line 204 has a stable discharge time to reduce misjudgment.

As shown in FIG. 4 , the current control circuit 210 includes, for example, a control transistor 210A, and the control transistor 210A is a metal oxide semiconductor field effect transistor (MOSFET) or a floating gate (Float gate, FG) transistor. The drain D1 of the N-type transistor 206 is electrically connected to the matching signal line 204, the source S1 of the N-type transistor 206 is electrically connected to the source S2 of the P-type transistor 208, and the P-type transistor 208 The drain D2 is electrically connected to one end of the control transistor 210A (for example, the drain D3 of the control transistor 210A). The control transistor 210A has a gate G3, and the gate G3 of the control transistor 210A is used to receive the control voltage C(i), and the control voltage C(i) is substantially a fixed voltage value.

The other end of the control transistor 210A (for example, the source S3 of the control transistor 210A) is, for example, electrically connected to a source line SL. In one embodiment, the N-type transistor 206 and the P-type transistor 208 are 2D (two-dimensional) flash memory structure or 3D (two-dimensional) flash memory structure. In one embodiment, the N-type transistor 206 and the P-type transistor 208 can use F-N tunneling (Fowler-Nordheim tunneling, FN tunneling), channel hot electron injection technology (Channel Hot Electron, CHE) or polysilicon-to-polysilicon ( Poly to poly) way to program (program). During programming, the input voltage of the input signal A(i) and the input voltage of the input signal B(i) may be different. When performing data search and comparison, the input voltage of the input signal A(i) is the same as the input voltage of the input signal B(i). In one embodiment, the N-type transistor 206 and the P-type transistor 208 can be wiped by F-N tunneling, Band-To-Band Hot Hole (BTBHH) or polysilicon-to-polysilicon. Except (erase).

In one embodiment, the analog content addressable memory 200 is a flash memory. Flash memory is, for example, Charge storage memory, Charge trapping memory, Split gate memory or Ferroelectric field-effect transistor. transistor, FeFET) memory. In another embodiment, the analog content addressable memory 200 is a super steep slope flash memory. Ultra-steep flash memory is Thyristor Random Access Memory (TRAM), Gate Control Thyristor (Gate Control Thyristor, GCT), Tunnel Field-Effect Transistor (TFET) ) or Negative Capacitance Field-Effect Transistor (NCFET).

Please refer to FIG. 5A and FIG. 5B. FIG. 5A shows the matching range MR0 of the memory cell 202 without the current control circuit 210, and FIG. 5B shows the matching signal line 204 connected to the memory cell 202 in FIG. 5A. Graph of output voltage versus discharge time. Curve CN is the characteristic curve of N-type transistor 206, and curve CP is the characteristic curve of P-type transistor 208. The threshold voltage Vthp (eg, about −0.4V) defines the matching range MR0. When the N-type transistor 206 and the P-type transistor 208 operate in the subthreshold region, it is possible that the slopes of the curves CN and CP in the matching range MR0 are not steep enough. As shown in FIG. 5A and FIG. 5B, when the memory cell 202 does not have the current control circuit 210, when the input voltage of the input signals A(i) and B(i) is V1, the conduction current of the N-type transistor 206 is I1, so that the conduction current of the P-type transistor 208 is also I1. At this time, the turned-on N-type transistor 206 and P-type transistor 208 will cause the output voltage on the matching signal line 204 to drop from the original voltage Vms according to the curve V(I1), and drop to the point at time t2 to determine whether it is matched or not. The reference voltage Vref. Similarly, when the input voltage of the input signals A(i) and B(i) is V2, the conduction current of the N-type transistor 206 is I2, so that the output voltage on the matching signal line 204 changes from the original voltage Vms according to the curve V( I2) drops, and drops to the reference voltage Vref for judging whether there is a match at the time point t1. When the input voltage of the input signals A(i) and B(i) is V3, the conduction current of the N-type transistor 206 is I3, so that the output voltage on the matching signal line 204 drops from the original voltage Vms according to the curve V(I3) , and drops to the reference voltage Vref for judging whether to match at time point t3. Since the input voltages of different input signals A(i) and B(i) correspond to different conduction currents, the time for the output voltage on the matching signal line 204 to drop from the original voltage Vms to the reference voltage Vref is different. That is to say, for multiple input signals A(i) or B(i) with different voltage levels, since the current level when the matching signal line 204 discharges is not fixed, the matching signal connected to the memory cell 202 The discharge times on the lines 204 are different, so that the matching signal lines 204 have different discharge times. In this way, when searching and comparing the data inside the memory to judge whether the range of data stored in the memory cell and the input data match, the length of time required for the judging action becomes unstable, making the The chance of misjudgment increases.

Please refer to FIG. 6A and FIG. 6B. FIG. 6A shows the matching range MR1 of the memory cell 202 with the current control circuit 210, and FIG. 6B shows the output of the matching signal line 204 connected to the memory cell 202 in FIG. 6A The relationship between voltage and discharge time. The curve CN and the curve CP in Fig. 6A are the same as the curve CN and the curve CP in Fig. 5A. The matching range MR1 of the memory cell 202 with the current control circuit 210 is related to the threshold voltage of the N-type transistor 206, the threshold voltage of the P-type transistor 208, and the fixed current value. The matching range MR1 is, for example, when the N-type transistor 206 and the P-type transistor 208 are both turned on with the conduction current I _pass , the corresponding minimum gate voltage V4 of the N-type transistor 206 (greater than the critical value of the N-type transistor 206 voltage Vthn), and the maximum gate voltage V5 of the P-type transistor 208 (less than the threshold voltage Vthp of the P-type transistor 208). As shown in FIG. 6A and FIG. 6B, when the input voltage of the input signals A(i) and B(i) is V1, the conduction current of the N-type transistor 206 and the P-type transistor 208 is Ipass. At this time, the turned-on N-type transistor 206 and P-type transistor 208 will cause the output voltage on the matching signal line 204 to drop from the original voltage Vms according to the curve V, and drop to the reference voltage for judging whether there is a match at time point t4. Vref. Similarly, when the input voltages of the input signals A(i) and B(i) are V2 and V3, the conduction current of the N-type transistor 206 is still Ipass, so that the output voltage on the matching signal line 204 remains unchanged from the original voltage Vms. Decrease according to the curve V), and drop to the reference voltage Vref for judging whether to match at the time point t4 respectively. Since the input voltages of different input signals A(i) and B(i) correspond to the same conduction current Ipass, the discharge time for the output voltage on the matching signal line 204 to drop from the original voltage Vms to the reference voltage Vref is almost the same. . That is to say, when the memory cell 202 has the current control circuit 210, since the current magnitude when the matching signal line 204 discharges is fixed, the input voltages of different input signals connected to the matching signal line 204 of the memory cell 202 correspond to The discharge times of the two are substantially the same, so that the matching signal line 204 has a stable discharge time. In this way, when searching and comparing the data inside the memory to judge whether the data stored in the memory cell matches the input data, the time required for the judgment action is fixed, and the error of misjudgment is reduced. probability.

Please refer to FIG. 7 , which shows an example of applying the memory cell shown in FIG. 4 to an analog content addressable memory device 300 . The analog content addressable memory device 300 includes a word line driver circuit 302, a plurality of memory cells 304 (that is, the memory cells 202 in FIG. 4 ), a plurality of matching signal lines 312, a plurality of source lines 314, source line drivers The circuit 316 and the sense amplifier circuit (Sense Amplifier) 318 . The word line driving circuit 302 is used for providing a plurality of input signals B(1), B(2), . . . , B(n) and a plurality of input signals A(1), A(2, . . . , A(n). Each memory cell 304 of the analog content addressable memory device 300 includes an N-type transistor 306, a P-type transistor 308, and a current control circuit 310. The N-type transistor 306 of each memory cell 304 has a gate G1, and each memory cell 304 The gate G1 of the N-type transistor 306 is used to receive the corresponding input signal B(i), i is a positive integer from 1 to n. The P-type transistor 308 of each memory cell 304 has a gate G2, and each memory cell 304 The gate G2 of the P-type transistor 308 is used to receive the corresponding input signal A(i). The current control circuit 310 is coupled to the P-type transistor 308 to generate the conduction current I _pass . Each matching signal line 312 is coupled Connected to the corresponding memory cell 304, each source line 314 is coupled to the corresponding current control circuit 310. The source line driver circuit 316 is coupled to a plurality of source lines 314, and the sense amplifier circuit 318 is coupled to a plurality of matching signals Line 312. Wherein, for a specific memory cell 304(j, i) (j is an integer between 1 and m) among the memory cells, when the input corresponding to the specific memory cell 304(j, i) When the input voltage of the signal B(i) and the input voltage of the input signal A(i) corresponding to the specific memory cell 304(j, i) are within the matching range of the specific memory cell 304(j, i), the specific memory cell The N-type transistor 306 and the P-type transistor 308 of 304(j, i) are both turned on, and the conduction current _Ipass of the specific memory cell 304(j, i) is substantially a fixed current value. The specific memory cell 304( The matching range of j, i) is the critical voltage of the N-type transistor 306 of the specific memory cell 304 (j, i), the critical voltage of the P-type transistor 308 of the specific memory cell 304 (j, i), and this fixed related to the current value.

When programming or erasing a plurality of memory cells 304 (eg memory cell 304(1, 1) to memory cell 304(m, n)), the input signal A(i) may be different from the input signal B(i) . When the input signals A(1) to A(n) are compared with the contents stored in the memory cells 304 in the first to mth columns, the input signal A(i) is the same as the input signal B(i).

For example, when the input signal A(1) to the input signal A(n) are compared with the contents stored in the memory cell 304(1, 1) to the memory cell 304(m, n) in the first column to the mth column Timing, assuming that the input signal A(1) to the input signal A(n) are respectively within the matching range of the memory cell 304(1, 1) to the memory cell 304(1, n) in the first row, it means the input signal A (1) The content of the input signal A(n) matches the content stored in the memory cells 304(1, 1) to 304(1, n) of the first column. That is to say, the analog values corresponding to the input signal A(1) to the input signal A(n) are determined by the matching ranges of the memory cell 304(1, 1) to the memory cell 304(1, n) respectively located in the first column within the corresponding analog value range. At this moment, the memory cell 304(1, 1) to the memory cell 304(1, n) in the first column are all turned on and current flows, so as to pull down the voltage of the matching signal line 312(1), so that the sense amplifier The circuit 318 detects a successful match result.

And if any one of the input signal A(1) to the input signal A(n) is not within the matching range of the memory cell 304(1, 1) to the memory cell 304(1, n) in the first column, it means the input signal The contents of A(1) to input signal A(n) do not match the contents of memory cells 304(1, 1) to 304(1, n) stored in row 1. That is to say, the analog values corresponding to the input signal A(1) to the input signal A(n) are not completely located in the matching range of the memory cell 304(1, 1) to the memory cell 304(1, n) in the first column within the corresponding analog value range. At this time, at least one of the memory cell 304(1, 1) to the memory cell 304(1, n) in the first column will not be turned on, so that the voltage of the matching signal line 312(1) will not be pulled down to be lower than the reference voltage Vref. In this way, the sense amplifier circuit 318 will detect an unsuccessful matching result. That is to say, the analog content addressable memory 300 can store analog content, any analog content matching the input signal A(1) to the input signal A(n) (for example, the analog content stored in the memory cell 304 of a row) can be searched out.

By using the memory cell shown in FIG. 4, the analog content addressable memory device 300 can search and compare data inside the memory to determine whether the data stored in the memory cell matches the input data. The voltage of the matching signal line 312 can be reduced by a fixed current for the turned-on memory cells, and the time for the voltage drop of the matching signal line 312 can be controlled to reduce the probability of misjudgment.

Please refer to FIG. 8 , which shows a circuit diagram of a memory cell 400 of an analog content addressable memory according to another embodiment of the present disclosure. The memory cell 400 includes an N-type transistor 402, a P-type transistor 404, a current control circuit 406, and a logic gate 408. The N-type transistor 402 has a gate G1, and the gate G1 of the N-type transistor 402 is used to receive an input signal. B(i). The P-type transistor 404 has a gate G2, and the gate G2 of the P-type transistor 404 is used for receiving the input signal A(i). The current control circuit 406 has a first sense amplifier 406A and a second sense amplifier 406B. The AND logic gate 408 is coupled to the first sense amplifier 406A and the second sense amplifier 406B, and each of the first sense amplifier 406A and the second sense amplifier 406B has a threshold current value. The N-type transistor 402 is electrically connected to the first sense amplifier 406A, and the P-type transistor 404 is electrically connected to the second sense amplifier 406B. When the input voltage of the input signal B(i) and the input voltage of the input signal A(i) are within the matching range, at least one of the conduction currents I1 corresponding to the N-type transistor 402 and at least one of the conduction currents corresponding to the P-type transistor 404 The other I2 of the conduction current is greater than or equal to the critical current value, and the logic gate 408 outputs a first logic value.

Please refer to FIG. 8 and FIG. 9 at the same time, wherein FIG. 9 shows a schematic diagram of the matching range of the memory cell 400 with the current control circuit 406 . The matching range is related to the threshold voltage Vthn of the N-type transistor 402 , the threshold voltage Vthp of the P-type transistor 404 , and the threshold current values of the first sense amplifier 406A and the second sense amplifier 406B. As shown in FIG. 9, when the critical current value of the first sense amplifier 406A and the second sense amplifier 406B is the critical current value Ith1, the matching range MRa is when the conduction current of the N-type transistor 402 is the critical current value Ith1. The gate voltage V1' and the conduction current of the P-type transistor 404 are determined by the gate voltage V6' of the critical current value Ith1. When the critical current value of the first sense amplifier 406A and the second sense amplifier 406B is the critical current value Ith2, the matching range MRa is the gate voltage V2' and P where the conduction current of the N-type transistor 402 is the critical current value Ith2. The conduction current of the type transistor 404 is determined by the gate voltage V5' of the critical current value Ith1. When the critical current value of the first sense amplifier 406A and the second sense amplifier 406B is the critical current value Ith3, the matching range MRa is the gate voltage V3' and P where the conduction current of the N-type transistor 402 is the critical current value Ith3. The conduction current of the transistor 404 is determined by the gate voltage V4' of the critical current value Ith1.

The critical current value Ith1 of the first sense amplifier 406A and the second sense amplifier 406B is taken as an example for illustration. Please refer to Figure 8 and Figure 9 at the same time. When the input voltage of the input signal A(i) and the input voltage of the input signal B(i) are within the matching range MRa, the N-type transistor 402 generates the first current I1, and the P-type transistor 404 generates the second current I2. When both the first current I1 and the second current I2 are greater than or equal to the critical current values of the first sense amplifier 406A and the second sense amplifier 406B, the first sense amplifier 406A and the second sense amplifier 406B will output the first logic Value, such as logical value 1. When the input of the two input ends of the AND logic gate 408 is the first logic value, the AND logic gate 408 will output the first logic value (for example, logic value 1), to indicate the input voltage of the input signal A(i) and the input The input voltages of the signal B(i) are all within the matching range MRa.

Therefore, according to the embodiment shown in FIG. 8, the first sense amplifier 406A and the second sense amplifier 406B of the memory cell 400 can respectively operate in a matching range when the input signal A(i) and the input signal B(i) are within the matching range. The critical current values of the first sense amplifier 406A and the second sense amplifier 406B are the same to determine whether the N-type transistor 402 and the P-type transistor 404 are on, so as to reduce the probability of misjudgment.

Please refer to FIG. 10 , which shows a circuit diagram of an analog content addressable memory device 500 using the memory cells of FIG. 8 . The analog content addressable memory device 500 includes a first word line driver circuit 502, a second word line driver circuit 504, a first N-channel NAND string group 506, a first P-channel NAND string group 508, a plurality of A sense amplifier circuit 510(1), 510(2), ..., 510(n), a plurality of second sense amplifier circuits 512(1), 512(2), ..., 512(n) and a plurality of the first One and logic gates 514(1), 514(2), . . . , 514(n). The first word line driving circuit 502 is used to provide a plurality of first input signals SL1(1), SL1(2), ..., SL1(m), and the second word line driving circuit 504 is used to provide a plurality of second input signals Signals SL2(1), SL2(2), …, SL2(m). The first N-channel NAND series group 506 includes a plurality of first N-channel NAND series 516(1), 516(2), ..., 516(n), and each first N-channel NAND series 516 is used to receive the first Input signals SL1(1), SL1(2), ..., SL1(m), each of the first N-channel NAND series 516 is further used to generate a first current, for example, the first N-channel NAND series 516(1), 516 (2), ..., 516(n) generate first currents I1(1), I1(2), ..., I1(n) respectively. The first P-channel NAND series group 508 includes a plurality of first P-channel NAND series 518(1), 518(2), ..., 518(n), and each first P-channel NAND series 518 is used to receive the second Input signals SL2(1), SL2(2), …, SL2(m). Each first P-channel NAND series 518 is further used to generate a second current, for example, the first P-channel NAND series 518(1), 518(2), . . . , 518(n) respectively generate a second current I2(1 ), I2(2), …, I2(n). A plurality of first sense amplifier circuits 510(1), 510(2), ..., 510(n) are respectively coupled to the first N-channel NAND series 516(1) of the first N-channel NAND series group 506 , 516(2), …, 516(n). The second sense amplifier circuits 512(1), 512(2), ..., 512(n) are respectively coupled to a plurality of first P-channel NAND series 518(1) of the first P-channel NAND series group 508 , 518(2), ..., 518(n), the first sense amplifier circuits 510(1), 510(2), ..., 510(n) and the second sense amplifier circuits 512(1), 512(2 ), …, 512(n) each have a critical current value. Each of the first and logic gates is coupled to a corresponding first sense amplifier circuit 510 and a corresponding second sense amplifier circuit 512 . One of the first sum logic gates 514(1), 514(2), . . . , 514(n) is the selected first sum logic gate 514(i) (i is a positive integer from 1 to n). When the currents of the first current I1(i) and the second current I2(i) corresponding to the selected first and logic gate 510(i) are greater than or equal to the critical current value, the selected first and logic gate 514(i ) outputs a first logic value to the decoder 520. At this time, the decoder 520 will judge that the data provided by the first word line driving circuit 502 matches the data stored in the first N-channel NAND series 516(i), and the data provided by the second word line driving circuit 504 The data matches the data stored in the first P-channel NAND string 518(i).

Therefore, according to FIG. 9, the first sense amplifier circuit 510(i) and the second sense amplifier circuit 512(i) of the analog content addressable memory device 500 can be respectively in the first current I1(i) and the second current I1(i). When the current I2(i) is greater than or equal to the same current level, that is, the critical current value of the first sense amplifier circuit 510(i) and the second sense amplifier circuit 512(i), the first sense amplifier circuit The sense amplifier circuit 510(i) and the second sense amplifier circuit 512(i) output a first logic value. In this way, when searching and comparing the analog data inside the memory, it is possible to avoid the length of time required to detect whether the match is due to the difference in magnitude of the first current I1(i) or the second current I2(i) discrepancies, resulting in misjudgment.

Furthermore, as shown in FIG. 10, one end of the first N-channel NAND series 516(i) of the first N-channel NAND series group 506 is used to receive the first bit line signal BL1(i). The other end of the first N-channel NAND series 516(i) of an N-channel NAND series group 506 is coupled to the corresponding first sense amplifier circuit 510(i). One end of the first P-channel NAND series 518(i) of the first P-channel NAND series group 508 is used to receive the second bit line signal BL2(i), and the first P channel of the first P-channel NAND series group 508 The other end of the channel NAND series 518(i) is coupled to the second sense amplifier circuit 512(i). The first N-channel NAND series 516(i) of the first N-channel NAND series group 506 includes a plurality of first N-type transistors, and the first P-channel NAND series 518(i) of the first P-channel NAND series group 508 ( i) including a plurality of first P-type transistors. The gates of the first N-type transistors of the first N-channel NAND series 516(i) are used to receive the first input signals SL1(1), SL1(2), . . . , SL1(m). The gates of the first P-type transistors of the first P-channel NAND series 518(i) are used to receive the second input signals SL2(1), SL2(2), . . . , SL2(m).

Assume that the range of data stored in one of the first N-channel NAND series (for example, the first N-channel NAND series 516(i), where i is a positive integer from 1 to n) matches the input signal. When the first input signal SL1(1), SL1(2), . When the storage ranges match, that is, the voltage levels of the first input signals SL1(1), SL1(2), . When the memory cell is within the matching range, the first N-channel NAND series 516(i) will output the first current I1(i). Similarly, when the second input signal SL2(1), SL2(2), . When the storage ranges of the memory cells match, that is, the voltage levels of the second input signals SL2(1), SL2(2), ..., SL2(m) are respectively located in the first P-channel NAND series 518(i) When the m memory cells are within the matching range, the first P-channel NAND series 518(i) will output the second current I2(i). At this time, when the currents of the first current I1(i) and the second current I2(i) are greater than or equal to the critical current value, the first logic gate 514(i) outputs a first logic value, representing the first word The data provided by the word line driver circuit 502 matches the data stored in the first N-channel NAND series 516(i), and the data provided by the second word line driver circuit 504 matches the data stored in the first P-channel NAND series 518(i) stored data match.

In one embodiment, the first N-channel NAND series set 506 and the first P-channel NAND series set 508 are 2D flash memory structure or 3D flash memory structure. In one embodiment, the first N-channel NAND series 506 and the first P-channel NAND series 508 can be programmed using F-N tunneling, channel hot electron injection or polysilicon-to-polysilicon. In one embodiment, the first N-channel NAND series 506 and the first P-channel NAND series 508 can be erased by F-N tunneling, band-to-band hot hole injection or polysilicon to polysilicon.

In one embodiment, the analog content addressable memory device 500 is a flash memory, and the flash memory is a charge storage memory, a charge trapping memory, a split gate memory, or a ferroelectric field effect transistor. Memory. In another embodiment, the analog content addressable memory device 500 is an ultra-steep flash memory, and the ultra-steep flash memory is a thyristor random access memory, a gate-controlled thyristor, a tunneling field effect crystal, or negative capacitance field effect transistor.

Please refer to FIG. 11 , which shows an analog content addressable memory device 600 according to another embodiment. The analog content addressable memory device 600 includes the analog content addressable memory device 500 of FIG. 10, a third word line driver circuit 602, a fourth word line driver circuit 604, a second N-channel NAND serial group 606, The second P-channel NAND series group 608, a plurality of third sense amplifier circuits 610(1), 610(2), ..., 610(n), a plurality of fourth sense amplifier circuits 612(1), 612( 2), ..., 612(n), a plurality of second sum logic gates 614(1), 614(2), ..., 614(n) and a plurality of third sum logic gates 622(1), 622(2) , …, 622(n). The third word line driving circuit 602 is used for providing a plurality of third input signals SL3(1), SL3(2), ..., SL3(m), and the fourth word line driving circuit 604 is used for providing a plurality of fourth input signals Signals SL4(1), SL4(2), …, SL4(m). The second N-channel NAND series group 606 includes a plurality of second N-channel NAND series 616(1), 616(2), ..., 616(n), and each second N-channel NAND series is used to receive a third input Signals SL3(1), SL3(2), …, SL3(m). Each second N-channel NAND series is further used to generate a third current, for example, the second N-channel NAND series 616(1), 616(2), . . . , 616(n) respectively generate a third current I3(1) , I3(2), …, I3(n). The second P-channel NAND string group 608 includes a plurality of second P-channel NAND strings 618(1), 618(2), . . . , 618(n). Each second P-channel NAND series is used to receive a fourth input signal SL4(1), SL4(2), ..., SL4(m), and each second P-channel NAND series is further used to generate a fourth current, for example The second P-channel NAND series 618(1), 618(2), ..., 618(n) generate fourth currents I4(1), I4(2), ..., I4(n) respectively. The third sense amplifier circuits 610(1), 610(2), . 616(2), ..., 616(n), a plurality of fourth sense amplifier circuits 612(1), 612(2), ..., 612(n) are coupled to the second P-channel NAND series group 608 A plurality of second P-channel NAND strings 618(1), 618(2), ..., 618(n), a plurality of third sense amplifier circuits 610(1), 610(2), ..., 610(n) Each of the plurality of fourth sense amplifier circuits 612(1), 612(2), . . . , 612(n) has a critical current value. Each second and logic gate 614(1), 614(2), . . . , 614(n) is coupled to a corresponding third sense amplifier circuit and a corresponding fourth sense amplifier circuit. Each third sum logic gate 622(1), 622(2), . . . , 622(n) is coupled to a corresponding first sum logic gate and a corresponding second sum logic gate. Wherein, one of the second sum logic gates 614(1), 614(2), . . . , 614(n) is the selected second sum logic gate 614(i), where i is a positive integer from 1 to n. When the currents of the third current I3(i) and the fourth current I4(i) corresponding to the selected second and logic gate 614(i) are greater than or equal to the critical current value, the selected second and logic gate 614( i) Output the first logic value. One of the third sum logic gates 622(1), 622(2), ..., 622(n) is the selected third sum logic gate 622(i). When the first sum logic gate 514(i) and the second sum logic gate 614(i) corresponding to the selected third sum logic gate 622(i) both output the first logic value, the selected third sum logic gate 622 (i) Output the first logical value.

As shown in FIG. 11, one end of each second N-channel NAND series 616(1), 616(2), ..., 616(n) of the second N-channel NAND series group 606 is used to receive a third bit Bit line signals, for example, the second N-channel NAND series 616(1), 616(2), ..., 616(n) respectively receive the third bit line signals BL3(1), BL3(2), ..., BL3( n). The other end of each second N-channel NAND series 616(1), 616(2), ..., 616(n) of the second N-channel NAND series group 606 is coupled to the corresponding third sense amplifier circuit, for example Each second N-channel NAND series 616(1), 616(2), ..., 616(n) is respectively coupled to a third sense amplifier circuit 610(1), 610(2), ..., 610(n) . One end of each second P-channel NAND series 618(1), 618(2), ..., 618(n) of the second P-channel NAND series group 608 is used to receive the fourth bit line signal, for example, the second P Channel NAND series 618(1), 618(2), ..., 618(n) receive fourth bit line signals BL4(1), BL4(2), ..., BL4(n). The other end of each second P-channel NAND series 618(1), 618(2), ..., 618(n) of the second P-channel NAND series group 608 is coupled to the corresponding fourth sense amplifier circuit, for example The other end of the second P-channel NAND series 618(1), 618(2), ..., 618(n) is coupled to the fourth sense amplifier circuit 612(1), 612(2), ..., 612(n ). Each second N-channel NAND series of the second N-channel NAND series group 606 includes a plurality of second N-type transistors. Each second P-channel NAND series of the second P-channel NAND series group 608 includes a plurality of second P-type transistors. The gates of each second N-type transistor of each second N-channel NAND series are used to receive the corresponding third input signal. The gates of each second P-type transistor of each second P-channel NAND series are used to receive the corresponding fourth input signal. Therefore, according to the embodiment of FIG. 11, the first sense amplifier circuit 510(1), 510(2), . . . , 510(n), the second sense amplifier circuit 512( 1), 512(2), ..., 512(n), third sense amplifier circuits 610(1), 610(2), ..., 610(n) and fourth sense amplifier circuits 612(1), 612 (2), ..., 612(n) respectively correspond to the first input signal SL1(1), SL1(2), ..., SL1(m), the second input signal SL2(1), SL2(2), ..., SL2(m), third input signals SL3(1), SL3(2), ..., SL3(m) and fourth input signals SL4(1), SL4(2), ..., SL4(m). When the third input signal SL3(1), SL3(2), . When the storage ranges match, that is, the voltage levels of the third input signals SL3(1), SL3(2), ..., SL3(m) are respectively located in m of the second N-channel NAND series 616(i) When the memory cell is within the matching range, the second N-channel NAND series 616(i) will output the third current I3(i). Similarly, when the fourth input signal SL4(1), SL4(2), ..., SL4(m) provided by the fourth word line driver circuit 604 is connected to m When the storage ranges of the two memory cells match, that is, the voltage levels of the fourth input signals SL4(1), SL4(2), ..., SL4(m) are respectively located in the second P-channel NAND series 618(i) When the m memory cells are within the matching range, the second P-channel NAND series 618(i) will output the fourth current I4(i). At this time, when the currents of the third current I3(i) and the fourth current I4(i) are both greater than or equal to the critical current value, the second logic gate 614(i) outputs a first logic value, representing the third word The data provided by the word line driver circuit 602 matches the data stored in the second N-channel NAND series 616(i), and the data provided by the fourth word line driver circuit 604 matches the data stored in the second P-channel NAND series 618(i) The stored data matches.

When the first sum logic gate 514(i) outputs the first logic value and the second sum logic gate 614(i) outputs the first logic value, the third sum logic gate 622(i) will output the first logic value. As shown in FIG. 11 , when i=2, the third AND logic gate 622 ( 2 ) will output the first logic value (eg logic value “1”) to the decoder 620 . At this time, the decoder 620 will judge that the data provided by the first word line driving circuit 502 matches the data stored in the first N-channel NAND string 516(i), and the data provided by the second word line driving circuit 504 The data matches the data stored in the first P-channel NAND string 518(i), and the data provided by the third word line driver circuit 602 matches the data stored in the second N-channel NAND string 616(i). , and the data provided by the fourth word line driver circuit 604 matches the data stored in the second P-channel NAND string 618(i). In this way, by analogy to the content addressable memory device 600, the amount of data to be searched (that is, the amount of input signals) can be increased, for example, the data provided by the third word line driver circuit 602 and the fourth word line driver circuit 604 can be increased. The provided data is used for data search and comparison to improve the performance of the analog content addressable memory. Furthermore, the ADAM device 600 can further reduce the size of the N-channel NAND series and the P-channel NAND series, so as to reduce the RC delay and speed up the response speed of the ADAM device.

According to the above-mentioned embodiment, the memory cell of the analog content addressable memory and the analog content addressable memory device proposed in this case use the current control circuit to fix the current level of different input signals within the matching range, so that the discharge of the matching signal line The time is stable to reduce the probability of misjudgment during data search and comparison, and to speed up the processing speed of analog content addressable memory devices.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

100, 200, 400: analog content addressable memory 202, 304: memory cell 204, 312, ML: matching signal line 206, 306, 402: N-type transistor 208, 308, 404: P-type transistor 210, 310, 406: current control circuit 210A, 310A: control transistor 300, 500, 600: analog content addressable memory Bulk device 302: word line drive circuit 314, SL: source line 316: source line drive circuit 318: sense amplifier circuit 406A: first sense amplifier 406B: second sense amplifier 408: and logic gate 502: First word line driving circuit 504: second word line driving circuit 506: first N-channel NAND string group 508: first P-channel NAND string group 510(1), 510(2), 510(n) : first sense amplifier circuits 512(1), 512(2), 512(n): second sense amplifier circuits 514(1), 514(2), 514(n): first and logic gates 516( 1), 516(2), 516(n): first N-channel NAND series 518(1), 518(2), 518(n): first P-channel NAND series 520, 620: decoder 602: third Word line driving circuit 604: fourth word line driving circuit 606: second N-channel NAND string group 608: second P-channel NAND string group 610(1), 610(2), 610(n): the first Three sense amplifier circuits 612(1), 612(2), 612(n): fourth sense amplifier circuits 614(1), 614(2), 614(n): second and logic gates 616(1) , 616(2), 616(n): the second N-channel NAND series 618(1), 618(2), 618(n): the second P-channel NAND series 622(1), 622(2), 622(n): third logic gate S1, A(1), A(2), A(n), B(1), B(2), B(n): input signal CL1: analog CAM memory cell R(1), R(2), R(3), R(4): column Rn: matching unsuccessful result Ry: matching successful result MSn: first floating gate device MSp: second floating gate device Ip, I _pass : conduction current MR, MR0, MR1, MRa, MRb, MRc: matching range CN, CP: curve LB: lower limit UB: upper limit G1, G2, G3: gate D1, D2, D3: drain S1, S2, S3: source C(1), C(2),..., C(n), C(i): control voltage I1(1), I1(2), I1(n): first current I2(1) , I2(2), I2(n): the second current I3(1), I3(2), I3(n): the third current I4(1), I4(2), I4(n): the fourth current SL1(1), SL1(2 ), SL1(m): the first input signal SL2(1), SL2(2), SL2(m): the second input signal SL3(1), SL3(2), SL3(m): the third input signal SL4 (1), SL4(2), SL4(m): the fourth input signal BL1(1), BL1(2), BL1(3), BL1(n): the first bit line signal BL2(1), BL2 (2), BL2(3), BL2(n): second bit line signal BL3(1), BL3(2), BL3(3), BL3(n): third bit line signal BL4(1) , BL4(2), BL4(3), BL4(n): the fourth bit line signal

Figure 1 shows a schematic diagram of the operation of an analog content-addressable memory (analog CAM); Figure 2 shows an analog CAM memory cell; Figure 3 shows the matching range of the analog CAM memory cell; FIG. 4 shows a circuit diagram of a memory cell of an analog content addressable memory according to an embodiment; Figure 5A shows the matching range of a memory cell without a current control circuit; Figure 5B shows the relationship between the output voltage and the discharge time of the matching signal line connected to the memory cell in Figure 5A; Figure 6A shows the matching range of a memory cell with a current control circuit; Figure 6B shows the relationship between the output voltage and the discharge time of the matching signal line connected to the memory cell in Figure 6A; FIG. 7 shows an example of applying the memory cell shown in FIG. 4 to an analog content addressable memory device 300; FIG. 8 shows a circuit diagram of a memory cell of an analog content addressable memory according to another embodiment; FIG. 9 shows a schematic diagram of a matching range of a memory cell with a current control circuit; FIG. 10 shows a circuit diagram of an analog content addressable memory device using the memory cells of FIG. 8. FIG. 11 illustrates an analog content addressable memory device according to another embodiment.

200: Analog Content Addressable Memory

202: memory cell

204: Matching signal line

206: N-type transistor

208: P-type transistor

210: current control circuit

210A: control transistor

A(i), B(i): input signal

C(i): control voltage

G1, G2, G3: gate

D1, D2, D3: drain

S1, S2, S3: source

I _pass : pass current

SL: source line

Claims (20)

A memory cell for an analog content-addressable memory (analog content-addressable memory, analog CAM), the memory cell comprising: An N-type transistor has a first gate, and the first gate of the N-type transistor is used to receive a first input signal; A P-type transistor has a second gate, and the second gate of the P-type transistor is used to receive a second input signal; and A current control circuit, coupled to at least one of the N-type transistor and the P-type transistor, for generating at least one conduction current; Wherein, when the input voltage of the first input signal and the input voltage of the second input signal are within a matching range, both the N-type transistor and the P-type transistor are turned on, and the corresponding conduction current is substantially It is a fixed current value, and the matching range is related to the threshold voltage of the N-type transistor, the threshold voltage of the P-type transistor, and the fixed current value. The memory cell as claimed in item 1, wherein the current control circuit has a control transistor, and the control transistor is a metal oxide semiconductor field effect transistor (MOSFET) or a floating gate (Float gate, FG) A transistor, one of the first ends of the N-type transistor is electrically connected to one of the first ends of the P-type transistor, and one of the second ends of the P-type transistor is electrically connected to one end of the control transistor , the control transistor system has a third gate, the third gate of the control transistor is used to receive a control voltage, and the control voltage is substantially a fixed voltage value. The memory cell as described in claim 2, wherein the second end of the N-type transistor is used to electrically connect with a matching signal line, the second end of the N-type transistor is a drain, and the N-type transistor The first end of the type transistor is the source. The memory cell as claimed in item 1, wherein the memory cell further includes an AND logic gate, the current control circuit has a first sense amplifier and a second sense amplifier, the AND logic gate is coupled to the The first sense amplifier and the second sense amplifier, the first sense amplifier and the second sense amplifier each have a critical current value, the N-type transistor system is electrically connected to the first sense amplifier, The P-type transistor system is electrically connected to the second sense amplifier; Wherein, when one of the at least one conduction current corresponding to the N-type transistor and the other of the at least one conduction current corresponding to the P-type transistor are greater than or equal to the critical current value, the AND logic gate outputs a first a logical value. The memory cell as described in claim 1, wherein the analog content addressable memory system is a flash memory, and the flash memory is a charge storage memory (Charge storage memory), a charge trapping memory (Charge trapping memory), a split gate memory (Split gate memory) or a ferroelectric field-effect transistor (Ferroelectric field-effect transistor, FeFET) memory. The memory cell as claimed in item 1, wherein the analog content addressable memory system is a super steep slope flash memory, and the super steep slope flash memory is a thyristor random access memory (Thyristor Random Access Memory, TRAM), a Gate Control Thyristor (GCT), a Tunnel Field-Effect Transistor (TFET), or a Negative Capacitance Field-Effect Transistor (Negative Capacitance Field- Effect Transistor, NCFET). The memory cell according to claim 1, wherein the N-type transistor and the P-type transistor system are a 2D (two-dimensional) flash memory structure or a 3D (three-dimensional) flash memory structure. An analog content addressable memory device comprising: A word line driving circuit for providing a plurality of first input signals and a plurality of second input signals; A plurality of memory cells, each of which includes: An N-type transistor having a first gate, the first gate of the N-type transistor is used to receive the corresponding first input signal; A P-type transistor has a second gate, and the second gate of the P-type transistor is used to receive the corresponding second input signal; and A current control circuit, coupled to at least one of the N-type transistor and the P-type transistor, for generating a conduction current; a plurality of matching signal lines, each of which is coupled to the corresponding memory cell; a plurality of source lines, each of which is coupled to the corresponding current control circuit; a source line driving circuit coupled to the source lines; and a sense amplifier circuit (Sense Amplifier), coupled to the matching signal lines; Wherein, for a specific memory cell among the memory cells, when the input voltage of the first input signal corresponding to the specific memory cell and the input voltage of the second input signal corresponding to the specific memory cell are both at the specific When the memory cell is within a matching range, both the N-type transistor and the P-type transistor of the specific memory cell are turned on, and the conduction current of the specific memory cell is substantially a fixed current value, and the specific memory cell The matching range is related to the threshold voltage of the N-type transistor of the specific memory cell, the threshold voltage of the P-type transistor of the specific memory cell, and the fixed current value. The analog content addressable memory device as described in claim 8, wherein the current control circuit of each of the memory cells has a control transistor, and the control transistor is a metal oxide semiconductor field effect transistor (MOSFET) or A floating gate (Float gate, FG) transistor, one of the first ends of the N-type transistor is electrically connected to one of the first ends of the P-type transistor, and one of the second ends of the P-type transistor is Electrically connected to one end of the control transistor, the control transistor system has a third gate, the third gate of the control transistor is used to receive a control voltage, the control voltage is substantially a fixed Voltage value. The analog content addressable memory device as described in claim 9, wherein one of the second ends of the N-type transistors of each of the memory cells is used to electrically connect with the corresponding matching signal line, and the N-type transistors The second end is a drain, and the first end of the N-type transistor is a source. The analog content addressable memory device as described in claim 8, wherein the analog content addressable memory device is a flash memory, and the flash memory is a charge storage memory, a charge capture memory, A split gate memory or a ferroelectric field effect transistor memory. The analog content addressable memory device as described in claim 8, wherein the analog content addressable memory device is an ultra-steep flash memory, and the ultra-steep flash memory is a thyristor random access memory , a gate-controlled thyristor, a tunneling field effect transistor, or a negative capacitance field effect transistor. The analog content addressable memory device as claimed in claim 8, wherein the N-type transistor and the P-type transistor are a 2D flash memory structure. An analog content addressable memory device comprising: A first word line driving circuit and a second word line driving circuit, the first word line driving circuit is used to provide a plurality of first input signals, and the second word line driving circuit is used to provide a plurality of first input signals Two input signals; A first N-channel NAND series group, including a plurality of first N-channel NAND series, each first N-channel NAND series is used to receive these first input signals, and each first N-channel NAND series is further used for generating a first current; A first P-channel NAND series group, including a plurality of first P-channel NAND series, each first P-channel NAND series is used to receive the second input signals, and each first P-channel NAND series is further used for generate a second current; A plurality of first sense amplifier circuits and a plurality of second sense amplifier circuits, the first sense amplifier circuits are respectively coupled to the first N-channel NAND series of the first N-channel NAND series group , the second sense amplifier circuits are respectively coupled to the first P-channel NAND strings of the first P-channel NAND string group, the first sense amplifier circuits and the second sense amplifiers the circuits each have a critical current value; and a plurality of first and logic gates, each of the first and logic gates is coupled to the corresponding first sense amplifier circuit and the corresponding second sense amplifier circuit; One of the first and logic gates is a selected first and logic gate, when the first current and the second current corresponding to the selected first and logic gate are greater than or equal to the critical current value, the selected first sum logic gate outputs a first logic value. The analog content addressable memory device as described in claim 14, wherein one end of each of the first N-channel NAND series of the first N-channel NAND series group is used to receive a first bit line signal, the second The other end of each of the first N-channel NAND series of an N-channel NAND series group is coupled to the corresponding first sense amplifier circuit, and each of the first P-channel NAND of the first P-channel NAND series group One end of the series is used to receive a second bit line signal, and the other end of each of the first P-channel NAND series of the first P-channel NAND series group is coupled to the corresponding second sense amplifier circuit, Each of the first N-channel NAND series of the first N-channel NAND series group includes a plurality of first N-type transistors, and each of the first P-channel NAND series of the first P-channel NAND series group includes a plurality of a first P-type transistor, the gates of each of the first N-type transistors in each of the first N-channel NAND strings are used to receive the corresponding first input signal, and each of the first P-channel NAND strings The gates of each of the first P-type transistors are used to receive the corresponding second input signal. The analog content addressable memory device as described in claim 14, wherein the analog content addressable memory device further comprises: A third word line driving circuit and a fourth word line driving circuit, the third word line driving circuit is used to provide a plurality of third input signals, and the fourth word line driving circuit is used to provide a plurality of first Four input signals; A second N-channel NAND series group, including a plurality of second N-channel NAND series, each second N-channel NAND series is used to receive the third input signals, and each second N-channel NAND series is further used for generate a third current; A second P-channel NAND series group, including a plurality of second P-channel NAND series, each second P-channel NAND series is used to receive the fourth input signals, and each second P-channel NAND series is further used for generate a fourth current; a plurality of third sense amplifier circuits and a plurality of fourth sense amplifier circuits, the third sense amplifier circuits are coupled to the second N-channel NAND series of the second N-channel NAND series group, The fourth sense amplifier circuits are coupled to the second P-channel NAND series of the second P-channel NAND series group, the third sense amplifier circuits and the fourth sense amplifier circuits are each have a critical current value; and a plurality of second and logic gates, each of the second and logic gates is coupled to the corresponding third sense amplifier circuit and the corresponding fourth sense amplifier circuit; a plurality of third AND logic gates, each of the third AND logic gates is coupled to the corresponding first AND logic gates and the corresponding second AND logic gates; Wherein, one of the second and logic gates is a selected second and logic gate, when the currents of the third current and the fourth current corresponding to the selected second and logic gate are greater than or equal to the critical current value, the selected second logic gate outputs the first logic value; and One of the third sum logic gates is a selected third sum logic gate, when the first sum logic gate and the second sum logic gate corresponding to the selected third sum logic gate both output the first sum logic gate When a logic value is selected, the selected third logic gate outputs the first logic value. The analog content addressable memory device as described in claim 16, wherein one end of each of the second N-channel NAND series of the second N-channel NAND series group is used to receive a third bit line signal, the first The other end of each of the second N-channel NAND series of the two N-channel NAND series groups is coupled to the corresponding third sense amplifier circuit, and each of the second P-channel NAND of the second P-channel NAND series group One end of the series is used to receive a fourth bit line signal, and the other end of each second P-channel NAND series of the second P-channel NAND series group is coupled to the corresponding fourth sense amplifier circuit, Each of the second N-channel NAND series of the second N-channel NAND series group includes a plurality of second N-type transistors, and each of the second P-channel NAND series of the second P-channel NAND series group includes a plurality of a second P-type transistor, the gates of each of the second N-type transistors in each of the second N-channel NAND strings are used to receive the corresponding third input signal, and each of the second P-channel NAND strings The gates of each of the second P-type transistors are used to receive the corresponding fourth input signal. The analog content addressable memory device as described in claim 14, wherein the analog content addressable memory device is a flash memory, and the flash memory is a charge storage memory, a charge capture memory, A split gate memory or a ferroelectric field effect transistor memory. The analog content addressable memory device as described in claim 14, wherein the first N-channel NAND series group and the first P-channel NAND series group are a 2D flash memory structure or a 3D flash memory structure. The analog content addressable memory device as described in claim 14, wherein the analog content addressable memory device is an ultra-steep flash memory, and the ultra-steep flash memory is a thyristor random access memory , a gate-controlled thyristor, a tunneling field effect transistor, or a negative capacitance field effect transistor.

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