KR101844074B1 - Architecture for a 3d memory array - Google Patents

Abstract

A technique for compensating for threshold voltage variations between memory cells in an array by applying different bias conditions to selected bit lines is described herein. Techniques for connecting global bit lines to various levels of memory cells in a three-dimensional array are also described herein, which can provide a minimization of capacitance differences between global bit lines.

Description

ARCHITECTURE FOR A 3D MEMORY ARRAY

The present invention relates to a high-density memory device in which changes in cell characteristics within an array can be changed, such as a memory device in which multi-level memory cells are arranged to provide a three-dimensional array.

The critical dimension (CD) of an element in an integrated circuit is being reduced to the limit of common cell technology, arrays are becoming larger and memory cells in the array may have characteristics that change in a way that affects marginal sensing. In a trend toward higher density implementations, designers are looking at techniques for stacking multi-level memory cells to increase storage capacity and lower the cost per bit. For example, Lai et al., "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory", IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006, and Jung et al., "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node", IEEE Int'l Electron Devices Meeting, 11-13 Dec. In 2006, thin film transistor technology is applied to charge trapping memory technology.

Johnson et al., "512-Mb PROM with a Three-Dimensional Array of Diodes / Anti-fuse Memory Cells ", IEEE J. Solid-State Circuits, vol. 38, no. 11, Nov. In 2003, a cross-point array technology was applied for anti-fuse memory. In Johnson's design, multi-level word lines and bit lines are provided and memory elements are located at the intersection points. The memory elements include a p + type polysilicon anode connected to the word line and an n type polysilicon cathode connected to the bit line, wherein the anode and the cathode are separated by the anti-fuse material.

In a three-dimensional array, differences in the electrical characteristics of the structure at various levels can lead to differences in the dynamics of programming, erasing, and charge storage, including threshold voltage changes corresponding to memory states of memory cells at various levels. Thus, in order to achieve the same threshold voltage within an acceptable margin for all levels, the programming and erasing processes must be configured to vary with the level of the target cell in some way. Such a change may cause durability problems of the memory cell and other complexity.

In a three-dimensional array, an access line, such as a global bit line, arranged for use in accessing various levels of the array may be arranged in an array of cells in which a property, such as capacitance and inductance, Which level, which position, and so on. For example, global bit lines are typically extended to decoder circuits used to read and write memory cells. Differences between vertical connections for various levels and other differences between levels can cause capacitance variations between global bit lines. This capacitance change affects the global bit line voltage during the read, program, and erase operations, and can be used to reduce the read margin, such as the large read margin between the programmed and erased states, and the slower sense time to compensate for the worst case capacitance. It can cause protocol requirements.

Accordingly, it would be desirable to provide a three-dimensional integrated circuit memory that provides a technique to compensate for changes in cell characteristics within the array and reduces the complexity resulting from differences between levels.

A technique for compensating for threshold voltage variations between memory cells in an array by applying different bias conditions to selected bit lines is described herein.

The compensation technique can be developed in a memory structure that includes a three-dimensional array and a memory structure that does not include a three-dimensional array, and provides management of dynamic cell characteristics to derive a threshold voltage change.

In a three-dimensional array, a level-dependent read operation is described that compensates for threshold voltage variations between levels by applying different read bias conditions to each in-level bit line, in particular, the local bit line in the array.

Techniques for connecting access lines, including global bit lines, to various levels of memory cells within a three-dimensional array are also described herein, which can provide a minimization of capacitance differences between global bit lines.

1 is a schematic block diagram of an integrated circuit including a NAND flash memory array that can operate as described herein.
2 is a partial schematic diagram of a three-dimensional NAND flash memory array.
3 is a partial perspective view of an example of a three-dimensional NAND flash memory array.
Fig. 4 shows an example in which the thickness of the semiconductor material strip forming the memory cell channel region at the lower level is greater than the thickness at the upper level.
Figure 5 illustrates an exemplary distribution of threshold voltages for a number of programmed memory cells at four different levels.
6 is a sequence of operational sequences for performing a level-dependent read operation as described herein.
Figure 7 is a schematic diagram of a circuit suitable for use in performing a level-dependent read operation on a selected memory cell.
Figure 8 is an exemplary timing diagram for operating the circuit shown in Figure 7 to perform a level-dependent read operation.
Figure 9 shows an exemplary layout of connections of global bit lines for a plurality of blocks having a plurality of levels of memory cells.
Figs. 10, 11, 12 and 13 show cross-sectional views of the vertical connector of the structure shown in Fig.
14 is a simplified block diagram of an integrated circuit including a three-dimensional memory array having global bit lines each coupled to a plurality of levels of memory cells.
15 is a schematic diagram showing a manner in which global bit lines are connected to a page buffer in one decoding structure.
16 is a perspective view of a three-dimensional NAND flash memory array structure having global bit lines each connected to a plurality of levels of memory cells.
17 shows an exemplary layout screen of connections of global bit lines for a plurality of multilevel blocks having memory cells arranged in the structure shown in FIG.

A technique for compensating for threshold voltage variations between memory cells in an array by applying different bias conditions to selected bit lines is described herein.

The compensation technique can be deployed in a memory structure including a three-dimensional array and also in a memory structure that does not include a three-dimensional array, thereby providing management of dynamic cell characteristics causing a threshold voltage change.

The integrated circuit elements described herein include a memory array and a bias circuit. The bias circuit compensates for a change in the threshold voltage that is correlated with the location of the selected memory cell in the physical structure of the memory array by applying different bias conditions to the bit line for the selected memory cell during the read operation or during other operations on the cell , The threshold voltage corresponds to the memory state of the memory cell in the array. The change in threshold voltage correlated with the location of a selected memory cell in the physical array of memory arrays, such as a change in level or plane of a memory cell in a three-dimensional array, may result in a plurality of threshold levels Which is induced to build the threshold voltage.

Different bias conditions may be applied simultaneously to a plurality of bit lines, such as during page access, and cells in a page may be placed at different locations within the array. Bias conditions are applied "simultaneously" for the purposes of this description if they are allowed to overlap in time during a read access that provides data from a plurality of memory cells in accordance with a single read command, such as during a page read.

In a three-dimensional array, a level-dependent read operation is described that compensates for threshold voltage variations between levels by applying different read bias conditions to the local bit lines at each level of the array. The level-dependent read operation may be deployed in combination with a change in WL voltage in an array structure that allows or allows the application of different word line WL voltages.

The integrated circuit described herein includes a memory array including a plurality of levels of memory cells. The levels of the plurality of levels include a local bit line and a memory cell coupled to the local bit line. The global bit lines are connected to the corresponding set of local bit lines in the array. The integrated circuit includes a decoding circuit for selecting a memory cell in the memory array. The integrated circuit further includes a bias circuit coupled to the global bit line to provide the selected bias voltage. The bias circuit selects a bias voltage for the global bit line corresponding to the selected memory cell in accordance with the control signal.

A technique for connecting global bit lines to various levels of memory cells in a three-dimensional array that may be provided to minimize capacitance differences between global bit lines is also described herein. In one form, the connectors for the various levels are arranged on the global bit lines such that the statistical functions (e.g. sum, average, etc.) of the level indexes of the levels connected to each of the global bit lines are constant.

The integrated circuit described herein includes a plurality of blocks. The plurality of blocks within the block includes a plurality of levels L (z). The plurality of levels of level L (z) are connected to the corresponding memory cells in the array by a plurality of word lines along a row and a two-dimensional array of memory cells with a plurality of local bit lines along the column, . The integrated circuit further includes a plurality of global bit lines. The global bit lines in the plurality of global bit lines include a plurality of connectors. Connectors in a plurality of connectors connected to a given global bit line are connected to corresponding local bit lines in a plurality of blocks. In the embodiment described herein, on a given global bit line, a corresponding local bit line in one of the plurality of blocks lies on a level L (z) different from the corresponding one of the plurality of blocks in the local bit line. By connecting the global bit lines to different levels within different blocks along the same global bit line, the capacitance of the global bit lines can be adjusted. In addition, by applying this design scheme to a set of global bit lines sharing a plurality of blocks of memory cells, the capacitance of each member of the set of global bit lines can approach the same value. The bias circuit may be coupled to a plurality of global bit lines that compensate for a change in the threshold voltage corresponding to the memory state of the selected memory cell based on the level L (z) of the selected memory cell.

A detailed description of an embodiment of the present invention is provided with reference to Figs. 1-17.

Figure 1 is a simplified block diagram of an integrated circuit 175 that includes a NAND flash memory array 160 that can operate as described herein. In some embodiments, the array 160 may include multi-level cells. The row decoder 161 is connected to a plurality of word lines 162 arranged along rows in a memory array. The column decoder of block 166 is connected to the set of page buffers 163 via the data bus 167 in this example. The global bit lines 164 are connected to local bit lines (not shown) arranged along the columns in the memory array 160. An address is supplied to the column decoder (block 166) and row decoder (block 161) on bus 165. (E.g., including input / output ports), such as a general purpose processor or a dedicated application circuit, or a combination of modules that provide system-on-chip functionality supported by the array 160 - in line 173. Data is supplied to the input / output port via line 173, or to another data destination, either inside or outside the integrated circuit 175.

The controller implemented in this example as the state machine 169 provides a signal for controlling the application of bias array supply voltage generated or provided through the voltage source of block 168 to perform the various operations described herein. This operation includes erase, program, and level-dependent read, which have different read bias conditions for each level of array 160. The controller may be implemented using dedicated logic circuitry as is well known in the art. In an alternate embodiment, the controller includes a general purpose processor, which is implemented on the same integrated circuit to execute a computer program to control the operation of the device. In another embodiment, a controller is implemented using a combination of dedicated logic circuitry and a general purpose processor.

For the sake of clarity, the term "program " herein refers to the operation of increasing the threshold voltage of a memory cell. Data stored in the programmed memory cell may be represented by "0" or "1 ". Herein, the term "erase " refers to a task of reducing the threshold voltage of a memory cell. Data stored in the erase memory cell can be represented by "1" or "0 ", in contrast to the programmed state. In addition, the mild bit cell can be programmed to various threshold levels and can be erased to a single lowest threshold level or a highest threshold level. Furthermore, the term "write " as used herein refers to the operation of changing the threshold voltage of a memory cell, and has the intention to cover both programming and erasing.

2 is a schematic diagram of a portion of a three-dimensional NAND flash memory array that may be used in an apparatus similar to that of FIG. In this example, three levels of memory cells are shown, which represent blocks of memory cells that may contain multiple levels.

Word line WL _{n -1,} a plurality of word lines WL including a _{n, n +1} WL extend in parallel along a first direction. The word line is electrically connected to the row decoder 261. The word lines are connected to the gates of the memory cells, and the gates are arranged in series in a NAND string. The word line WL _n represents a word line. As it is shown in Figure 2, the word line WL _n are vertically connected to the gates of the various levels of each of the memory cells underlying the word line WL _n.

A plurality of local bit lines are arranged along the columns to form NAND strings at various levels of the memory array. As shown in FIG. 2, the array includes a local bit line BL ₃₁ on a third level, a local bit line BL _{21 on} a second level, and a local bit line BL ₁₁ on a first level.

The memory cell has a dielectric charge trapping structure between the corresponding word line and the corresponding local bit line. In the illustration, there are three memory cells in the NAND string for simplicity. For example, one NAND string formed by a local bit line BL ₃₁ on a third level includes memory cells 220, 222, and 224. In a typical implementation, a NAND string may include 16, 32, or more memory cells.

A plurality of string select lines, including string select lines SSL _{n -1} , SSL _n , and SSL _{n +1} , are electrically coupled to the group decoder 258 (which may be part of the row decoder 261). The string selection line is connected to the gate of the string selection transistor arranged at the first end of the memory cell NAND string. As shown in FIG. 2, each string select line is connected vertically to the gate of the column of the string select transistor at each of the various levels. For example, the string selection line SSL _{n +1} is connected to the gates of the three levels of string selection transistors 210, 212 and 214.

Local bit lines on a particular level are selectively connected to extensions on a particular level by corresponding string select transistors. For example, the local bit line on the third level is selectively connected to the extension 240 by the corresponding string selection transistor of that level. Likewise, the local bit line on the second level is selectively connected to the extension 242, and the local bit line on the first level is selectively connected to the extension 244.

The extension on each level includes a corresponding contact pad for contacting a vertical connector connected to a corresponding global bit line. For example, third level extensions 240 are connected to global bit line GBL _{n -1} through contact pad 230 and vertical connector 200. The extension 242 on the second level is connected to the global bit line GBL _n through the global pad 232 and the vertical connector 202. The extension 244 on the first level is connected to the global bit line GBL _{n +1} .

The global bit lines GBL _{n -1} , GBL _n , and GBL _{n +1} are connected to additional blocks (not shown) in the array and extend to the page buffer 263. In this way, a three-dimensional decoding network is established and accessed by using one word line, all or part of the bit line, and one string selection line to the page of the selected memory cell.

A block select transistor is arranged at the second end of the NAND string. For example, the block select transistor 260 is arranged at the second end of the NAND string formed by the memory cells 220, 222, and 224. The ground select line GSL is connected to the gate of the block select transistor. The ground select line GSL is electrically coupled to the row decoder 261 to receive the bias voltage during operation described herein.

The block select transistor is used to selectively connect the second end of all the NAND strings in the block to the reference voltage provided on the common source line CSL. The common source line CLS receives the bias voltage from a bias circuit (not shown) during the operation described herein. In some operations described herein, the CSL is biased to a reference voltage that is higher than the voltage of the bit line that is connected to the opposite end of the NAND string, rather than to the conventional "source" role at or near ground.

3 is an example partial perspective view of a three-dimensional NAND flash memory array capable of applying a level-dependent bias during a read operation to compensate for a change in the threshold voltage correlated with the level of the selected cell. In Fig. 3, the filling material is removed to show the appearance of the word lines and bit lines constituting the three-dimensional array.

The memory array is formed on the insulating layer 310 above the semiconductor or other structure (not shown) below. The memory array is arranged for connection to a row decoder and includes a plurality of conduction lines 325-1 and 325-2, acting as word lines WL ₁ and WL ₂ . A silicide layer may be formed on the upper surfaces of the conductive lines 325-1 and 325-2.

Conduction lines 325-1 and 325-2 are coplanar with semiconductor material strips that act as local bit lines at various levels. For example, semiconductor material strip 312 acts as a third level local bit line, semiconductor material strip 313 acts as a second level local bit line, and semiconductor material strip 314 acts as a first level Lt; / RTI > The semiconductor material strips are separated by an insulating layer (not shown).

The semiconductor material strip may be a p-type semiconductor material. Conduction lines 325-1 and 325-2 may be semiconductor materials having the same or different conductivity types, or may be other conductive word line materials. For example, semiconductor material strips may be fabricated using p-type polysilicon or p-type single crystal silicon, and conduction lines 325-1 and 325-2 may be fabricated using relatively heavily doped p + -type polysilicon .

Alternatively, the semiconductor material strip may be an n-type semiconductor material. Conduction lines 325-1 and 325-2 may be semiconductor materials having the same or different conductivity types. This n-type strip array results in a buried channel, depletion mode charge trapping memory cell. For example, semiconductor material strips may be fabricated using n-type polysilicon or n-type single crystal silicon, and conduction lines 325-1 and 325-2 may be fabricated using heavily doped p + -type polysilicon have. A typical doping concentration of the n-type semiconductor material strip may be about 10 ¹⁸ / cm ³ , and the range of available embodiments is between about 10 ¹⁷ / cm ³ and 10 ¹⁹ / cm ³ . The use of n-type semiconductor material strips may be particularly useful for non-junction embodiments to improve conductivity along the NAND string, thus enabling high read currents.

The memory cells have a charge storage structure between the semiconductor material strip and conduction lines 325-1 and 325-2, acting as local bit lines. For example, a memory cell 380 is formed between the semiconductor material strip 312 and the conductive line 325-1, which acts as a third level local bit line. In this illustration, there are two memory cells in one NAND string for simplicity. Each memory cell in the embodiment described herein is a double gate field effect transistor having an active charge storage region on both sides of the interface between the conduction lines 325-1 and 325-2 and the corresponding semiconductor material strip.

In this example, the charge storage structure comprises a tunneling layer, a charge trapping layer, and a blocking layer. In one embodiment, the tunneling layer is silicon oxide (O), the charge storage layer is silicon nitride (N), and the blocking dielectric layer is silicon oxide (O). As an alternative, the memory cell may be made of a silicon-rich nitride (Si _x O _y N _z ), a silicon-rich nitride, a silicon-rich oxide, a trapping layer filled with nano- Charge storage structure.

In one embodiment, a bandgap engineered SONOS (BE-SONOS) charge storage structure comprising a dielectric tunneling layer comprising a combination of materials forming a "U" -type valence band reversed under zero bias is utilized . In one embodiment, the composite tunneling dielectric layer includes a first layer, referred to as a hole tunneling layer, a second layer, referred to as a band offset layer, and a third layer, referred to as an isolated layer. The hole tunneling layer in this embodiment includes, for example, silicon dioxide formed on the side surfaces of the semiconductor material strip using co-location steam generating ISSG, and may be deposited by NO addition to the periphery during deposition, or by post deposition NO annealing A selective nitridation process may be performed. The thickness of the first layer of silicon dioxide is less than 20 angstroms, preferably less than 15 angstroms. The thickness of the representative embodiment may be 10 angstroms or 12 angstroms.

The string selection line SSL _n , SSL _{n +1} is connected to the gate of the string selection transistor at the first end of the memory cell NAND string. A string selection transistor is formed between the multi-level string selection gate structure and the semiconductor material strip of the corresponding NAND string. For example, a string selection transistor 350 is formed between the semiconductor material strip 312 and the string selection gate structure 329. The string selection gate structure 329 is connected to the string selection line SSLn via a contact plug 365.

The semiconductor material strip is selectively connected to another level of semiconductor material strip by an extension. For example, the third level semiconductor material strips are selectively connected to each other via extensions 340. Likewise, the second level semiconductor material strips are selectively connected to one another via extensions 342, and the first level semiconductor material strips are selectively connected to one another via extensions 344. [

The third level of extension 340 is connected to global bit line GBL _{n -1} through contact pad 330 and vertical connector 300. The second level of extension 342 is connected to global bit line GBL _n via contact pad 332 and vertical connector 302. The first level of extension 344 is connected to the global bit line GBL _{n +1} .

The global bit lines GBL _{n -1} , GBL _n , and GBL _{n +1} are connected to additional blocks (not shown) in the array and extend to the page buffer 263.

The block select transistors are arranged at the second end of the NAND string. For example, the block select transistor 351 is arranged at the second end of the NAND string formed by the semiconductor material strip 312. The gate structure 349 acting as the ground select line GSL is connected to the gate of the block select transistor.

The block select transistor is arranged at the second end of the NAND string. For example, the block select transistor 351 is arranged at the second end of the NAND string formed by the semiconductor material strip 312. The gate structure 349 acting as the ground select line GSL is connected to the gate of the block select transistor.

The block select transistor is used to selectively connect the second ends of all the NAND strings in the block to the reference voltage provided on the common source line CSL 370. [ The CSL 370 extends parallel to the word lines.

The structure shown in FIG. 3 can be fabricated using, for example, the techniques described in U.S. Patent Application No. 13 / 018,110, filed January 31, 2011, the contents of which are incorporated herein by reference.

In operation, each memory cell stores a data value according to a threshold voltage. The reading or writing of the selected memory cell may be implemented by applying an appropriate voltage to the word line, bit line, string select line, ground select line, and common source line.

During programming, an appropriate voltage may be applied to induce electron tunneling into the charge storage layer of the selected memory cell. The programming operation increases the threshold voltage of the selected memory cell. The selected memory cell may be programmed using Fowler-Nordheim (FN) electron tunneling.

During the erase operation, an appropriate voltage may be applied to induce hole tunneling into the charge storage layer of the selected memory cell, or to induce electron tunneling from the charge storage layer. The erase operation reduces the threshold voltage of the selected memory cell.

At the time of the reading operation, a current flowing in the selected memory cell can be sensed by applying a proper reading voltage. The data value may be determined based on the current flowing in the selected memory cell during the read operation. The read voltage may be selected so that the erased memory cell is turned on (i.e., conducts current) during the read operation and the programmed memory cell remains off (i.e., little or no current flows) .

In a three-dimensional array, the difference between the levels causes a difference in charge storage kinetics and causes a change in the threshold voltage corresponding to the memory state of the memory cell at various levels. 4 shows an example in which the thickness of the semiconductor material strip forming the channel region of the lower level memory cell is larger than the thickness of the upper level. The difference in channel thickness can be caused by the etching process used to form the device.

If the same programming and erase operations are used for each level of memory cell, this difference in channel thickness and the different difference between the levels can result in a broad distribution of threshold voltages of the memory cells at various levels. Figure 5 shows an example distribution of threshold voltages for a number of programmed memory cells at four different levels. In the example shown in FIG. 5, a programmed memory cell at level 4 has a threshold voltage in distribution 500 that is generally higher than the distribution 510 of programmed memory cells at level 1.

Thus, the programming and erasing process can be adapted to vary with the level of the selected memory cell in a predetermined manner, to implement the same threshold voltage for a particular memory state for all levels of the memory cell. This adaptation can cause problems of durability of the memory cell and other complications.

Additionally, when the same read operation is used for each level, a threshold voltage change between memory cells at various levels reduces the read margin between the programmed state and the erased state. If the reading margin is narrow, a complicated circuit is required, and the diary process may be slowed down.

One technique for achieving a wide read margin is to apply the lower word line voltage to read and verify the lower level memory cell and to apply the upper word line voltage to read and verify the upper level memory cell. This technique is shown in Figure 5 as four different lines for the read voltage V _READ and four different lines for the program verify voltage V _PV . However, since the word lines are connected to the memory cells at the respective levels in the array structure shown in FIGS. 2 and 3, when different word line voltages are applied based on the level of the selected memory cell, Simultaneous reading of the cell is excluded.

The level-dependent read operations described herein compensate for threshold voltage changes by applying different read bias conditions to the bit lines for access to cells within each level of the array 160, Lt; / RTI > is maintained in a dense distribution even as the threshold voltage for the memory cells on the different levels of the current on the bit line to the bit line for the bit line changes. In doing so, the technique described herein can maintain a relatively wide read margin between the programmed state and the erased state for each level, and does not require a different read word line voltage.

6 is a sequence of a task sequence 600 for performing a level-dependent read operation as described herein.

In step 610, a read command for a particular address is received.

In step 620, the address is decoded by the decoder circuit to identify the physical location (such as the level of the three-dimensional embodiment) of the selected memory cell associated with the address. The decoder circuit generates, according to the address, a control signal indicating the position of the selected memory cell.

In step 630, the bias circuit pre-charges the bit line of the selected memory cell to a voltage level that depends on the position or level of the selected memory cell, in accordance with the control signal.

At step 640, a read operation is performed on the selected memory cell to determine the stored data value. In step 650, data is output from the page buffer.

FIG. 7 is a schematic diagram of a circuit suitable for use in performing a level-dependent read operation on a selected memory cell 700. FIG. In this example, reading is level-dependent. In another example, the read operation may depend on the location of the selected memory cell in another sector or segment of the three-dimensional or two-dimensional array, and the cells in that sector or segment have read characteristics within a certain range.

The selected memory cell 700 is part of the NAND string formed by the local bit line BL 710 within a certain level of the array. The NAND string also includes a memory cell 702 and a memory cell 704. The string selection transistor 712 selectively connects the bit line 710 to the global bit line 720 through the contact pad 714 and the vertical connector 716. The gate of the string selection transistor 712 is connected to the string selection line SSL 718.

Block select transistor 706 selectively connects the second end of the NAND string to common source line CSL 708.

The global bit line 720 is connected to the sense circuit 730 by a column decoder circuit (not shown) via the page buffer circuit for the global bit line 720. The signals BLCLAMP, VBOOST, BLPWR, BLPRECHG, and PBEN are controlled by the control logic (not shown) used to control the performance and timing of the diary occupation, including the precharge period and sense period, as described below with reference to the timing diagram of FIG. Lt; / RTI > shown schematically by boxes 750-754) and a voltage source. Cell position decoder 760 is used to provide cell position information for use in generating VBOOST and BLCLAMP signals, as described below, based on the location of selected cells or other sectors or segments of a particular level of the array do. In some embodiments, the cell position decoder 760 is the same circuit used for plane decoding for a three-dimensional array (see FIG. 15).

The clamp transistor M1 is connected between the global bit line 720 and the data line DLIB. Signal BLCLAMP is connected to the gate of clamp transistor M1.

The precharge transistor M2 has a first terminal connected to the data line DLIB, a second terminal connected to the bit line power BLPWR signal, and a gate connected to the signal BLPRECHG. A controllable voltage source 752 applies the BLPWR signal at a voltage level and timing dependent on the control sequence under execution. The control circuit 753 applies the BLPRECHG signal at a voltage level and timing that depends on the control sequence being executed.

The signal VBOOST is also connected to the data line DLIB via the capacitor C1. The controllable voltage source 751 applies the VBOOST signal at a voltage level and timing that depends on the control sequence being executed.

The enable transistor M3 is arranged between the data line BLIB and the latch-based sense amplifier circuit 740. The control signal PBEN is connected to the gate of the enable transistor M3. The control logic 754 applies the PBEN signal at a voltage level and timing dependent on the control sequence being executed.

8 is an exemplary timing diagram for operating the circuit shown in FIG. 7 to perform a level-dependent read operation on the selected memory cell 700. FIG. The control circuitry on the integrated circuit is arranged to cause a sequence in the read operation by controlling bias circuits, word lines, and other circuits in the memory array, as shown in Fig.

When a read operation is started, control signals BLCLAMP, VBOOST, BLPWR, BLPRECHG, and PBEN are applied to control the timing of a read operation.

During the time interval T0, the word lines WL0 and WL2 connected to the gates of the unselected memory cells 704 and 702 are charged with a voltage value VPASSR sufficient to turn on unselected memory cells 704 and 702. The word line WL1 connected to the gate of the selected memory cell 700 is charged with the voltage value VREAD. VREAD is sufficient to turn on the selected memory cell 700 in the erased state and insufficient to turn on the selected memory cell 700 in the case of the programmed state (in the case of a 1-bit cell). In the embodiment shown, the voltage value VREAD is substantially the same for each level of the memory cell. The string select line 718 is charged to a high value to turn on the string select transistor 712. The ground select line GSL is set to a low value to turn off the block select transistor 706. [

The selected local bit line 710 is discharged to ground through M1 and M2 by setting the controllable voltage BLCLAMP and the timing signal BLPRECHG to a high level and setting the controllable voltage BLPWR to ground. The common source line CSL is charged to a high level to charge a non-selected local bit line (not shown). The unselected bit lines are precharged to the level of the common source line CSL via their respective bias circuits.

During the time interval T1, the BLPWR signal is changed to an intermediate voltage value, such as 2.3 volts, to charge the data line DLIB via M2. The BLCLAMP signal is biased to the voltage value VBLCLAMP1 based on the level of the selected memory cell 700. [ Each of these array levels (corresponding to memory cells selected in such a structure) for use to provide different decision criteria that depend on the selected memory cell, as indicated by the four lines in the timing diagram for the value of BVLCLAMP1 A different bias level is used. In other words, the bit lines at different levels of the array are precharged to different voltage levels. In this way, different precharge bit line levels can compensate for threshold voltage differences between cells at these levels. The precharged bit line voltage level BL is given by the difference between the threshold voltage of transistor M1 and VBLCLAMP1 during the interval T1.

During the time interval T2, the BLCLAMP and BLPRECHG signals are set to a low level to turn off M1 and M2 to float the selected bit line 710 and the data line DLIB. The ground select line GSL is charged to a high value to turn on the block select transistor 706 and thus connects the second end of the NAND string to the common source line CSL 708 (held at a high level). The selected bit line 710 will be charged based on the cell current flowing through the selected memory cell 700 as indicated by the four lines on the timing diagram for BL and the high threshold current HVT memory state Diverging lines for low-threshold voltage LVT memory states (increased because the current flows from CSL to DLIB). During a portion of the time interval T2, the voltage level at the data line DLIB may be boosted to a higher voltage by applying a different voltage level VBOOST1 to the VBOOST signal based on the level of the selected memory cell 700. [ This can provide a greater voltage swing on the data line DLIB during the time interval T3, as indicated by the four lines on the timing diagram for VBOOST and DLIB.

During a portion of the time interval T3, the control signal BLCLAMP is biased to the voltage value VBLCLAMP2. VBLCLAMP2 is also based on the level of the selected memory cell 700, as indicated by the four lines on the timing diagram for VBLCLAMP2. The voltage value of VBLCLAMP2 may be greater than the voltage value of the voltage value VBLCLAMP1 applied during the time interval T1. For example, VBLCLAMP2 may be 0.2 volts greater than VBLCLAMP1 for a given selected memory cell.

After the time interval T2, if the selected bit line 710 is charged to a voltage less than the threshold voltage of the subtracting M1 of VBLCLAMP2, M1 is turned on when VBLCLAMP2 is applied. This connects the selected bit line 710 to the data line DLIB and equalizes the voltage level therebetween, as can be seen in the area 800 on the DLIB trace of FIG. Instead, after time interval T2, if the selected bit line 710 is charged to a voltage greater than the threshold voltage of subtracting M1 of VBLCLAMP2, M1 is turned off. This holds the voltage level of the data line DLIB.

After setting the voltage level on the data line DLIB, the signal VBOOST is set to a low value to provide an appropriate DLIB level for the latches set in the sense amplifier. The sense amplifier can sense the data based on the voltage of the DLIB at the end of the interval T3 or just before the end of the interval T3.

At time T4, all signals are restored to their initial state.

Thus, the memory elements comprised in the described integrated circuit include a plurality of bit lines connected to corresponding data lines in a set of data lines via respective clamp transistors, the data lines being connected to corresponding sense circuits, A bias voltage source for applying a bias voltage to the control terminal of the clamp transistor which is dependent on the selected memory cell, and a bias voltage source for applying a bias voltage to the control terminal of the clamp transistor responsive to the timing signal during a read operation of the selected memory cell in the memory array, .

The memory array of the present example includes a NAND array, which includes a plurality of NAND strings each having a ground selection transistor and a string selection transistor, a ground selection line and a string selection line, and a word line, Wherein the bias circuit causes a sequence that can be simultaneously applied to a NAND string for a selected page of a memory cell for a read operation of a selected cell on a selected NAND string,

Charging the word line connected to the NAND string selected for the read operation to the target level at the first time interval T0 and applying a low reference voltage through the precharge circuit when the ground selection transistor is off and the string selection transistor is on Discharging the bit line,

- precharging the data line to the read reference voltage and applying the first clamp voltage to the clamp transistor depending on the selected memory cell, so that the data and bit lines for the selected NAND string are selected Precharged to a level depending on the memory cell,

Turning off the clamp transistor and disconnecting the precharge circuit from the data line, turning the ground selection transistor on when applying a read bias voltage to the source line,

In the fourth time interval T3, a second clamp voltage higher than the first clamp voltage is applied to the clamp transistor depending on the selected memory cell, and the level of the data line is detected to display the value of the data stored in the selected memory cell .

In the embodiment described herein, the bias circuit includes a boost circuit coupled to the data line, the boost circuit capacitively boosting the voltage on the data line by a boost amount, in accordance with a timing signal during a read operation. The boost voltage source is coupled to a boost circuit to set a boost amount that is dependent on the selected memory cell and the sequence is configured to boost the data line within or after the fourth time interval to boost the data line before sensing the level of the data line. Voltage application.

The read operation described herein can be applied to a memory structure including a three-dimensional array, a memory structure that does not include a three-dimensional array, and can provide management of dynamic cell characteristics, , In combination with a change in the WL voltage in an array structure that allows this, results in a threshold voltage change.

As described above, in a three-dimensional memory array, global bit lines are connected to local bit lines within the various levels of the memory array via vertical connectors and contact pads.

Differences between the vertical connectors and the contact pads to various levels and other differences between the levels can cause a total capacitance difference between the global bit lines. 3, the contact pad 330 and the level 3 vertical connector 300 have different capacitances than the capacitances of the contact pad 332 and the level 2 vertical connector 302. For example, referring to FIG. This difference leads to a total capacitance change of the global bit line, which again can reduce the read margin both in terms of voltage-to-current magnitude and speed, and can affect other characteristics of the array during operation.

9 shows an exemplary layout view of the connection of global bit lines GBL ₁ to GBL ₈ to a plurality of blocks having multi-level memory cells. Figures 10, 11, 12 and 13 are cross-sectional views of the vertical connector for each block.

Each block includes a plurality of levels each including a two-dimensional array of memory cells. Each two-dimensional array of memory cells includes a plurality of local bit lines and a plurality of word lines coupled to corresponding memory cells in the array. The two-dimensional array can be implemented in a NAND structure, for example, as described above. Alternatively, other array structures may be used.

The block size and number of blocks will vary from embodiment to example. In some embodiments, the size of each block may be, for example, 2KB (kilobytes), 4KB, 8KB, or 16KB, and so on.

Global bit lines GBL ₁ to GBL ₈ are connected to local bit lines (not shown) in the various levels of the block via vertical connectors. In this figure, each block includes four levels for simplicity. The level at which the vertical connector connects the global bit line is indicated by the level index 1, 2, 3, or 4. For example, the global bit line GBL ₁ is connected to the local bit line in the first level memory block N-1 via a level 1 connector and connected to the local bit line in the second level memory block N via a level 2 connector And is connected to the local bit line in the third level memory block N + 1 through the level 3 connector and to the local bit line in the fourth level memory block N + 2 through the level 4 connector.

The vertical connector for each block in this example is a "step connector structure for a local bit line ", which can be implemented by arranging the contact pads at each level in a stair step manner similar to that shown in Fig. (stepped connector structure for local bit lines).

Global bit line GBL ₁ To GBL ₈ at various levels between the arrays, the difference between the capacitances of the global bit lines GBL ₁ to GBL ₈ can be small.

In the embodiment shown, the connector is arranged such that the sum of the level indices of the corresponding local bit lines for each of the global bit lines GBL ₁ to GBL ₈ is constant. Alternatively, the connector may be arranged such that other statistical functions, such as an average of the level indices, may be constant in constant. In general, the connector may be arranged to select a capacitance change between global bit lines in accordance with a particular implementation.

In this way, the capacitance difference between the global bit lines GBL ₁ to GBL ₈ can be small or can be controlled within a selected limit. This, of course, provides a broad read margin between the programmed state and the erased state.

14 is a simplified block diagram of an integrated circuit 1475 that includes a three-dimensional memory array 1460 having global bit lines that are each coupled to a plurality of levels of memory cells. A row decoder 1466 is coupled to the plurality of word lines 1462 arranged along the row of the memory array 1460. The column decoder 1466 is connected to the page buffer 1463 via the data bus 1467 in this example. A plane decoder 1464 is coupled to the page buffer 1463. Global bit lines 1464 are connected to local bit lines (not shown) arranged along columns within the various levels of memory array 1460. The address is supplied to the column decoder 1466, row decoder 1461, and plane decoder 1464 on bus 1465. Data is supplied from an input / output port, or from another data source inside or outside the integrated circuit, via line 1473. In the illustrated embodiment, other circuitry 1474 is included on an integrated circuit, such as a general purpose processor, or a combination of dedicated application circuitry or modules that provide system-on-chip functionality supported by array 1460 do. Data is supplied to the input / output port via line 1473, or to other data destinations within or outside the integrated circuit.

The controller implemented in state machine 1469 in this example performs various tasks described herein, including erase, program, level-dependent reading with different read bias conditions for each level of array 1460 To provide a control signal to control the application of the bias array supply voltage provided or generated at block 1468 via a voltage source. In combination, controller 1469 and block 1468 may include bias circuitry and logic represented by blocks 750-754 in FIG. The controller may be implemented using dedicated logic circuits well known in the art. In an alternative embodiment, the controller includes a dedicated processor, which may be embodied on the same integrated circuit, that executes the computer program to control the operation of the element. In another embodiment, a combination of dedicated logic circuitry and a dedicated processor may be used in the implementation of the controller.

FIG. 15 is a schematic diagram showing how global bit lines GBL ₁ to GBL ₈ are connected to page buffers 1511 to 1518, and the combination of these page buffers corresponds to page buffer 1463 of FIG. The page buffers 1511-1518 may include circuitry, for example, similar to the case of FIG. In an embodiment that includes a biasing circuit to compensate for bit line biasing for a cell location, the page buffer includes a clamp transistor, a boost capacitor, a latch, and a charging circuit for bit line power.

A planar decoder, such as the planar decoder 1464 of Figure 14, includes a switch circuit coupled to a plurality of global bit lines to apply a bias voltage to a selected global bit line that depends on the level L (z) of the selected memory cell . The switch circuit of this example includes voltage switches 1500, 1502, 1504, and 1506. In this example, upon initiating a read operation for one address, the plane decoder 1464 may decode the address to identify the physical location, including the block and level, of the selected memory cell associated with the address. The switch circuit may be configured to simultaneously apply a bias voltage through a voltage switch to a selected global bit line to access a page of the memory cell.

Voltage switches 1500, 1502, 1504 and 1506 receive different voltage signals Vsource1, Vsource2, Vsource3, and Vsource4, which are generated or provided via a voltage source (block 1468) The voltage switches 1500, 1502, 1504 and 1506 output one of the control voltages Vsource1, Vsource2, Vsource3 and Vsource4 as the level-dependent control signal BLCLAMP, as described above. The level-dependent control signal BLCLAMP is the global bit line GBL ₁ Clamp transistors in the page buffer circuit coupled to the GBL to ₈ are provided (not shown). As described above, the level-dependent control signal BLCLAMP precharges the local bit line and the global bit line of the selected memory cell during the level-dependent read operation described herein.

In FIG. 15, each page buffer 1511-1518 is connected to a different global bit line to enable a wide, parallel, read operation.

In the example shown, global bit lines GBL ₁ and GBL ₈ are connected to different sets of bit lines within the same level of each block. Therefore, the output of the voltage switch 1500 is provided to both the page buffer 1 (1511) connected to the global bit line GBL ₁ and the page buffer 8 (1515) connected to the global bit line GBL ₈ .

16 is a perspective view of another example of a three-dimensional NAND flash memory array structure having global bit lines each connected to a plurality of levels of memory cells, wherein a level-dependent bias may be applied as described herein. In the example shown, four levels of memory cells are shown, which represent blocks of memory cells that can contain many levels.

Insulation material was removed from the drawing to show additional structure. For example, the insulating layer was removed between the semiconductor strips in the ridge-shaped stack, and the insulating layer was removed between the ridge-shaped stacks of the semiconductor strip.

A multi-layer array is formed on the insulating layer, and the multi-layer array includes a plurality of conductive lines 1625-1, 1625-2, ..., WL1-WL1-WL1- ... 1625n-1, 1625n. The plurality of ridge-shaped stacks include semiconductor strips that act as local bit lines. The same level of semiconductor strips are electrically connected together by extensions having contact pads arranged in a stari- step manner.

The illustrated word line sequence numbers from 1 to N appearing forward from the rear of the overall structure are applied to the even memory pages. In the case of an odd memory page, the word line order is a descending order from N to 1 appearing forward from the rear of the entire structure.

As shown, the extensions 1602, 1603, 1604, 1605 on the first end of the block are electrically connected to the different global bit lines GBL ₁ to GBL ₄ . Likewise, extensions 1652, 1653, 1654, and 1655 are connected to different global bit lines GBL ₁ To GBL ₄ it is electrically connected to the.

Any given stack of semiconductor strips is connected to extensions 1602, 1603, 1604, 1605 or extensions 1652, 1653, 1654, 1655, and not to both. The stack of semiconductor strips has one of two opposite orientations: bit line end-source line end orientation or source line end-bit line end orientation.

The stack of semiconductor strips terminated at one end by extensions 1652,1653,1625 and 1655 includes an SSL gate structure 1619, a ground select line GSL 1626, a word line WL 1625-1 to a word line WL The source select line 1625-N, the ground select line GSL 1627, and the source line 1628 at the other end. These stacks of semiconductor strips do not reach extensions 1602, 1603, 1604, 1605.

A stack of semiconductor strips terminated at one end by extensions 1602, 1603, 1604 and 1605 includes an SSL gate structure 1609, a ground select line GSL 1627, word lines WL 1625-N to word lines WL (1625-1), ground select line GSL (1626), and is terminated at the other end by source line (1628). These stacks of semiconductor strips do not reach the extensions 1652, 1653, 1654, 1655.

The charge storage structure separates the word lines 1625-1 to word line 1625-n from the semiconductor strip. The ground select lines GSL 1626 and GSL 1627 are coplanar with a plurality of ridge-like stacks, similar to word lines.

Global bit lines GBL ₁ to GBL ₄ are formed in the metal layers ML1, ML2 and ML3. In the example shown, although masked by different parts of the figure, each global bit line GBL ₁ to GBL ₄ is connected to two different levels of blocks of memory cells. For example, in the figure, the global bit line GBL ₁ is connected to an extension 1605 which is connected to a set of semiconductor strips acting as a fourth level local bitline, and which acts as a first level local bitline And is connected to an extension 1652 connected to a set of semiconductor strips. This is further described below with reference to FIG.

17 is an exemplary layout view of the connection of global bit lines GBL ₁ to GBL ₈ to a plurality of multilevel blocks having memory cells arranged in the structure shown in FIG.

The global bit lines GBL ₁ to GBL ₈ are connected to local bit lines (not shown) at various levels of the block via the vertical connectors. In this figure, each block includes four levels for simplicity. The level at which the vertical connector is connected to the global bit line on top is indicated by level indices 1, 2, 3 and 4.

For example, the global bit line GBL ₁ is connected via a level 1 connector to a set of local bit lines within a first level of memory block M and via a level 2 connector to a set of local Bit line and is connected via a level 3 connector to a set of local bit lines within the third level of memory block M + 1.

The vertical connector for each block is arranged in a region labeled "Step Connector Structure for Local Bit Line ", which can be implemented by arranging the contact pads in each level in a step-step manner similar to that shown in Fig. have.

In the examples of Figs. 16 and 17, the global bit lines GBL ₁ to GBL ₈ are patterned in the third metal layer, and the string selection lines SSL ₁ to SSL ₈ are patterned in the first and second metal layers. The string selection signals are coupled to a string selection transistor on the alternate end of the block through a first metal segment parallel to the string below and a second metal segment parallel to the word line. Segments parallel to the word lines in block M are denoted as SSL ₁ through SSL ₈ in the figure. Vertical connections between the metal layers are indicated by the "Xed" box. The even and odd ground select lines GSL1 and GSL2 and word line WLx on the top and bottom of each block may be implemented in a patterned conductive layer, such as a polysilicon layer, below the first metal layer in this example.

Claims (12)

In an integrated circuit device,
A memory array,
A bias circuit for compensating for a change in threshold voltage corresponding to a memory state of a memory cell in the array by applying different bias conditions to the selected bit line
/ RTI >
The memory array comprising a plurality of bit lines connected through corresponding clamp transistors to corresponding data lines in a set of data lines connected to corresponding sensing circuits,
Wherein the bias circuit is responsive to a timing signal during a read operation of a selected memory cell in the memory array and wherein the bias circuit comprises a precharge circuit coupled to the data line and a bias terminal coupled to the control terminal of the clamp transistor, And a bias voltage source for applying a voltage,
Wherein the memory array comprises a NAND array each comprising a ground selection transistor and a string selection transistor, a ground selection line and a string selection line, and a plurality of NAND strings having word lines, A control circuit coupled to the circuit is configured and said control circuit causes a sequence for a read operation of a selected cell on a selected NAND string,
Charging the word line connected to the NAND string selected for the read operation to the target level at the first time interval T0 and applying a low reference voltage through the precharge circuit when the ground selection transistor is off and the string selection transistor is on Discharging the bit line,
- in a second time interval T1, the data line is precharged to the read reference voltage and the first clamp voltage is applied to the clamp transistor depending on the selected memory cell, so that the data line and the addressing line for the selected NAND string, And is precharged to a level that depends on < RTI ID = 0.0 >
Turning off the clamp transistor and disconnecting the precharge circuit from the data line, turning the ground selection transistor on when applying a read bias voltage to the source line,
In a fourth time interval T3, a second clamp voltage higher than the first clamp voltage is applied to the clamp transistor depending on the selected memory cell, and the level of the data line is detected to display the value of the data stored in the selected memory cell
Integrated circuit device. delete delete The method according to claim 1,
The boost circuit includes a boost circuit coupled to the data line and a boost voltage source coupled to the boost circuit, the boost circuit capacitively boosting the voltage on the data line by a boost amount in accordance with a timing signal during a read operation , The boost voltage source sets a boost amount dependent on the selected memory cell and the sequence applies a boost voltage within or before a second time period to boost the data line before sensing the level of the data line
Integrated circuit device. The method according to claim 1,
The word line voltage applied to the memory cells in the array is the same among the different bias conditions
Integrated circuit device. In an integrated circuit,
A plurality of blocks of the plurality of blocks each including a plurality of levels L (z), the plurality of levels of level L (z) each including a two-dimensional array of memory cells, The plurality of blocks including a plurality of local bit lines coupled to corresponding memory cells in the array,
A plurality of global bit lines, wherein global bit lines of the plurality of global bit lines include a plurality of connectors, connectors of a plurality of connectors are connected to corresponding local bit lines in a plurality of blocks, Wherein the corresponding local bit line is on a level L (z) different from the corresponding local bit line in another block of the plurality of blocks,
A switch circuit coupled to the plurality of global bit lines, the switch circuit being configured to apply a respective bias voltage to a corresponding global bit line dependent on a level L (z) of a selected memory cell,
≪ / RTI > 7. The method of claim 6, wherein there are N levels L (z) in each of the plurality of blocks, the level index z is 1 to N, and the connector is arranged on each global bit line of the plurality of global bit lines So that the statistical function of the level index for the level L (z) of the corresponding local bit line is constant
integrated circuit. The method according to claim 6,
And a bias circuit coupled to a switch circuit that compensates for a change in threshold voltage corresponding to a memory state of the selected memory cell based on a level L (z) of the selected memory cell
integrated circuit. The method according to claim 6,
And a buffer connected to said plurality of global bit lines and said switch circuit
integrated circuit. In an integrated circuit,
A memory array comprising a plurality of levels of memory cells, the plurality of levels of levels comprising a local bit line and a memory cell coupled to a local bit line,
A global bit line coupled to a corresponding set of local bit lines in the array,
A decoding circuit for selecting the memory cells in the plurality of levels,
A bias circuit coupled to a global bit line to provide a selected bias voltage, said bias circuit being responsive to a control signal to select a bias voltage for a global bit line corresponding to a level of a selected memory cell,
≪ / RTI > 11. The method of claim 10,
A set of local bit lines connected to a given one global bit line of global bit lines may include a local bit line within two or more levels of the memory array
integrated circuit. 11. The method of claim 10,
The global bit lines are connected to corresponding data lines of a set of data lines via respective clamp transistors, the data lines are connected to a corresponding sense circuit, and the bias circuit receives a timing signal Wherein the bias circuit comprises a precharge circuit coupled to the data line and a bias voltage source for applying a bias voltage to the control terminal of the clamp transistor depending on the level of the selected memory cell
integrated circuit.

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