JP2011238303A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress power consumption while maintaining data readout speed.SOLUTION: A semiconductor memory device comprises a bit line BL; a plurality of word lines (corresponding to WLA1-WLAn); memory cells (corresponding to CellB1-CellBn) that are located at respective intersections between the bit line BL and the plurality of word lines and each of which includes a switch element (corresponding to TrA1) on/off controlled by a signal of the word line and a memory element (corresponding to RB1) being able to have a read-out current flowing through the bit line BL when the switch element is closed; and a sense amplifier (corresponding to 1A) that amplifies the read-out current flowing through the bit line BL, and is configured to have a constant current value of the read-out current flowing into the memory element in a conductive state when the memory element in the memory cell, in which a signal of the connected word line is activated, is in the conductive state, irrespective of a connection position of the bit line BL of the memory cell.

Description

  The present invention relates to a semiconductor memory device, and more particularly to a data read technique in a semiconductor memory device.

  With the increasing functionality of electronic devices, programmable cells are frequently used in built-in semiconductor integrated circuits. One of such programmable cells is a non-volatile state memory element formed in a semiconductor device, which is called a one-time programmable cell (OTP cell) and can be written only once. For example, Patent Document 1 discloses an OTP memory cell in which the breakdown voltage of an OTP cell can be made lower than that of a conventional OTP cell. According to the OTP memory cell, the selection transistor and the peripheral circuit can be configured by using a transistor having a small transistor size and a low breakdown voltage, and a circuit area can be reduced.

  By the way, there is a growing demand for an increase in memory capacity due to an increase in the number of stored programs and a reduction in power consumption for battery driving in portable devices and the like. As the memory capacity increases, the bit line to which the programmable cell is connected becomes longer and the parasitic resistance of the bit line tends to increase. For this reason, the cell current is reduced, and the data read speed of the cell is lowered. However, when the cell current of all cells is increased, the operating current of the programmable cell is increased. For this reason, there is an increasing need for a technique for suppressing the operating current while maintaining the cell data reading speed.

  In view of this, Japanese Patent Application Laid-Open No. H10-228688 discloses an apparatus that can compensate for the decrease in voltage and current based on the position / address of the memory cell. This device obtains a wider read margin by applying a lower read voltage to the near-near bit than to the far-far bit. Alternatively, the read voltage is fixed, but a large read margin is obtained by changing the reference current depending on whether the memory cell being read is a near-near bit or a far-far bit.

JP 2008-288358 A Japanese translation of PCT publication No. 2008-524772

  The following analysis is given in the present invention.

  By the way, the device described in Patent Document 2 only shows the idea of compensating for the decrease in voltage and current based on the position / address of the memory cell, and does not disclose a specific circuit configuration. For this reason, a specific circuit cannot be realized as a semiconductor memory device.

  A semiconductor memory device according to one aspect (side surface) of the present invention is arranged at an intersection of a bit line, a plurality of word lines, and a bit line and a plurality of word lines, respectively, and opening / closing is controlled by a signal of the word line. And a sense cell that amplifies the read current that flows through the bit line, and a connected word line. When the memory element in the memory cell in which the signal is activated is conductive, the current value of the read current flowing through the memory element in the conductive state is made constant regardless of the connection position of the bit line of the memory cell. Constitute.

  According to the present invention, it is possible to suppress power consumption while maintaining a data reading speed.

1 is a circuit diagram of a main part of a semiconductor memory device according to a first embodiment of the present invention. It is a figure showing the electric current of each antifuse cell which concerns on 1st Example of this invention. FIG. 6 is a circuit diagram of a main part of a semiconductor memory device according to a second embodiment of the present invention.

  The semiconductor memory device according to the embodiment of the present invention includes a bit line (BL in FIG. 1), a plurality of word lines (corresponding to WLA1 to WLAn in FIG. 1), and an intersection of the bit line and the plurality of word lines, respectively. A switching element (corresponding to TrA1 in FIG. 1) arranged and controlled to open and close by a signal on the word line and a storage element (corresponding to RB1 in FIG. 1) through which a read current can flow through the bit line when the switching element is closed ) Including a memory cell (corresponding to CellB1 to CellBn in FIG. 1) and a sense amplifier (corresponding to 1A in FIG. 1) for amplifying a read current flowing through the bit line, and the signal of the connected word line is active The current value of the read current flowing through the memory element that is in a conductive state when the memory element in the memory cell is in a conductive state depends on the connection position of the bit line of the memory cell. Configured so as to be constant.

  In the semiconductor memory device, the memory cell includes a voltage control element (corresponding to TrB1 in FIG. 1) between the switch element and the storage element, and the voltage control element has a predetermined end of the memory element connected to the voltage control element. You may make it control to the voltage level of.

  In a semiconductor memory device, a voltage control element (corresponding to TrH1 in FIG. 3) is provided between one end of a bit line and a sense amplifier, and the voltage control element is a bit line in a memory cell in which a word line signal is activated. One end of the bit line may be controlled to a voltage level corresponding to the connection position.

  The semiconductor memory device includes a level adjustment circuit (1B in FIG. 1) that outputs a voltage corresponding to a predetermined voltage level, and the switch element is supplied with the signal of the corresponding word line to the gate, The voltage control element is a first MOS transistor (TrA1 in FIG. 1) connected to the bit line, the gate is connected to the output of the level adjusting circuit, and one of the source and drain is connected to the source and drain of the first MOS transistor. A second MOS transistor (TrB1 in FIG. 1) may be connected to the other drain and the other of the source / drain to one end of the memory element.

  The semiconductor memory device includes a level adjustment circuit (1D in FIG. 3) that outputs a voltage corresponding to the position of the activated word line. A first MOS transistor (TrA1 in FIG. 3) in which one of the drains is connected to the bit line and the other of the source / drain is connected to one end of the storage element, and the voltage control element has a gate connected to the output of the level adjustment circuit. A second MOS transistor (TrH1 in FIG. 3) that connects one of the source and drain to the input end of the bit line current of the sense amplifier and connects the other of the source and drain to one end of the bit line. Also good.

  In the semiconductor memory device, the memory element may be a nonvolatile memory element.

  In the semiconductor memory device, the nonvolatile memory element may be an antifuse element.

  According to the semiconductor memory device as described above, the cell current can be made constant by adjusting the control voltage of the voltage control element, regardless of whether the memory cell is at the near end or the far end of the bit line. Therefore, the cell operating current, that is, the power consumption of the semiconductor memory device can be suppressed while maintaining the cell data reading speed.

  Hereinafter, it will be described in detail with reference to the drawings in accordance with embodiments.

  FIG. 1 is a circuit diagram of a main part of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, the semiconductor memory device includes a differential amplifier 1A, a level adjustment circuit 1B, a word selection circuit 1C, and antifuse cells CellB1 to CellBn. Note that a circuit related to reading after the output Q of the differential amplifier 1A, an address-related circuit, and the like are well-known techniques and are not related to the present invention, and thus description thereof is omitted.

  The differential amplifier 1A inputs the reference current Iref from one input terminal (−), connects one end of the bit line BL to the other input terminal (+), and reads the reference current Iref flowing through the bit line BL and the reference current Iref. It functions as a sense amplifier that amplifies the difference.

  Antifuse cells CellB1 to CellBn connected to the bit line BL show only the antifuse cells in the row direction. The antifuse cells are arranged in an array also in the column direction, but are omitted for simplification of illustration.

  The word selection circuit 1C receives the address signal A and outputs word selection signals WLA1 to WLAn via the word lines to the antifuse cells CellB1 to CellBn, respectively. A read current read from the antifuse cell corresponding to any of the word selection signals WLA1 to WLAn that is activated flows to the differential amplifier 1A via the bit line BL.

  In the bit line BL, a parasitic resistance RPA1 exists between the differential amplifier 1A and the near-end antifuse cell CellB1, and a parasitic resistance RPA2 exists between the antifuse cell CellB1 and the antifuse cell CellB1. A parasitic resistance RPAn exists between the antifuse cell CellBn-1 and the far-end antifuse cell CellBn.

  The level adjustment circuit 1B is a circuit that outputs a gate voltage control signal VgB that is a constant control voltage (analog voltage) to the antifuse cells CellB1 to CellBn, and is configured by a simple circuit such as resistance division.

  Hereinafter, the configuration and connection of the antifuse cell CellB1 closest to the differential amplifier 1A (near end) will be described. Since the configuration and connection of the other antifuse cells CellB2 to CellBn are the same as those of the antifuse cell CellB1, the description thereof is omitted.

  The antifuse cell CellB1 includes a selection transistor TrA1, an antifuse element (hereinafter referred to as a resistance RB1 after destruction), and an N-channel MOS transistor TrB1. Here, the N-channel MOS transistor TrB1 can be formed of a depletion type N-channel MOS transistor.

  The selection transistor TrA1 has a drain connected to the bit line BL, a source connected to the drain of the N-channel MOS transistor TrB1, and a word selection signal WLA1 applied to the gate. The selection transistor TrA1 becomes conductive when the word selection signal WLA1 is at L level, and a read current flows from the bit line BL to the resistor RB1 after destruction of the antifuse element via the N-channel MOS transistor TrB1.

  N-channel MOS transistor TrB1 has a source connected to one end of resistor RB1, and provides gate voltage control signal VgB from level adjusting circuit 1B to the gate. The other end of the resistor RB1 is grounded.

  Next, the operation of the antifuse cells CellB1 to CellBn will be described.

The voltage Vn of the bit line BL of the far end cell is lower than the voltage V1 of the bit line BL of the near end cell due to the influence of the parasitic resistances RPA1 to RPAn. Here, the current flowing through the bit line BL is IBL, and the resistance values of the parasitic resistors RPA1 to RPAn are all set to the same R. Since n resistors R are connected in series on the bit line BL, Vn is expressed by the following equation (1).
Vn = V1-IBL * nR (1)

  Here, the cell current flowing in the far-end cell is set to be the same as the cell current flowing in the near-end cell, thereby ensuring a determination margin with respect to the reference current Iref in the differential amplifier 1A. Therefore, the cell currents of the antifuse cells CellB1 to CellBn are set by setting the gate voltage control signal VgB of the N-channel MOS transistors TrB1 to TrBn higher by V1-Vn in advance by the voltage drop to the far-end cell. To do.

In this case, assuming that the threshold value of the N-channel transistors TrB1 to TrBn is Vth and the voltage applied to the gate is VgB, the source voltages VRB1 to VRBn of the N-channel transistors TrB1 to TrBn are expressed by the following equation (2).
VRB1 to VRBn = VgB−Vth (2)

  The level adjustment circuit 1B adjusts the potential of the gate voltage control signal VgB to adjust the cell current Icell flowing through the antifuse cell. That is, by making the gate voltage control signal VgB of the N channel MOS transistors TrB1 to TrBn constant, the source voltages VRB1 to VRBn of the N channel transistors TrB1 to TrBn become constant. As a result, the cell current Icell flowing through each antifuse cell becomes constant. The differential amplifier 1A compares the reference current Iref with the cell current Icell flowing through the antifuse cell and performs a read operation.

Since it is the bit line voltage Vn of the far-end cell, the respective gate voltages VgB of the N-channel MOS transistors of the near-end cell and the far-end cell are expressed by Expression (3), where the threshold value of the N-channel MOS transistor is Vth. The
VgB = Vn + Vth (3)

Expression (4) is established from Expressions (2) and (3).
VRB1 to VRBn = Vn (4)

  Therefore, if the resistance values of the resistors RB1 to RBn are the same, the cell currents Icell1 to Icelln of the near-end cell to the far-end cell are constant from the equation (4). That is, as shown in FIG. 2, the current of each antifuse cell is suppressed to the same value as the current Icelln of the far-end antifuse cell CellBn regardless of the connection position of the bit line of the antifuse cell. . According to such a configuration, it is possible to suppress the power consumption of the antifuse cell while maintaining the cell data reading speed.

  FIG. 3 is a circuit diagram of the main part of the semiconductor memory device according to the second embodiment of the present invention. In FIG. 3, the same reference numerals as those in FIG. The difference in circuit configuration from the first embodiment is that (1) in each of the antifuse cells CellG1 to CellGn, the N-channel MOS transistors TrB1 to TrBn in FIG. That is, it is arranged between the input terminal (+) of the differential amplifier 1A and one end of the bit line BL, and (2) the level adjustment circuit 1D inputs the address signal A.

  The level adjustment circuit 1D is a circuit that outputs a voltage that takes into account the potential drop due to the layout arrangement position (bit line connection position) of each antifuse cell. The level adjustment circuit 1D is a circuit that selects a resistance division voltage using the address signal A. For example, it is composed of a D / A conversion circuit or the like. The level adjustment circuit 1D adjusts the cell current Icell flowing through the antifuse cell selected by the address signal A by changing the gate level VgG of the N-channel MOS transistor TrH1 according to the address signal A.

The level adjustment circuit 1D expresses the gate voltage of the N-channel MOS transistor TrH1 when the near-end cell is selected, and the gate voltage of the N-channel MOS transistor TrH1 when the far-end cell is selected. The voltage VgG is output so as to satisfy (6).
VgG1 = Vn + Vth (5)
VgGn = Vn + (V1-Vn) + Vth
= V1 + Vth (6)

By setting the gate level of the N-channel MOS transistor TrH1 at the time of selection of the near-end cell and the far-end cell as equations (5) and (6), it is applied to the resistors RB1 and RBn of the near-end cell and the far-end cell, respectively. The voltages VRG1 and VRGn are both Vn as shown in the following equations (7) and (8). In addition, Formula (1) is used for derivation of Formula (8).
VRG1 = VgG1-Vth
= Vn + Vth-Vth
= Vn Formula (7)
VRGn = VgGn−Vth−IBL * nR
= V1 + Vth-Vth-IBL * nR
= V1-IBL * nR
= Vn Formula (8)

  Therefore, if the resistance values of the resistors RB1 to RBn are the same, the cell current in each antifuse cell is constant regardless of the position of the antifuse cell.

  According to the present embodiment, only one N-channel MOS transistor TrH1 is arranged at the base of the bit line BL, not in the antifuse cells CellG1 to CellGn. Therefore, the area of the antifuse cells arranged in large numbers can be reduced.

  It should be noted that the disclosures of the aforementioned patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1A Differential amplifier 1B, 1D level adjustment circuit 1C Word selection circuit BL Bit lines CellB1 to CellBn, CellG1 to CellGn Antifuse cells RB1 to RBn Resistance (after antifuse element destruction)
RPA1 to RPAn Bit line parasitic resistance TrA1 to TrAn Select transistor TrB1 to TrBn, TrH1 N-channel MOS transistor

Claims (7)

Bit lines,
Multiple word lines,
A switching element that is arranged at an intersection of the bit line and the plurality of word lines and whose opening / closing is controlled by a signal of the word line, and a read current can flow through the bit line when the switching element is closed A memory cell including a storage element;
A sense amplifier that amplifies the read current flowing in the bit line;
With
When the memory element in the memory cell in which the signal of the connected word line is active is in the conductive state, the current value of the read current flowing through the storage element in the conductive state is determined as the bit line of the memory cell. A semiconductor memory device characterized by being configured so as to be constant regardless of the connection position. The memory cell includes a voltage control element between the switch element and the storage element,
2. The semiconductor memory device according to claim 1, wherein the voltage control element controls one end of the memory element connected to the voltage control element to a predetermined voltage level. A voltage control element is provided between one end of the bit line and the sense amplifier,
2. The voltage control element according to claim 1, wherein one end of the bit line is controlled to a voltage level corresponding to a connection position of the bit line in the memory cell in which a signal of the word line is activated. Semiconductor memory device. A level adjustment circuit for outputting a voltage corresponding to the predetermined voltage level;
The switch element is a first MOS transistor in which a signal of the corresponding word line is supplied to a gate, and one of a source and a drain is connected to the bit line,
The voltage control element has a gate connected to the output of the level adjustment circuit, one source / drain connected to the other source / drain of the first MOS transistor, and the other source / drain connected to the memory element. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is a second MOS transistor connected to one end. A level adjustment circuit that outputs a voltage according to the position of the activated word line;
The switch element is supplied with a signal of the corresponding word line to the gate, connects one of the source and drain to the bit line, and connects the other of the source and drain to one end of the storage element. Because
The voltage control element has a gate connected to the output of the level adjustment circuit, one of the source and the drain connected to the input end of the bit line current of the sense amplifier, and the other of the source and the drain connected to one end of the bit line. 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is a second MOS transistor to be connected.   The semiconductor memory device according to claim 1, wherein the memory element is a nonvolatile memory element.   The semiconductor memory device according to claim 6, wherein the nonvolatile memory element is an antifuse element.

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