KR101691094B1 - Nonvolatile memory device and memory system thereof - Google Patents

Abstract

A nonvolatile memory device according to an embodiment of the present invention includes:
A memory cell array including a plurality of memory cells stacked in a direction orthogonal to the substrate; A row select circuit coupled to the memory cell array through word lines; And a ramper for controlling the rising ramp of at least one of the driving signals to be equal to the rising ramp of the reference driving signal when the same level of driving signals are provided through the word lines. The nonvolatile memory device according to the embodiment of the present invention can prevent the read failure due to the reduction of the read margin.

Description

NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM THEREOF FIELD OF THE INVENTION The present invention relates to a nonvolatile memory device,

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device and a memory system including the same.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored in the volatile memory device is lost when power supply is interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory device, a PRAM ), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory devices are largely divided into NOR type and NAND type.

Recently, a semiconductor memory device having a three-dimensional array structure has been studied to improve the integration degree of the semiconductor memory device.

It is an object of the present invention to provide a nonvolatile memory device that provides drive signals with a constant rising ramp to a memory cell array and a memory system including the same.

A nonvolatile memory device according to an embodiment of the present invention includes: a memory cell array including a plurality of memory cells stacked in a direction orthogonal to a substrate; A row select circuit for generating drive signals and providing the drive signals to the memory cell array through word lines; And a ramper for adjusting a rising slope of at least one of the driving signals so that the driving signals have a constant rising slope.

In an embodiment, the planar memory cells parallel to the substrate share a word line.

In an embodiment, the memory cell array includes bit lines; And pillars formed between the bit lines and the substrate, wherein the cross-sectional area of the pillars in a direction parallel to the substrate decreases as the substrate is closer to the substrate.

In an embodiment, the word lines are arranged side by side between the substrate and the bit lines in a direction orthogonal to the pillars, and the ramper is configured to increase a rising ramp of a driving signal provided to the word lines, Same as the slop.

As an embodiment, the ramper includes ramping blocks corresponding to the word lines, respectively, and the ramping blocks adjust the rising ramp of the driving signals to the same as the rising ramp of the reference driving signal.

In an embodiment, the ramper includes at least one ramping block corresponding to a word line adjacent to the substrate among the word lines, wherein the at least one ramping block includes a ramping of a driving signal provided to a word line adjacent to the substrate The slope is adjusted to be equal to the rising slope of the reference drive signal.

In an embodiment, the memory cell array includes bit lines; And first and second sub pillars formed between the bit lines and the substrate, the second sub pillars being each stacked on the first sub pillars and being parallel to the substrate The cross-sectional areas of the first and second sub pillars in one direction decrease as they approach the substrate.

In an embodiment, the word lines are divided into first and second word line groups, each of which is orthogonal to the first and second sub pillars and arranged side by side between the substrate and the bit line, 1 and the second word line group to the same as the rising ramp of the reference driving signal.

In an embodiment, the ramper includes at least one first ramping block corresponding to a word line adjacent to the substrate of the first word line group and at least one first ramping block corresponding to a word line adjacent to the substrate of the second word line group Wherein the first ramping block adjusts the rising ramp of the driving signal provided to the word line adjacent to the substrate of the first word line group to be equal to the rising ramp of the reference driving signal And the second ramping block adjusts the rising ramp of the driving signal provided to the word line adjacent to the substrate of the second word line group to be equal to the rising ramp of the reference driving signal.

In an embodiment, the ramper generates drive signals that step up to a target voltage.

A non-volatile memory device according to an embodiment of the present invention includes a substrate and a plurality of memory cells stacked in a direction orthogonal to the substrate, the non-volatile memory device comprising: a first word line; A second word line located between the substrate and the first word line; A row selection circuit for providing first and second driving signals to the first and second word lines, respectively; And a ramper for adjusting the rising ramp of the first and second driving signals in the same manner as the rising ramp of the reference driving signal.

As an embodiment, bit lines; And a pillar formed between the bit lines and the substrate, the cross-sectional area of the pillars being coplanar with the first word line being coplanar with the second word line Is greater than the cross-sectional area of the pillars.

In one embodiment, the ramper includes first and second ramping blocks corresponding to the first and second word lines, respectively, wherein the first and second ramping blocks are connected to a rising ramp of the first and second drive signals, Is adjusted in the same manner as the rising slope of the reference drive signal.

In an embodiment, the ramper includes a ramping block corresponding to the second word line, and the ramping block adjusts the rising ramp of the second driving signal to be equal to the rising ramp of the first driving signal.

In an embodiment, the planar memory cells parallel to the substrate share a word line.

A memory system according to an embodiment of the present invention includes a nonvolatile memory device; And a controller configured to control the nonvolatile memory device, wherein the nonvolatile memory device comprises: a memory cell array including a plurality of memory cells stacked in a direction orthogonal to the substrate; A row select circuit for generating drive signals and providing the drive signals to the memory cell array through word lines; And a ramper for adjusting a rising slope of at least one of the driving signals so that the driving signals have a constant rising slope.

In an embodiment, the memory cell array includes bit lines; And a filigree formed between the bit lines and the substrate, the cross-sectional area of the pillars in a direction parallel to the substrate decreases as the substrate is closer to the substrate.

In an embodiment, the word lines are arranged side by side between the substrate and the bit lines in a direction orthogonal to the pillars, and the ramper is configured to increase a rising ramp of a driving signal provided to the word lines, Same as the slop.

In an embodiment, the memory cell array includes bit lines; And first and second sub pillars formed between the bit lines and the substrate, the second sub pillars being each stacked on the first sub pillars and being parallel to the substrate The cross-sectional areas of the first and second sub pillars in one direction decrease as they approach the substrate.

In an embodiment, the word lines are divided into first and second word line groups, each of which is orthogonal to the first and second sub pillars and arranged side by side between the substrate and the bit line, 1 and the second word line group to the same as the rising ramp of the reference driving signal.

A non-volatile memory device according to an embodiment of the present invention may provide drive signals having a constant rising slope to a memory cell array. Therefore, a decrease in reliability due to the reduction in read margin can be prevented.

1 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.
2 is a block diagram showing the memory cell array of FIG.
FIG. 3 is a perspective view showing a first embodiment of one of the memory blocks of FIG. 2. FIG.
4 is a cross-sectional view taken along the line I-I 'of the memory block of FIG.
5 is a cross-sectional view showing the transistor structure of FIG.
Fig. 6 is a circuit diagram showing an equivalent circuit according to the first embodiment of the memory block described with reference to Figs. 3 to 5. Fig.
7 is a view showing a raising slope of drive signals in a general case.
FIG. 8 is a block diagram showing the word line driver and the ramper of FIG. 1;
FIG. 9 is a view for explaining the driving block of FIG. 8 in more detail.
10 is a view for explaining the ramping block of FIG. 8 in more detail.
11 is a timing chart showing the operation of the first ramping block of FIG.
12 and 13 show a first driving signal in which the rising slope is adjusted by the first ramping block.
14 is a block diagram illustrating a nonvolatile memory device according to another embodiment of the present invention.
15 is a diagram for explaining the word line driver of FIG. 14 in more detail.
16 is a perspective view showing a modification of the memory block of Fig.
17 is a cross-sectional view taken along the line II-II 'of the memory block of FIG.
18 is a circuit diagram showing an equivalent circuit of the memory block described with reference to Figs. 16 and 17. Fig.
19 is a block diagram illustrating a word line driver for providing drive signals to the memory blocks of Figs. 16-18.
20 to 22 are diagrams for explaining a read disturbance when the rising slope is not adjusted.
23 is a circuit diagram showing an equivalent circuit according to the second embodiment of the memory block described with reference to Figs. 3 to 5. Fig.
Fig. 24 is a circuit diagram showing an equivalent circuit according to the third embodiment of the memory block described with reference to Figs. 3 to 5. Fig.
25 is a circuit diagram showing an equivalent circuit according to the fourth embodiment of the memory block described with reference to Figs. 3 to 5. Fig.
26 is a circuit diagram showing an equivalent circuit according to the fifth embodiment of the memory block described with reference to Figs. 3 to 5. Fig.
FIG. 27 is a perspective view showing a second embodiment of one of the memory blocks of FIG. 2. FIG.
28 is a perspective view showing a modification of the memory block of FIG. 27;
FIG. 29 is a perspective view showing a third embodiment of one of the memory blocks of FIG. 3. FIG.
30 is a cross-sectional view taken along line III-III 'of the memory block of FIG. 29;
FIG. 31 is a perspective view showing a modification of the memory block of FIG. 29;
32 is a cross-sectional view taken along line IV-IV 'of the memory block of FIG. 31;
FIG. 33 is a perspective view showing a fourth embodiment of one of the memory blocks of FIG. 3. FIG.
FIG. 34 is a cross-sectional view taken along the line V-V 'of the memory block of FIG. 33; FIG.
35 is a perspective view showing a modification of the memory block of FIG. 33;
FIG. 36 is a cross-sectional view taken along the line VI-VI 'of the memory block of FIG. 35;
FIG. 37 is a perspective view showing a fifth embodiment of one of the memory blocks of FIG. 2. FIG.
38 is a cross-sectional view taken along line VII-VII 'of the memory block of FIG. 37;
FIG. 39 is a block diagram showing a memory system including the nonvolatile memory device of FIG. 1 or FIG.
40 is a block diagram showing an application example of the memory system of FIG.
41 is a block diagram illustrating a computing system including the memory system described with reference to FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. . The same elements will be referred to using the same reference numerals. Similar components will be referred to using similar reference numerals.

In a nonvolatile memory device including a memory block having a three-dimensional structure, the rising slopes of the driving signals provided to the word lines may be different from each other due to factors such as a process. The difference in the rising slope may cause a read failure due to a decrease in the read margin. A non-volatile memory device according to an embodiment of the present invention uses a ramping technique to adjust the rising ramp of the driving signals. For example, the non-volatile memory device can prevent a decrease in the read margin by adjusting the rising ramp of the drive signals provided to the word lines, respectively. Hereinafter, for convenience of description, a nonvolatile memory device according to an embodiment of the present invention will be described focusing on program operation. However, the technical idea of the present invention can also be applied to a read operation and an erase operation.

1 is a block diagram illustrating a non-volatile memory device 100 in accordance with an embodiment of the present invention. 1, a non-volatile memory device 100 includes a memory cell array 110, a high voltage generator 120, a row select circuit 130, a read and write circuit 140, a data input / output circuit 150, And control logic 160.

The memory cell array 110 is connected to the row selection circuit 130 via the word lines WL and to the read and write circuit 140 via the bit lines BL. The memory cell array 110 includes a plurality of memory cells. Illustratively, memory cell array 110 is comprised of a plurality of memory cells capable of storing one or more bits per cell.

The high voltage generator 120 generates the program voltage Vpgm and the pass voltage Vpass to be used in the program and delivers it to the word line driver 132. [ The high voltage generator 120 operates in response to control of the control logic 160. Illustratively, the high voltage generator 120 may comprise a plurality of transistors and a plurality of pumping capacitors.

The row selection circuit 130 receives the program voltage Vpgm and the pass voltage Vpass from the high voltage generator 120. In a program operation, the row selection circuit 130 provides the program voltage Vpgm to the selected word line and the pass voltage Vpass to the unselected word line. The row selection circuit 130 includes a word line driver 131, a ramper 132, and a row decoder 133.

The word line driver 131 receives the program voltage Vpgm and the pass voltage Vpass from the high voltage generator 120. The word line driver 131 transfers the program voltage Vpgm or the pass voltage Vpass to each signal line SL in response to a part of the address RAi of the row address RA. For example, in a program operation, the word line driver 131 supplies the program voltage Vpgm to the signal line corresponding to the selected word line and the pass voltage Vpass to the signal line corresponding to the unselected word line to provide.

The rampper 132 receives the program voltage Vpgm or the pass voltage Vpass corresponding to each word line from the word line driver 131. [ The rampper 132 generates drive signals DS that increase stepwise to the target voltage level. For example, when receiving the program voltage Vpgm, the rampper 132 generates a driving signal that gradually increases to the program voltage Vpgm. When the pass voltage Vpass is received, the rampper 132 generates a driving signal that gradually increases to the pass voltage Vpass.

The row decoder 133 receives the driving signals DS from the ramper 132. The row decoder 133 selects the word lines WL to which the driving signals DS are to be applied in response to the remaining address RAj of the row address RA. For example, the input address RAj may be an address for selecting a memory block. In this case, the row decoder 133 selects the memory block in response to the input address RAj. The row decoder 133 transfers the driving signals DS to the word lines of the selected memory block, respectively.

The read and write circuit 140 is connected to the memory cell array 110 through the bit lines BL and to the data input / output circuit 150 via the data lines DL. The read / write circuit 140 receives data from the data input / output circuit 150 and writes the received data to the memory cell array 110. The read and write circuit 140 reads data from the memory cell array 110 and transfers the read data to the data input / output circuit 150. Illustratively, the read and write circuitry 140 may include components such as a page buffer (or page register) to perform reading and writing of data, and a column select circuit to select bit lines BL.

The data input / output circuit 150 is connected to the read and write circuit 140 via the data lines DL. The data input / output circuit 150 operates in response to the control of the control logic 160. The data input / output circuit 150 is configured to exchange data (DATA) with the outside. The data input / output circuit 150 transfers data (DATA) transmitted from the outside to the read and write circuit 140 through the data lines DL. The data input / output circuit 150 outputs data (DATA) transferred through the data lines DL from the read / write circuit 140 to the outside. By way of example, the data input / output circuit 150 may include components such as a data buffer.

The control logic 160 controls all operations of the nonvolatile memory device 100. The control logic 160 is configured to control the high voltage generator 120, the row selection circuit 130, the read and write circuit 140, and the data input / output circuit 150. The control logic 160 operates in response to a control signal CTRL transmitted from the outside.

The non-volatile memory device 100 according to the embodiment of the present invention provides the word lines with driving signals DS < 1: n > having a constant rising slope. Since the driving signals DS < 1: n > have a constant rising ramp, the nonvolatile memory device 100 can prevent the reduction of the reading margin due to the program speed difference. Therefore, the reliability of the nonvolatile memory device 100 can be improved. Hereinafter, the structure of the memory cell array 110 according to the embodiment of the present invention will be described in more detail.

2 is a block diagram illustrating the memory cell array 110 of FIG. Referring to FIG. 2, the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block BLK has a three-dimensional structure (or vertical structure). For example, each memory block BLK includes structures extending along the first to third directions. For example, each memory block BLK includes a plurality of NAND strings NS extending along a second direction. For example, a plurality of NAND strings NS may be provided along the first and third directions.

Each NAND string NS is connected to a bit line BL, a string selection line SSL, a ground selection line GSL, word lines WL, and a common source line CSL. That is, each memory block includes a plurality of bit lines BL, a plurality of string selection lines SSL, a plurality of ground selection lines GSL, a plurality of word lines WL, and a common source line CSL Lt; / RTI &gt; The memory blocks BLK1 to BLKz are described in more detail with reference to Fig.

Illustratively, the memory blocks BLK1 to BLKz are selected by the row selection circuit 130 shown in Fig. For example, the row selection circuit 130 selects the memory block BLK corresponding to the decoded row address among the memory blocks BLK1 to BLKz.

3 is a perspective view showing a first embodiment of one of the memory blocks BLK1 to BLKz of FIG. 2 (BLKi). 4 is a cross-sectional view taken along the line I-I 'of the memory block BLKi of FIG. Referring to Figs. 3 and 4, the memory block BLKi includes structures extended along first to third directions.

First, a substrate 111 is provided. Illustratively, the substrate 111 will be a well with a first type. For example, the substrate 111 may be a p-well formed by implanting a Group 5 element such as boron (B, Boron). For example, the substrate 111 may be a pocket p-well provided in an n-well. In the following, it is assumed that the substrate 111 is a p-well. However, the substrate 111 is not limited to being a p-well.

On the substrate 111, a plurality of doped regions 311 to 314 extending along the first direction are provided. For example, the plurality of doped regions 311 - 314 may have a second type different from the substrate 111. For example, the plurality of doped regions 311 to 314 may have n types. Hereinafter, it is assumed that the first to fourth doping regions 311 to 314 have n types. However, the first to fourth doped regions 311 to 314 are not limited to having an n-type.

A plurality of insulating materials 112 extending along the first direction are sequentially provided along the second direction on the region of the substrate 111 between the first and second doped regions 311 and 312. For example, a plurality of insulating materials 112 may be provided spaced a certain distance along the second direction. Illustratively, the insulating materials 112 will comprise an insulating material such as silicon oxide.

A plurality of pillars (not shown) disposed sequentially along the first direction on the region of the substrate 111 between the first and second doped regions 311 and 312 and through the insulating materials 112 along the second direction. Are provided. Illustratively, the plurality of pillars 113 will be connected to the substrate 111 through the insulating materials 112.

Illustratively, each pillar 113 will comprise a plurality of materials. For example, the surface layer 114 of each pillar 113 may comprise a silicon material having a first type. For example, the surface layer 114 of each pillar 113 will comprise a silicon material having the same type as the substrate 111. In the following, it is assumed that the surface layer 114 of each pillar 113 includes p-type silicon. However, the surface layer 114 of each pillar 113 is not limited to include p-type silicon.

The inner layer 115 of each pillar 113 is comprised of an insulating material. For example, the inner layer 115 of each pillar 113 may comprise an insulating material such as silicon oxide. For example, the inner layer 115 of each pillar 113 may include an air gap.

In an area between the first and second doped regions 311 and 312 an insulating layer 116 is provided along the exposed surfaces of the insulating materials 112, the pillars 113, and the substrate 111. Illustratively, the insulating film 116 provided on the exposed surface in the second direction of the last insulating material 112 provided along the second direction can be removed.

Illustratively, the thickness of the insulating film 116 may be less than one-half the distance between the insulating materials 112. That is, between the insulating film 116 provided on the lower surface of the first insulating material of the insulating materials 112 and the insulating film 116 provided on the upper surface of the second insulating material below the first insulating material, 112 and the insulating film 116 may be disposed.

In the region between the first and second doped regions 311 and 312, the first conductive materials 211 to 291 are provided on the exposed surface of the insulating film 116. For example, a first conductive material 211 extending along a first direction is provided between the substrate 111 and the insulating material 112 adjacent to the substrate 111. More specifically, a first conductive material 211 extending in a first direction is provided between the insulating film 116 and the substrate 111 on the lower surface of the insulating material 112 adjacent to the substrate 111. [

Hereinafter, the heights of the first conductive materials 211 to 291, 212 to 292, and 213 to 293 are defined. The first conductive materials 211 to 291, 212 to 292, and 213 to 293 are defined to have first to ninth heights sequentially from the substrate 111. That is, the first conductive materials 211 to 213 adjacent to the substrate 111 have a first height. The first conductive materials 291 to 293 adjacent to the second conductive materials 331 to 333 have a ninth height. As the distance between the first conductive material and the substrate 111 increases, the height of the first conductive material increases.

A first conductive material extending along the first direction is formed between the insulating film 116 on the upper surface of the specific insulating material and the insulating film 116 on the lower surface of the insulating material disposed over the specific insulating material, / RTI &gt; Illustratively, a plurality of first conductive materials 221 - 281 extending in a first direction are provided between the insulating materials 112. Illustratively, the first conductive materials 211-291 may be metallic materials. Illustratively, the first conductive materials 211-291 may be conductive materials such as polysilicon or the like.

In the region between the second and third doped regions 312 and 313, the same structure as the structure on the first and second doped regions 311 and 312 will be provided. Illustratively, in regions between the second and third doped regions 312, 313, a plurality of insulating materials 112 extending in a first direction, sequentially disposed along a first direction, A plurality of pillars 113 passing through the plurality of insulating materials 112, an insulating film 116 provided on the exposed surfaces of the plurality of insulating materials 112 and the plurality of pillars 113, A plurality of first conductive materials (212-292) extending along one direction are provided.

In the region between the third and fourth doped regions 313 and 314, the same structure as the structure on the first and second doped regions 311 and 312 will be provided. Illustratively, in a region between the third and fourth doped regions 312, 313, a plurality of insulating materials 112 extending in a first direction, sequentially disposed along a first direction, A plurality of pillars 113 passing through the plurality of insulating materials 112, an insulating film 116 provided on the exposed surfaces of the plurality of insulating materials 112 and the plurality of pillars 113, A plurality of first conductive materials 213 to 293 extending along one direction are provided.

Drains 320 are provided on the plurality of pillars 113, respectively. Illustratively, drains 320 will be silicon materials doped with a second type. For example, the drains 320 may be n-type doped silicon materials. Hereinafter, it is assumed that the drains 320 include n type silicon. However, the drains 320 are not limited to including n-type silicon. Illustratively, the width of each drain 320 may be greater than the width of the corresponding pillar 113. For example, each drain 320 may be provided in the form of a pad on the upper surface of the corresponding pillar 113.

On the drains 320, second conductive materials 331 - 333 are provided extending in a third direction. The second conductive materials 331 to 333 are sequentially disposed along the first direction. Each of the second conductive materials 331 to 333 is connected to the drains 320 of the corresponding region. Illustratively, the drains 320 and the second conductive material 333 extending in the third direction can each be connected through contact plugs. Illustratively, the second conductive materials 331-333 will be metal materials. Illustratively, the second conductive materials 331 - 333 will be conductive materials such as polysilicon or the like.

3 and 4, each pillar 113 forms a string together with an adjacent region of the insulating film 116 and an adjacent one of the plurality of first conductive lines 211 to 291, 212 to 292, and 213 to 293 . For example, each pillar 113 forms a NAND string NS together with an adjacent region of the insulating film 116 and an adjacent region out of the first conductive lines 211 to 291, 212 to 292, and 213 to 293. The NAND string NS includes a plurality of transistor structures TS. The transistor structure TS is described in more detail with reference to Fig.

5 is a cross-sectional view showing the transistor structure (TS) of Fig. Referring to FIGS. 3 to 5, the insulating film 116 includes first to third sub-insulating films 117, 118, and 119.

The surface layer 114 of pillar 113 containing p-type silicon will operate as a body. The first sub-insulating film 117 adjacent to the pillar 113 will act as a tunneling insulating film. For example, the first sub-insulating film 117 adjacent to the pillar 113 may include a thermally-oxidized film.

The second sub-insulating film 118 will act as a charge storage film. For example, the second sub-insulating film 118 will act as a charge trapping layer. For example, the second sub-insulating film 118 may include a nitride film or a metal oxide film (for example, an aluminum oxide film, a hafnium oxide film, or the like).

The third sub-insulating film 119 adjacent to the first conductive material 233 will function as a blocking insulating film. Illustratively, the first sub-insulating layer 119 adjacent to the first conductive material 233 extended in the first direction may be formed as a single layer or a multilayer. The third sub-insulating layer 119 may be a high-k dielectric layer having a dielectric constant higher than that of the first and second sub-insulating layers 117 and 118 (for example, an aluminum oxide layer, a hafnium oxide layer, or the like).

The first conductive material 233 will act as a gate (or control gate). That is, the first conductive material 233 acting as a gate (or control gate), the third sub-insulating film 119 acting as a blocking insulating film, the second sub-insulating film 118 acting as a charge storage film, and the tunneling insulating film The first sub-insulating layer 117, and the surface layer 114 including the p-type silicon that functions as a body will form a transistor (or a memory cell transistor structure). Illustratively, the first to third sub-insulating layers 117 to 119 may constitute an ONO (oxide-nitride-oxide) layer. In the following, the surface layer 114 of the pillar 113 containing p-type silicon is defined as operating in the body in the second direction.

The memory block BLKi includes a plurality of pillars 113. That is, the memory block BLKi includes a plurality of NAND strings NS. More specifically, the memory block BLKi includes a plurality of NAND strings NS extending in a second direction (or a direction perpendicular to the substrate).

Each NAND string NS includes a plurality of transistor structures TS disposed along a second direction. At least one of the plurality of transistor structures TS of each NAND string NS operates as a string selection transistor (SST). At least one of the plurality of transistor structures TS of each NAND string NS operates as a ground selection transistor GST.

The gates (or control gates) correspond to the first conductive materials 211-291, 212-292, 213-293 extended in the first direction. That is, the gates (or control gates) extend in a first direction to form word lines and at least two select lines (e.g., at least one string select line SSL and at least one ground select line GSL).

The second conductive materials 331 to 333 extended in the third direction are connected to one end of the NAND strings NS. Illustratively, the second conductive materials 331-333 extending in the third direction act as bit lines BL. That is, in one memory block BLKi, a plurality of NAND strings are connected to one bit line BL.

Second type doped regions 311-314 extending in a first direction are provided at the other end of the NAND strings. The second type doped regions 311-314 extending in the first direction act as a common source line (CSL).

In summary, the memory block BLKi includes a plurality of NAND strings extended in a direction perpendicular to the substrate 111 (second direction), and a plurality of NAND strings NS are formed on one bit line BL And operates as a connected NAND flash memory block (for example, charge capturing type).

3 to 5, it has been described that the first conductive lines 211 to 291, 212 to 292, and 213 to 293 are provided in nine layers. However, the first conductive lines 211 to 291, 212 to 292, and 213 to 293 are not limited to being provided in nine layers. For example, the first conductive lines may be provided in at least eight layers forming memory cells and at least two layers forming select transistors. The first conductive lines may be provided in at least sixteen layers constituting memory cells and at least two layers forming select transistors. Also, the first conductive lines may be provided in a plurality of layers forming memory cells and in at least two layers forming select transistors. For example, the first conductive lines may also be provided in the layer that forms the dummy memory cells.

3 to 5, it has been described that three NAND strings NS are connected to one bit line BL. However, it is not limited that three NAND strings NS are connected to one bit line BL. Illustratively, in the memory block BLKi, m NAND strings NS may be connected to one bit line BL. At this time, the number of the first conductive materials 211 to 291, 212 to 292, and 213 to 293 extending in the first direction by the number of the NAND strings NS connected to one bit line BL, The number of doping regions 311 to 314 operating as the source line CSL will also be adjusted.

3 to 5, it has been described that three NAND strings NS are connected to one first conductive material extending in a first direction. However, it is not limited that three NAND strings NS are connected to one first conductive material. For example, to one first conductive material, n NAND strings NS may be connected. At this time, the number of bit lines 331 to 333 will also be adjusted by the number of NAND strings NS connected to one first conductive material.

As described with reference to FIGS. 3 to 5, the cross-sectional area of the pillar 113 along the first and third directions can be reduced as it is closer to the substrate 111. For example, the cross-sectional area along the first and third directions of the pillar 113 may vary due to process characteristics or errors.

Illustratively, the pillar 113 is formed by providing materials such as a silicon material and an insulating material in a hole formed by etching. As the depth to be etched increases, the area along the first and third directions of the holes formed by the etching may decrease. That is, the cross-sectional area of the pillar 113 along the first and third directions can be reduced as it is closer to the substrate 111.

Fig. 6 is a circuit diagram showing an equivalent circuit BLKi_1 according to the first embodiment of the memory block BLKi described with reference to Figs. 3 to 5. Fig. Referring to Figs. 3-6, NAND strings NS11-NS31 are provided between the first bit line BL1 and the common source line CSL. NAND strings NS12, NS22, and NS32 are provided between the second bit line BL2 and the common source line CSL. Between the third bit line BL3 and the common source line CSL, NAND strings NS13, NS23, NS33 are provided. The first to third bit lines BL1 to BL3 correspond to the second conductive materials 331 to 333 extended in the third direction, respectively.

The string selection transistor SST of each NAND string NS is connected to the corresponding bit line BL. The ground selection transistor GST of each NAND string NS is connected to the common source line CSL. Memory cells MC are provided between the string selection transistor SST and the ground selection transistor GST of each NAND string NS.

In the following, NAND strings NS are defined in units of rows and columns. The NAND strings NS connected in common to one bit line form one column. For example, the NAND strings NS11 to NS31 connected to the first bit line BL1 will correspond to the first column. NAND strings NS12 to NS32 connected to the second bit line BL2 will correspond to the second column. The NAND strings NS13 to NS33 connected to the third bit line BL3 will correspond to the third column.

NAND strings NS connected to one string select line SSL form one row. For example, the NAND strings NS11 to NS13 connected to the first string selection line SSL1 form a first row. The NAND strings NS21 to NS23 connected to the second string selection line SSL2 form a second row. The NAND strings NS31 to NS33 connected to the third string selection line SSL3 form the third row.

For each NAND string NS, the height is defined. Illustratively, in each NAND string NS, the height of the ground selection transistor GST is defined as one. The height of the memory cell MC1 adjacent to the ground selection transistor GST is defined as two. The height of the string selection transistor (SST) is defined as 9. The height of the memory cell MC7 adjacent to the string selection transistor SST is defined as eight. As the distance between the memory cell MC and the ground selection transistor GST increases, the height of the memory cell MC increases. That is, the first to seventh memory cells MC1 to MC7 are defined to have the second to eighth heights, respectively.

Each NAND string NS shares a ground selection line GSL. The ground selection line GSL will correspond to the first conductive lines 211 to 213 having the first height. That is, it can be understood that the ground selection transistors GST also have a first height.

The memory cells MC at the same height of the NAND strings NS in the same row share the word line WL. The word lines WL of the NAND strings NS having the same height and corresponding to the different rows are connected in common. That is, the memory cells MC of the same height share the word line WL.

First conductive lines 221 to 223 having a second height are connected in common to form a first word line WL1. First conductive lines 231 to 233 having a third height are connected in common to form a second word line WL2. The first conductive lines 241 to 243 having a fourth height are connected in common to form a third word line WL3. The first conductive lines 251 to 253 having a fifth height are connected in common to form a fourth word line WL4. The first conductive lines 261 to 263 having a sixth height are connected in common to form a fifth word line WL5. The first conductive lines 271 to 273 having a seventh height are connected in common to form a sixth word line WL6. The first conductive lines 281 to 283 having an eighth height are connected in common to form a seventh word line WL7.

The NAND strings NS in the same row share a string selection line (SSL). The NAND strings NS in the different rows are connected to the different string selection lines SSL1, SSL2 and SSL3, respectively. The first through third string selection lines SSL1 through SSL3 may correspond to the first conductive lines 291 through 293 each having a ninth height.

Hereinafter, the first string selection transistors SST1 are defined as string selection transistors SST connected to the first string selection line SSL1. The second string selection transistors SST2 are defined as string selection transistors SST connected to the second string selection line SSL2. The third string selection transistors SST3 are defined as string selection transistors SST connected to the third string selection line SSL3.

The common source line CSL is connected in common to the NAND strings NS. For example, in the active region on the substrate 111, the first to fourth doped regions 311 to 314 may be connected to each other to form a common source line CSL.

As shown in FIG. 6, the word lines WL of the same height are connected in common. Thus, when the word line WL of a particular height is selected, all of the NAND strings NS connected to the selected word line WL will be selected.

NAND strings NS in different rows are connected to different string select lines SSL. Thus, by selecting and deselecting the string selection lines SSL1 to SSL3, the NAND strings NS of unselected rows among the NAND strings NS connected to the same word line WL are separated from the corresponding bit lines And the NAND strings NS of the selected row may be connected to the corresponding bit line.

Illustratively, during program and read operations, one of the string selection lines SSL1 through SSL3 will be selected. That is, the program and read operations will be performed in units of rows of the NAND strings NS11 to NS13, NS21 to NS23, NS31 to NS33.

Illustratively, during a program and read operation, a select voltage is applied to the selected word line of the selected row and a non-selected voltage is applied to the unselected word lines. For example, the select voltage may be the program voltage Vpgm or the selected read voltage Vrd. For example, the unselected voltage may be a pass voltage (Vpass) or an unselected read voltage (Vread). That is, the program and read operations will be performed in word line units of selected rows of NAND strings (NS11 to NS13, NS21 to NS23, NS31 to NS33).

FIG. 7 is an exemplary diagram illustrating a rising slope of drive signals in a general case.

As described with reference to FIGS. 3 to 5, the cross-sectional area of the pillar 113 along the first and third directions decreases as it is closer to the substrate 111 due to process characteristics or errors. For example, the cross-sectional area along the first and third directions of the pillar 113 corresponding to the second height is smaller than the cross-sectional area along the first and third directions of the pillar 113 corresponding to the eighth height.

The reduction of the cross-sectional area of the pillar 113 along the first and third directions means an increase in the cross-sectional area of the first conductive lines in the second and third directions. That is, the cross-sectional area along the second and third directions of the word lines increases as the distance from the substrate 111 increases. For example, as shown in FIG. 4, the cross-sectional area along the second and third directions of the first conductive lines 221 to 223 having the second height is greater than that of the first conductive lines 281 283 in the second and third directions. 6, the cross-sectional area along the second and third directions of the first word line WL1 having the second height is greater than the cross-sectional area along the second and third directions of the seventh word line WL7 having the eighth height . Therefore, since the resistance of the word line is inversely proportional to the cross-sectional area, the resistance of the first word line WL1 is smaller than that of the seventh word line WL7.

As described above, the word line resistance of a memory cell array having a three-dimensional structure is smaller the closer it is to the substrate. Therefore, in the case of a general nonvolatile memory device, the driving signal provided to the word line close to the substrate has a rising sled larger than the driving signal applied to the substrate and the far word line. The difference in the slope of the rising slope may cause a decrease in the read margin depending on the program speed difference.

For example, referring to FIG. 7, during a program operation, the first drive signal DS < 1 > provided to the first word line WL1 is raised to the pass voltage Vpass, And the seventh driving signal DS &lt; 7 &gt; provided to the seventh word line WL7 has a rising slope of '?' While increasing to the pass voltage Vpass. That is, the rising ramp of the first driving signal DS <1> is larger than the rising ramp DS <7> of the seventh driving signal while rising to the pass voltage Vpass.

For example, while the first driving signal DS <1> and the seventh driving signal DS <7> are rising from the pass voltage Vpass to the program voltage Vpgm, And has a lyophilization slope of. That is, while rising to the program voltage Vpgm, the rising ramp of the first driving signal DS <1> is larger than the rising ramp DS <7> of the seventh driving signal.

Thus, when the memory cells connected to the first word line WL1 and the seventh word line WL7 are respectively programmed, the memory cells connected to the first word line WL1 are connected to the memory cells connected to the seventh word line WL7 Is programmed faster. The difference in program speed of these memory cells causes a decrease in the read margin.

In order to prevent such a problem, the nonvolatile memory device 100 according to the embodiment of the present invention adjusts a rising slope of driving signals using a ramper 132 (see FIG. 1). For example, the nonvolatile memory device 100 uses the ramper 132 to cause the rising ramp "γ" of the first drive signal DS <1> to be the rising ramp of the seventh drive signal DS <7> the rising slope of the first driving signal DS &lt; 1 &gt; The nonvolatile memory device 100 also uses the rampers 132 so that the rising ramp '?' Of the first driving signal DS <1> is the same as the rising ramp of the seventh driving signal DS <7> The second driving signal DS < RTI ID = 0.0 > 1 < / RTI > Hereinafter, the word line driver 131 and the ramper 132 according to the embodiment of the present invention will be described in more detail.

8 is a block diagram showing the word line driver 131 and the ramper 132 of FIG. Referring to FIG. 8, the word line driver 131 includes a decoding block 131_a and first to seventh driving blocks 131_b1 to 131_b7. The ramper 132 includes first to seventh ramping blocks 132_1 to 132_7.

The decoding block 131_a receives the row address RAi. The decoding block 131_a decodes the received row address RAi and generates decoded row addresses DRAi. The decoding block 131_a transfers the decoded row addresses DRAi to the corresponding one of the first to seventh driving blocks 131_b1 to 131_b7.

The first to seventh driving blocks 131_b1 to 131_b7 receive the decoded row addresses DRAi from the decoding block 131_a. The first to seventh driving blocks 131_b1 to 131_b7 receive the program voltage Vpgm and the pass voltage Vpass from the high voltage generating circuit 120 (see FIG. 1). The first to seventh driving blocks 131_b1 to 131_b7 output either the program voltage Vpgm or the pass voltage Vpass in response to the decoded row addresses DRAi. Each driving block is described in more detail in FIG. 9 below.

The first to seventh ramping blocks 132_1 to 132_7 are connected to the first to seventh driving blocks 131_b1 to 131_b7, respectively. The first to seventh ramping blocks 132_1 to 132_7 receive the program voltage Vpgm or the pass voltage Vpass from the first to seventh driving blocks 131_b1 to 131_b7, respectively. The first to seventh ramping blocks 132_1 to 132_7 generate the first to seventh drive signals DS <1> to DS <7>, respectively.

The first to seventh ramping blocks 132_1 to 132_7 constantly control the rising ramp of the first to seventh drive signals DS <1> to DS <7> using ramping. That is, the first to seventh ramping blocks 132_1 to 132_7 generate the first to seventh drive signals DS <1> to DS <7> having a predetermined rising slope. Here, ramping means a step-up voltage generating function.

3 to 7, since the cross-sectional area of the first word line WL1 in the second and third directions is larger than that of the seventh word line, the rising of the first driving signal DS < 1 > The slop is larger than the rising slope of the seventh drive signal DS < 7 >. In this case, the first ramping block 132_1 adjusts the first driving signal DS <1> so as to have the same rising ramp as the seventh driving signal DS <7>. Likewise, the second to sixth ramping blocks 132_2 to 132_6 are provided for the second to sixth drive signals DS <2> to DS <6> to have the same rising ramp as the seventh drive signal DS < Adjust the rising slope. Each ramping block is described in more detail in FIGS. 10 and 11 below.

FIG. 9 is a view for explaining the driving block of FIG. 8 in more detail. In FIG. 9, a first driving block 131_1b and a first ramping block 132_1 connected to the first driving block 131_1 are illustrated. Referring to FIG. 9, the first driving block 131_b1 includes a first switch S / W1 and a second switch S / W2.

The first switch S / W1 receives the pass voltage Vpass and the first activation signal EN_1 from the high voltage generation circuit 120 (see FIG. 1) and the control logic 160 (see FIG. 1). The second switch S / W2 receives the program voltage Vpgm and the second activation signal EN_2 from the high voltage generation circuit 120 and the control logic 160, respectively. The first switch S / W1 and the second switch S / W2 are turned on at any one of the pass voltage Vpass and the program voltage Vpgm in response to the decoded row address DRAi1 provided from the decoding block 131_a As shown in FIG.

The first ramping block 132_1 receives the pass voltage Vpass or the program voltage Vpgm. The first ramping block 132_1 generates a first driving signal DS <1> corresponding to the received voltage level.

10 is a view for explaining the ramping block of FIG. 8 in more detail. In Fig. 10, a first ramping block 132_1 is shown as an example. For convenience of explanation, it is assumed that the first ramping block 132_1 receives the program voltage Vpgm from the first driving block 131_b1. Referring to FIG. 10, the first ramping block 132_1 includes first to sixth switches S / W1 to S / W6 and first to eleventh transistors NM1 to NM11.

The first to sixth switches S / W1 to S / W6 are each supplied with a high voltage Vpp. The first to sixth switches S / W1 to S / W6 receive the first to sixth lamp activation signals Ramp_EN_1 to Ramp_EN_6, respectively. The first to sixth switches S / W1 to S / W6 transmit the high voltage Vpp to the gates of the corresponding sixth to eleventh transistors NM6 to NM11 in response to the corresponding lamp activation signal.

The first to fifth transistors NM1 to NM5 are connected in series. That is, the gates and drains of the first to fourth transistors NM1 to NM4 are connected to the sources of the second to fifth transistors NM2 to NM5, respectively. The source of the first transistor NM1 is connected to the drain of the sixth transistor NM6 and the drain of the fifth transistor NM5 is connected to the program voltage Vpgm.

The gates of the sixth to eleventh transistors NM6 to NM11 are connected to the first to sixth switches S / W1 to S / W6, respectively. The drains of the sixth to eleventh transistors NM6 to NM11 are connected to the sources of the first to fifth transistors NM1 to NM5, respectively. The sources of the sixth to eleventh transistors NM6 to NM11 are connected to the same node and output the first driving signal DS < 1 >.

11 is a timing chart showing the operation of the first ramping block 132_1 of FIG. 11, it is assumed that the voltage level of the first driving signal DS <1> rises from the pass voltage Vpass to the program voltage Vpmg.

Referring to FIGS. 10 and 11, first, the first lamp activation signal Ramp_EN_1 is activated. The first switch S / W1 transfers the high voltage Vpp to the gate of the sixth transistor NM6 in response to the activation of the first lamp activation signal Ramp_EN_1. Thus, the sixth transistor NM6 is turned on. The drain of the sixth transistor NM6 is connected to the drain of the first transistor NM1.
Therefore, a voltage level of the program voltage Vpgm that is lowered by the threshold voltage of the first to fifth transistors NM1 to NM5 is output to the source of the sixth transistor NM6. That is, the voltage level of the first driving signal DS <1> is a voltage level lowered by the threshold voltage of the first to fifth transistors NM1 to NM5 at the program voltage Vpgm. In this case, the voltage level of the first driving signal DS < 1 > may be referred to as a first ramping level.

Thereafter, when the second ramp-up signal Ramp_EN_2 is activated, the seventh transistor NM7 is turned on and the voltage of the program voltage Vpgm is increased by the threshold voltage of the second through fifth transistors NM2-NM5 The voltage level is output to the source of the seventh transistor NM7. That is, the voltage level of the first driving signal DS <1> is the voltage level that is voltage-enhanced by the threshold voltage of the second to fifth transistors NM2 to NM5 in the program voltage Vpgm. In this case, the voltage level of the first driving signal DS < 1 > may be referred to as a second ramping level (second ramping level). The second ramping level is higher than the first ramping level by the threshold voltage of the first transistor NM1.

In the same manner, when the third to sixth activation signals Ramp_EN_3 to Ramp_EN_6 are sequentially activated, the voltage level of the first driving signal DS <1> is lower than the threshold voltage of the second to fifth transistors NM2 to NM5 . As a result, the voltage level of the first drive signal DS < 1 > is stepped up to the program voltage Vpgm level.

In the embodiment of the present invention, the rising slope of the first driving signal DS < 1 > may be adjusted in the same manner as the rising slope of the reference driving signal. For example, the rising slope of the first driving signal DS < 1 > may be adjusted to be equal to the rising slope of the reference driving signal by adjusting the time t1 to t6 at which each of the lamp activation signals transits. As another example, by varying the number of transistors of the first ramping block 132_1 and the number of transistors of the seventh ramping block 132_7, the rising ramp of the first driving signal DS <1> . &Lt; / RTI &gt;

7), since the resistance of the seventh word line is greater than that of one word line, the rising ramp of the seventh driving signal DS <7> is the same as that of the first driving signal DS <1> Lt; / RTI &gt; It is assumed that the seventh drive signal DS <7> is set as the reference drive signal since the rising slope of the seventh drive signal DS <7> is smaller than the first drive signal DS <1>. It is assumed that the seventh ramping block 132_7 has the same structure as the first ramping block 132_1.

In this case, the time difference between the transition timings t1 to t6 of the lamp activation signals of the first ramping block 132_1 is set longer than the time difference between the transition timings of the lamp activation signals of the seventh ramping block 13_7 . Therefore, the rising slope of the first driving signal DS < 1 > is relatively lowered. As a result, the rising slope of the first driving signal DS < 1 > may be adjusted in the same manner as the rising slope of the seventh driving signal DS < 7 >.

12 and 13 show the first driving signal DS < 1 > in which the rising ramp is adjusted by the first ramping block 132_1. 12, the rising ramp of the first driving signal DS <1> during the rising to the pass voltage Vpass is the rising ramp of the first driving signal DS <1> when the ramp is not performed, As shown in FIG. The rising ramp of the first driving signal DS < 1 > while rising from the pass voltage Vpass to the program voltage Vpgm is a rising ramp of the first driving signal DS < 1 > As shown in FIG.
13, while the rising ramp of the first driving signal DS <1> rises to the path voltage Vpass and the program voltage Vpgm, the rising ramp of the first driving signal DS <1> Can be adjusted to have a slop. That is, the rising slope of the first driving signal DS <1> may be adjusted to be the same as the rising slope of the seventh driving signal DS <7>.

Likewise, the rising slopes of the second to sixth driving signals DS < 2 > to DS < 6 > can be adjusted in the same manner as the rising slopes of the seventh driving signal DS & This is similar to that described above with reference to Figs. 9 to 13, and a detailed description thereof will be omitted.

As described above, the nonvolatile memory device according to the embodiment of the present invention can uniformly adjust the rising ramp of the driving signals applied to the word lines by using ramping. Therefore, a reduction in the read margin due to the difference in program speed can be prevented.

12 and 13, the rising slope '?' And the rising slope '?' Are shown to have different values, respectively. However, it should be understood that this is an example. For example, the nonvolatile memory device according to the embodiment of the present invention can control the driving signals so that the rising slope '?' And the rising slope '?' Have the same value.
In FIGS. 8 to 13, the first to seventh drive signals DS <1> to DS <7> are all ramped. However, it should be understood that this is an example. For example, only the driving signal adjacent to the substrate among the first to seventh driving signals DS < 1 > to DS < 7 > This will be described in more detail in Figs. 14 and 15 below.

14 is a block diagram illustrating a non-volatile memory device 200 according to another embodiment of the present invention. The non-volatile memory device 200 of FIG. 14 is similar to the non-volatile memory device 100 of FIG. 1 except that the word line driver 231 includes a ramper 232. That is, while the non-volatile memory device 100 of FIG. 1 ramps all the driving signals, the non-volatile memory device 200 of FIG. 14 ramps only some of the driving signals.

FIG. 15 is a diagram for explaining the word line driver 231 of FIG. 14 in more detail. Referring to FIG. 15, the word line driver 231 includes a decoding block 231_a, first to seventh driving blocks 231_b1 to 231_b7, and a ramper 232. The ramper 232 includes first and second ramping blocks 132_1 and 132_2. The word line driver 231 and the ramper 232 of FIG. 15 are similar to the word line driver 131 and the ramper 132 of FIG. 8, except for the connection relationship between the driving block and the ramping block. Therefore, the difference from FIG. 8 will be mainly described below.

Referring to FIG. 15, only the first and second driving blocks 231_b1 and 231_b2 among the first to seventh driving blocks 231_b1 to 231_b7 are connected to the first and second ramping blocks 232_1 and 232_2, respectively. That is, although the rising slopes of the first and second driving signals DS <1> and DS <2> are adjusted to the rising slope of the reference driving signal, the third to seventh driving signals DS < 7>) is output without adjustment of the rising slope. Here, the reference drive signal may be any one of the third to seventh drive signals DS <3> to DS <7>.

4 and 8, the cross-sectional area along the second and third directions of the word lines is larger toward the substrate 111 (see FIG. 3). That is, the resistance of the word lines is smaller the closer to the substrate 111. Therefore, in a general case, the rising slope of the driving signal applied to the word line close to the substrate 111 is larger than the driving signal applied to the substrate and the far word line. In this case, the reduction in the read margin due to the program speed difference may be mainly caused by the drive signal applied to the word line close to the substrate 111. [

15, only the rising ramp of the first and second driving signals DS < 1 >, DS < 2 > provided on the word lines close to the substrate 111 is the rising ramp of the reference driving signal Lt; / RTI &gt; That is, only the first and second driving blocks 231_b1 and 231_b2 among the first to seventh driving blocks 231_b1 to 231_b7 can be implemented so that the first and second ramping blocks 232_1 and 232_2 are connected. Therefore, a reduction in the read margin due to the difference in program speed can be prevented.

15, the rising slopes of the first and second driving signals DS <1> and DS <2> of the first to seventh driving signals DS <1> to DS <7> are adjusted. However, it should be understood that this is an example. For example, the nonvolatile memory device according to the embodiment of the present invention may include only the rising sled of the first driving signal DS <1> among the first to seventh driving signals DS <1> to DS <7> Can be implemented.

3 to 15, the materials between the bit line and the substrate of the memory block BLKi of FIG. 2 are described as being penetrated in a second direction by a single pillar. However, it should be understood that this is an example. For example, the memory block may be implemented so that there are at least two pillars connected in series between the bit line and the substrate. This will be described in more detail in Figs. 16 to 18 below.

16 is a perspective view showing a modified example BLKi 'of the memory block BLKi of FIG. 17 is a cross-sectional view taken along line II-II 'of the memory block BLKi' of FIG. The memory block BLKi_2 is the same as the memory described with reference to Figs. 4 to 21 except that one pillar of the memory block BLKi 'includes a first subpillar 113a and a second subpillar 113b. Block BLKi. Therefore, redundant description of the same configuration is omitted.

16 and 17, a first sub-pillar 113a is provided on a substrate 111. The first sub- Illustratively, the surface layer 114a of the first sub-pillar 113a comprises a p-type silicon material. For example, the surface layer 114a of the first sub-pillar 113a operates as a body in the second direction. The inner layer 115a of the first sub-pillar 113a is made of an insulating material.

And a second sub-pillar 113b is provided on the first sub-pillar 113a. Illustratively, the surface layer 114b of the second sub-pillar 113b comprises a p-type silicon material. For example, the surface layer 114b of the second sub-pillar 113b operates as a body in the second direction. The inner layer 115b of the second sub-pillar 113b is made of an insulating material.

Illustratively, the surface layer 114a of the first sub-pillar 113a and the surface layer 114b of the second sub-pillar 113b are connected. 16 and 17, the surface layer 114a of the first sub-pillar 113a and the surface layer 114b of the second sub-pillar 113b are p-type silicon pads (SIP), for example, Lt; / RTI &gt;

18 is a circuit diagram showing an equivalent circuit (BLKi'_1) of the memory block BLKi 'described with reference to Figs. 16 and 17. Fig. Compared with the memory block BLKi of FIG. 6, a dummy memory cell BLKi'_1 is provided between the first to third word lines WL1 to WL3 and the fourth to sixth word lines WL4 to WL6, A word line DWL is provided.

The memory cells MC1 to MC3 of the second to fourth heights are connected in common to the first to third word lines WL1 to WL3, respectively. At the fifth height, dummy memory cells DMC are provided. The dummy memory cells DMC of the fifth height are connected in common to the dummy word lines DWL. The memory cells MC4 to MC6 of the sixth to eighth heights are connected in common to the fourth to sixth word lines WL4 to WL6, respectively.

Illustratively, the first conductive lines at a height corresponding to the silicon pad (SIP) are connected in common to form a dummy word line DWL. In FIG. 18, the first conductive lines 251 to 253 at the fifth height (see FIG. 17) are shown as forming a dummy word line DWL. However, the height of the first conductive lines forming the dummy word line DWL is not limited.

16 to 18, the sectional areas of the word lines corresponding to the first and second sub pillars 113a and 113b along the second and third directions are larger as they are closer to the substrate 111, respectively. The cross-sectional areas of the first to third word lines WL1 to WL3 corresponding to the first sub-pillar 113a in the second and third directions are the same as those of the fourth to sixth word lines Lines WL4 to WL6.

Specifically, the cross-sectional area along the second and third directions of the first word line WL1 is larger than the second and third word lines WL2 and WL3 and is equal to or similar to the fourth word line WL4 . The cross sectional area along the second and third directions of the second word line WL2 is larger than the third word line WL3 and will be the same as or similar to the fifth word line WL5. The cross sectional area along the second and third directions of the third word line WL3 will be the same as or similar to the sixth word line WL6.

Since the cross-sectional area of the first and fourth word lines WL1 and WL4 is the largest, in general, the rising slopes of the driving signals corresponding to the first and fourth word lines WL1 and WL4 correspond to different word lines Is larger than the rising slope of the driving signals. Therefore, the reduction of the read margin due to the program speed difference can be caused mainly by the drive signals applied to the first and fourth word lines WL1 and WL4. In order to prevent this, the nonvolatile memory device according to the embodiment of the present invention may adjust the rising slopes of the driving signals corresponding to the first and fourth word lines WL1 and WL4. This will be described in more detail with reference to Fig. 19 below.

19 is a block diagram showing a word line driver 331 for providing drive signals to the memory blocks of Figs. 16-18. 19, the word line driver 331 includes a decoding block 331_a, a dummy driving block 331_b0, first to sixth driving blocks 331_b1 to 331_b6, first and second ramping blocks 332_1, 332_2). The first and second ramping blocks 332_1 and 332_2 may be referred to as a ramper.

The word line driver 331 of FIG. 19 is similar to the word line driver 221 of FIG. 15 except for the connection relationship between the driving block and the ramping block. Therefore, the difference from FIG. 15 will be mainly described below.

Referring to FIG. 19, the first to third drive signals DS <1> to DS <3> are provided to the first to third word lines WL1 to WL3 (see FIG. 18). The fourth to sixth drive signals DS <4> to DS <6> are provided to the fourth to sixth word lines (WL4 to WL6, see FIG. 18). The dummy driving signal DS < D > is provided to the dummy word line DWL (see Fig. 18). The first to third word lines WL1 to WL3 may be referred to as a first word line group. The fourth to sixth word lines (WL4 to WL6) may be referred to as a second word line group. Only the first and fourth driving blocks 331_b1 and 331_b4 of the first to sixth driving blocks 331_b1 to 331_b6 are connected to the first and second ramping blocks 332_1 and 332_2, respectively.

16 to 18, since the cross-sectional area of the first word line WL1 of the first word line group is the largest, in general, the rising slope of the first drive signal DS < 1 > . Likewise, since the cross-sectional area of the fourth word line WL4 of the second word line group is the largest, in general, the rising slope of the fourth drive signal DS <4> is greatest.

Thus, as shown in Fig. 19, the word line driver 331 can be implemented to adjust the rising slopes of the first and fourth driving signals DS < 1 >, DS < 4 >. By adjusting the rising slopes of the first and fourth driving signals DS < 1 >, DS < 4 >, the reduction of the reading margin due to the program speed difference can be prevented.

19, the rising slopes of the first and fourth driving signals DS <1> and DS <4> among the first to sixth driving signals DS <1> to DS <6> are adjusted. However, it is to be understood that the present invention is not limited thereto and the technical idea of the present invention is not limited thereto.

1 to 19, the nonvolatile memory device according to the embodiment of the present invention is described as adjusting the rising ramp of the program voltage and the pass voltage. However, it should be understood that this is an example. For example, a non-volatile memory device according to an embodiment of the present invention may be used to uniformly adjust the rising ramp of the voltages provided to the word lines during a read operation. This will be explained in more detail with reference to Figs. 20 to 22 below.

FIGS. 20 to 22 are diagrams for explaining read disturbance when the rising slope is not adjusted. FIG.

In Fig. 20, the scattering of the threshold voltage of the memory cell MC is shown. Illustratively, it is assumed that the memory cell MC has a distribution of threshold voltages corresponding to four logic states (E, P1, P2, P3). That is, it is assumed that the memory cell MC stores 2 bits. However, the memory cell MC is not limited to storing two bits.

FIG. 21 shows a read operation in the case where the rising slope is not adjusted. For convenience of explanation, it is assumed that the rising slopes of the driving signals provided to the first to seventh word lines (WL1 to WL7) become larger toward the substrate. That is, it is assumed that the memory blocks including the first to seventh word lines (WL1 to WL7) have the same structure as the memory blocks shown in Figs. 3 to 6. It is assumed that a read operation to the second word line WL2 is performed.

In FIG. 22, the channel voltage of one NAND string of NAND strings corresponding to the selected string line (Selected SSL) in FIG. 21 is shown. Specifically, the channel voltage of the NAND string at the sixth time (t6, see Fig. 21) is shown in Fig. The first to seventh memory cells MC1 to MC7 correspond to the memory cells belonging to the same NAND string among the memory cells of the first to seventh word lines WL1 to WL7, respectively. For convenience of explanation, it is assumed that the third memory cell MC3 has a threshold voltage corresponding to the logic state P3. It is assumed that the first, second, and fourth to seventh memory cells MC1, MC2, MC4 to MC7 have threshold voltages corresponding to the erase state E, respectively.

20 to 22, the bit line BL is precharged to the bit line precharge voltage VBL. Thereafter, a string selection voltage VSSL and a ground selection voltage VGSL are provided to the selected string selection line (Selected SSL) and the ground selection line GSL, respectively. Also, the selected second word line WL2 is provided with the first selected read voltage Vrd1, and the unselected word lines WL1, WL3 to WL7 are provided with the unselected read voltage Vread.

The first to seventh drive signals DS < 1 > to DS < 7 > provided to the first to seventh word lines WL1 to WL7 are sequentially And reaches the first selected read voltage Vrd1 level. In this case, since the memory cells MC1, MC2, and MC4 to MC7 except for the third memory cell MC3 have the threshold voltage of the erase state E, the memory cells MC1, MC2, MC4 to MC7 are sequentially . For example, the first memory cell MC1 is turned on at the earliest third time t3 as compared with the memory cells of other erase states, and the seventh memory cell MC7 is turned on And is turned on at the slow fifth time t5.

On the other hand, since the third memory cell MC3 has a threshold voltage corresponding to the logic state P3, the third memory cell MC3 receives the third driving signal DS < 3 > supplied to the third word line WL3 >) Is turned on, for example, when the unselected read voltage Vread is reached. Therefore, the third memory cell MC3 can be turned on at the sixth time t6 that is slowest than the other memory cells MC1, MC2, MC4 to MC7.

In this case, as shown in FIG. 22, the channel voltage of the NAND string including the first to seventh memory cells MC1 to MC7 can be divided around the third memory cell MC3. That is, at the sixth time t6, the third memory cell MC3 is turned off, and the other memory cells MC1, MC2, MC4 to MC7 are turned on, so that the channel voltage of the NAND string (Vss) and a bit line pre-charge voltage (VBL) at the center of the bit line MC3. This difference in channel voltage can cause read disturbance due to hot electron injection, which can lead to a decrease in read margin.

In order to prevent the above-described read disturbance, the nonvolatile memory device according to the embodiment of the present invention can uniformly adjust the rising slope of the selected read voltage Vrd and the unselected read voltage Vread. For example, the nonvolatile memory device according to the embodiment of the present invention can prevent the read disturbance by adjusting the transition points of the lamp activation signal. The construction and operation of the non-volatile memory device for preventing read disturb is similar to the non-volatile device described in Figs. 1 to 19 adjusts the rising ramp of the program voltage Vpgm and the pass voltage Vpass while the non-volatile memory device for preventing read disturbance adjusts the selected read voltage Vrd, And the rising ramp of the unselected read voltage (Vread). Therefore, a detailed description is omitted.

On the other hand, in Fig. 6, it is described that the memory block BLKi described with reference to Figs. 3 to 5 corresponds to the equivalent circuit BLK_1 according to the first embodiment. However, this is for illustrative purposes only, and the embodiment of the present invention is not limited thereto. Hereinafter, an equivalent circuit according to the second to fifth embodiments of the memory block BLKi described with reference to Figs. 3 to 5 will be described.

23 is a circuit diagram showing an equivalent circuit (BLKi_2) according to the second embodiment of the memory block BLKi described with reference to Figs. 3 to 5. Fig. Compared with the equivalent circuit described with reference to Fig. 6, the side transistors LTR are additionally provided in each NAND string NS of the memory block BLKi_3.

In each NAND string NS, the side transistor LTR is connected to the ground selection transistor GST and the common source line CSL. The gate (or control gate) of the lateral transistor LTR is connected to the ground selection line GSL together with the gate (or control gate) of the ground selection transistor GST.

As described with reference to Figs. 3 to 6, the first conductive lines 211, 212, and 213 having the first height correspond to the ground selection line GSL.

When a specific voltage is applied to the first conductive lines 211, 212, and 213 having the first height, a channel is formed in the region of the surface layer 114 adjacent to the first conductive lines 211, 212, and 213. That is, a channel is formed in the ground selection transistors GST. When a specific voltage is applied to the first conductive lines 211, 212, and 213, a channel is formed in the region of the substrate 111 adjacent to the first conductive lines 211, 212, and 213.

The first doped region 311 is connected to the channel formed on the substrate 111 by the voltage of the first conductive line 211. The channel generated in the substrate 111 by the voltage of the first conductive line 211 is connected to the channel generated in the surface layer 114 operating in the body in the second direction by the voltage of the first conductive line 211 .

Likewise, a channel is formed in the substrate 111 by the voltage of the first conductive lines 211, 212, and 213. The first to fourth doped regions 311 to 314 are formed by the voltages of the first conductive lines 211, 212 and 213 and the surface layers acting on the body in the second direction through the channel generated in the substrate 111 Respectively.

As described with reference to FIGS. 3 to 6, the first to fourth doped regions 311 to 314 are connected in common to form a common source line CSL. The channels of the common source line CSL and the memory cells MC1 through MC7 are electrically connected through a channel parallel to the substrate 111 and a channel perpendicular to the substrate 111 formed by the voltage of the ground selection line GSL .

That is, it can be understood that between the common source line CSL and the memory cells MC1 through MC3, a transistor driven by the ground selection line GSL and parallel to the substrate and parallel to the substrate is provided. A transistor perpendicular to the substrate can be understood as a ground selection transistor (GST), and a transistor parallel to the substrate can be understood as a side transistor (LTR).

Fig. 24 is a circuit diagram showing an equivalent circuit (BLKi_4) according to the third embodiment of the memory block BLKi described with reference to Figs. 3 to 5. Fig. Compared with the memory block BLKi_1 in Fig. 6, in each NAND string NS, two ground selection transistors GST1 and GST2 are provided between the memory cells MC1 to MC6 and the common source line CSL The ground selection transistors GST1 and GST2 are connected to one ground selection line GSL.

Fig. 25 is a circuit diagram showing an equivalent circuit (BLKi_5) according to the fourth embodiment of the memory block BLKi described with reference to Figs. 3 to 5. Fig. Compared with the memory block BLKi_3 in Fig. 24, in each NAND string NS, two string select transistors SST1 and SST2 can be provided between the memory cells MC1 to MC5 and the bit line BL have.

In the NAND strings of the same row, the string selection transistors (SST) of the same height will share a single string selection line (SSL). For example, in the first row of NAND strings NS11 to NS13, the first string selection transistors SST1 share the eleventh string selection line SSL11. And the second string selection transistors SST2 share the twenty-first string selection line SSL21.

In the NAND strings NS21 to NS23 of the second row, the first string selection transistors SST1 share the twelfth string selection line SSL12. And the second string selection transistors SST2 share the twenty second string selection line SSL22.

In the third row of NAND strings NS31 to NS33, the first string selection transistors SST1 share the thirteenth string selection line SSL13. And the second string selection transistors SST2 share the 23rd string selection line SSL23.

Fig. 26 is a circuit diagram showing an equivalent circuit (BLKi_6) according to the fifth embodiment of the memory block BLKi described with reference to Figs. 3 to 5. Fig. Compared with the memory block BLKi_4 in Fig. 25, the string selection lines SSL corresponding to the NAND strings NS in the same row are connected in common.

On the other hand, the equivalent circuit of the memory block BLKi 'described with reference to Figs. 22 and 23 can be implemented similarly to the circuit described in Figs. 23 to 26. Fig. Therefore, detailed description of equivalent circuits according to another embodiment of the memory block BLKi 'described with reference to Figs. 22 and 23 is omitted.

On the other hand, among the memory blocks of FIG. 2, the memory block described with reference to FIGS. 3 to 5 and the memory block described with reference to FIGS. 16 and 17 may be implemented in various modifications. Modifications of the memory block according to the embodiment of the present invention will be described below.

FIG. 27 is a perspective view showing a second embodiment (BLKj) of one of the memory blocks BLK1 to BLKz of FIG. 2. FIG. The sectional view of the memory block BLKj along the line I-I 'is the same as the sectional view shown in FIG.

Compared with the memory block BLKi in FIG. 3, in the memory block BLKj, the pillars 113 'will be provided in the form of a quadratic pole. In addition, insulating materials 101 are provided between pillars 113 'spaced apart a certain distance along the first direction. Illustratively, the insulating materials 101 will extend along the second direction to contact the substrate 111.

The first conductive materials 211 to 291, 212 to 292 and 213 to 293 described with reference to FIG. 3 are electrically connected to the first portions 211a to 291a, 212a to 292a, 213a to 293a And the second portions 211b to 291b, 212b to 292b, and 213b to 293b.

In the region on the first and second doped regions 311 and 312, each pillar 113 'includes first portions 211a through 291a of the first conductive materials and an insulating film 116 and one NAND string NS And the second portions 211b to 291b of the first conductive materials and the NAND string NS which is different from the insulating film 116 are formed.

In the region on the second and third doped regions 312 and 313, each pillar 113 'includes first portions 212a through 292a of the first conductive materials and an insulating film 116 and one NAND string NS And the second portions 212b to 292b of the first conductive materials and the NAND string NS other than the insulating film 116 are formed.

In the region on the third and fourth doping regions 313 and 314, each pillar 113 'includes first portions 213a to 293a of the first conductive materials and the insulating film 116 and one NAND string NS And the second portions 213b to 293b of the first conductive materials and the NAND string NS other than the insulating film 116 are formed.

That is, by separating the first and second portions 211a to 291a and 211b to 291b of the first conductive materials provided on both sides of each pillar 113 'using the insulating material 101, 113 'may form two NAND strings NS.

The memory block BLKj may be implemented with the equivalent circuits described with reference to FIG. 6 or FIGS. 23 to 26. The rising ramp of the program voltage Vpgm and the path voltage Vpass provided to the word lines of the memory block BLKj in the program operation will be constantly adjusted. Therefore, a reduction in the read margin due to the difference in program speed can be prevented. The rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKj in a read operation can be adjusted. Therefore, read disturbance can be prevented.

Fig. 28 is a perspective view showing a modified example (BLKj ') of the memory block BLKj of Fig. 27; A cross-sectional view taken along the line I-I 'of the memory block BLKj' is the same as the cross-sectional view shown in FIG. The memory block BLKj 'is the same as the memory block BLKj' described with reference to FIG. 27 except that one pillar of the memory block BLKj 'includes the first subpillar 113a and the second subpillar 113b. BLKj).

As described with reference to Figs. 17 and 18, one pillar in the memory block BLKj 'includes a first sub-pillar 113a and a second sub-pillar 113b. The first sub pillars 113a and the second sub pillars 113b will be configured as described with reference to FIGS. 17 and 18. FIG.

As described with reference to Fig. 18, one pillar 113 'forms two NAND strings NS. The first portions 211a-291a and the second portions 211b-291b, 212b-292b, 213b-293b of the first conductive materials are connected to ground select lines GSL, word lines WL, Corresponding to select lines (SSL). The word lines WL of the same height will be connected in common.

The memory block BLKj 'may be implemented with the equivalent circuits described with reference to FIG. 6 or FIGS. 23 to 26. The rising ramp of the program voltage Vpgm and the path voltage Vpass provided in the word lines of the memory block BLKj 'in the program operation will be constantly adjusted. Therefore, a reduction in the read margin due to the difference in program speed can be prevented. The rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKj 'in the read operation can be adjusted. Therefore, read disturbance can be prevented.

29 is a perspective view showing a third embodiment (BLKm) of one of the memory blocks BLK1 to BLKz of FIG. 30 is a cross-sectional view taken along line III-III 'of the memory block BLKm of FIG. 29; The memory block BLKm is the same as the memory block BLKi described with reference to FIGS. 3 to 5 except that the n-type doped region 315 forming the common source line CSL is provided in the form of a plate. . Illustratively, n-type doped region 315 may be provided as an n-type well.

The memory block BLKm may be implemented with the equivalent circuits described with reference to FIG. 6 or FIGS. 23 to 26. The rising ramp of the program voltage Vpgm and the path voltage Vpass provided to the word lines of the memory block BLKm in the program operation will be constantly adjusted. Therefore, a reduction in the read margin due to the difference in program speed can be prevented. The rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKm in a read operation can be adjusted. Therefore, read disturbance can be prevented.

31 is a perspective view showing a modification (BLKm ') of the memory block (BLKm) of FIG. 29; 32 is a cross-sectional view taken along the line IV-IV 'of the memory block BLKm' of FIG. 31; 29 and 30, except that one pillar of the memory block BLKm 'includes the first sub-pillar 113a and the second sub-pillar 113b, the memory block BLKm' Is the same as the memory block BLKm.

As described with reference to FIGS. 16 and 17, one pillar in the memory block BLKm 'includes a first sub-pillar 113a and a second sub-pillar 113b. The first sub-pillars 113a and the second sub-pillars 113b will be configured as described with reference to FIGS. 22 and 23. FIG.

29 and 30, an n-type doped region 315 forming a common source line CSL is provided in the form of a plate.

The memory block BLKm 'may be implemented with the equivalent circuits described with reference to FIG. 6 or FIGS. 23 to 26. The rising ramp of the program voltage Vpgm and the path voltage Vpass provided to the word lines of the memory block BLKm 'during the program operation will be constantly adjusted. Therefore, a reduction in the read margin due to the difference in program speed can be prevented. The rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKm 'in a read operation can be adjusted. Therefore, read disturbance can be prevented.

FIG. 33 is a perspective view showing a fourth embodiment (BLKn) of one of the memory blocks BLK1 to BLKz of FIG. 3; FIG. 34 is a cross-sectional view taken along the line V-V 'of the memory block BLKn of FIG. 33; 33 and 34, an n-type doped region 315 forming a common source line CSL is provided in the form of a plate as described with reference to FIGS. 29 and 30. FIG.

Compared with the memory block BLKi described with reference to FIGS. 3 and 4, the first conductive lines 221 'to 281' forming the word lines WL1 to WL7 are provided in the form of a plate do.

The surface layer 116 'of each pillar 113' includes an insulating film. The surface layer 116 'of the pillar 113' is configured to store data like the insulating film 116 described with reference to FIG. For example, the surface layer 116 'will include a tunneling insulating film, a charge storage film, and a blocking insulating film. The middle layer 114 'of the pillar 113' includes p-type silicon. The middle layer 114 'of the pillar 113' acts as a body in the second direction. The inner layer 115 'of the pillar 113' comprises an insulating material.

Illustratively, when the first conductive line 281 'of the eighth height is used as the string select line SSL, the first conductive line 281' of the eighth height is connected to the first conductive line 291 ').

The memory block BLKn may be implemented with the equivalent circuits described with reference to FIG. 6 or FIGS. 23 to 26. The rising ramp of the program voltage Vpgm and the path voltage Vpass provided to the word lines of the memory block BLKn during the program operation will be constantly adjusted. Therefore, a reduction in the read margin due to the difference in program speed can be prevented. The rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKn in the read operation can be adjusted. Therefore, read disturbance can be prevented.

35 is a perspective view showing a modification (BLKn ') of the memory block (BLKn) of FIG. 33; 36 is a cross-sectional view taken along the line VI-VI 'of the memory block BLKn' of FIG. 33 and 34 except that one pillar of the memory block BLKn 'includes the first sub-pillar 113a and the second sub-pillar 113b, the memory block BLKn' Is the same as the memory block BLKn.

As described with reference to FIGS. 16 and 17, one pillar in the memory block BLKn 'includes a first sub-pillar 113a and a second sub-pillar 113b. The first sub-pillars 113a and the second sub-pillars 113b will be configured as described with reference to FIGS. 22 and 23. FIG.

The memory block BLKn 'may be implemented with the equivalent circuits described with reference to FIG. 6 or FIGS. 23 to 26. The rising ramp of the program voltage Vpgm and the path voltage Vpass provided to the word lines of the memory block BLKn 'during the program operation will be constantly adjusted. Therefore, a reduction in the read margin due to the difference in program speed can be prevented. The rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKn 'in a read operation can be adjusted. Therefore, read disturbance can be prevented.

FIG. 37 is a perspective view showing a fifth embodiment (BLKo) of one of the memory blocks BLK1 to BLKz of FIG. 2. FIG. 38 is a cross-sectional view taken along line VII-VII 'of the memory block BLKo of FIG. 37;

37 and 38, on the substrate 111, first to fourth upper word lines UW1 to UW4 extending in the first direction are sequentially provided along the second direction. The first to fourth upper word lines UW1 to UW4 are provided apart from each other by a specific distance along the second direction. The first upper pillars UP1 are provided along the first direction and spaced apart from each other by a specific distance along the first direction and through the first to fourth upper word lines UW1 to UW4.

The first to fourth lower word lines DW1 to DW4 extending along the first direction are formed on the substrate 111 spaced apart from the first to fourth upper word lines UW1 to UW4 in the third direction Are sequentially provided along the second direction. The first to fourth lower word lines DW2 to DW4 are provided apart from each other by a specific distance along the second direction.

The first lower pillars DP1 are provided that are spaced apart from each other by a specific distance along the first direction and pass through the first to third lower word lines DW1 to DW4. A second lower pillars DP2 are provided, spaced apart from each other by a specific distance along the first direction, and passing through the first to fourth lower word lines DW1 to DW4 along the second direction. Illustratively, the first lower pillars DP1 and the second lower pillars DP2 may be arranged in parallel along the second direction.

On the substrate 111 spaced apart from the lower word lines DW1 to DW4 in the third direction, the fifth to eighth upper word lines UW5 to UW8 extending along the first direction extend along the second direction Sequentially. The fifth to eighth upper word lines UW5 to UW8 are provided apart from each other by a specific distance along the second direction. The second upper pillars UP2 are arranged to be spaced apart from each other by a specific distance along the first direction and through the fifth to eighth upper word lines UW5 to UW8 along the second direction.

A common source line CSL extending in a first direction is provided on top of the first and second lower pillars DP1 and DP2. Illustratively, the common source line (CSL) will comprise a silicon material having n type. Illustratively, when the common source line (CSL) is composed of a conductive material having no polarity such as metal or polysilicon, the common source line (CSL) and the first and second lower pillars (DP1 and DP2) Sources having n types may be additionally provided. Illustratively, the common source line CSL and the first and second lower pillars DP1 and DP2 may be connected through contact plugs, respectively.

And drains 320 are provided above the first and second upper pillars UP1 and UP2, respectively. Illustratively, the drains 320 will comprise a silicon material having n type. A plurality of bit lines BL1 to BL3 extending along the third direction are sequentially provided on the drains 320 along the first direction. Illustratively, the bit lines BL1 to BL3 will be made of metal. Illustratively, bit lines BLl through BL3 and drains 320 may be connected through contact plugs.

Each of the first and second upper pillars UP1 and UP2 includes a surface layer 116 &quot; and an inner layer 114 &quot;. Each of the first and second lower pillars DP1, DP2 includes a surface layer 116 &quot; and an inner layer 114 &quot;. The surface layer 116 &quot; is configured to store data like the insulating film 116 described with reference to Fig. For example, the surface layer 116 &quot; of the first and second upper pillars UP1 and UP2 and the first and second lower pillars DP1 and DP2 is formed of a blocking insulating film, a charge storage film, .

The tunnel insulating film will include a thermally oxidized film. The charge storage film 118 may include a nitride film or a metal oxide film (for example, an aluminum oxide film, a hafnium oxide film, or the like). The blocking insulating film 119 may be formed as a single layer or a multilayer. The blocking insulating film 119 may be a high-k film (for example, an aluminum oxide film, a hafnium oxide film, or the like) having a higher dielectric constant than the tunnel insulating film and the charge storage film. Illustratively, the tunnel insulating film, the charge storage film, and the blocking insulating film can constitute oxide-nitride-oxide (ONO).

The first and second upper pillars UP1 and UP2 and the inner layer 114 '' of the first and second lower pillars DP1 and DP2 will comprise a p-type silicon material. The first and second upper pillars UP1 and UP2 and the inner layer 114 '' of the first and second lower pillars DP1 and DP2 act as bodies in the second direction.

In the substrate 111, the first upper pillars UP1 and the first lower pillars DP1 are connected through the first pipeline contacts PC1. Illustratively, the surface layers 116 '' of the first upper pillars UP1 and the first lower pillars DP1 are each connected through the surface layers of the first pipeline contacts PC1. The surface layers of the first pipeline contacts PC1 will consist of the same materials as the surface layers 116 &quot; of the first upper pillars UP1 and the first lower pillars DP1.

Illustratively, the inner layers 114 '' of the first upper pillars UP1 and the first lower pillars DP1 are connected through the inner layers of the first pipeline contacts PC1, respectively. The inner layers of the first pipeline contacts PC1 will consist of the same materials as the inner layers 114 &quot; of the first upper pillars UP1 and the first lower pillars DP1.

That is, the first upper pillars UP1 and the first through fourth upper word lines UW1 through UW4 form the first upper strings, and the first lower pillars DP1, The lines DW1 to DW4 form first lower strings. The first upper strings and the first lower strings are connected via first pipeline contacts PC1, respectively. The drains 320 and the bit lines BL1 to BL3 are connected to one end of the first upper strings. A common source line (CSL) is connected to one end of the first substrings. That is, the first upper strings and the first lower strings form a plurality of strings connected between the bit lines BLl to BL3 and the common source line CSL.

Similarly, the second upper pillars UP2 and the fifth to eighth upper word lines UW5 to UW8 form the second upper strings, and the second lower pillars DP2, the first to fourth lower word lines The lines DW1 to DW4 form the second lower strings. The second upper strings and second lower strings are connected via second pipeline contacts PC2. And drains 320 and bit lines BL1 to BL3 are connected to one end of the second upper strings. A common source line (CSL) is connected to one end of the second substrings. That is, the second upper strings and the second lower strings form a plurality of strings connected between the bit lines BLl to BL3 and the common source line CSL.

The equivalent circuit of the memory block BLKo is similar to that of FIG. 6 except that eight transistors are provided in one string and two strings are connected to each of the first to third bit lines BL1 to BL3 will be. However, the number of word lines, bit lines, and strings of the memory block BLKo is not limited.

Illustratively, first and second pipeline contact gates (not shown) are provided, respectively, to form a channel in the inner layer that operates on the body in the first and second pipeline contacts PC1 and PC2 . Illustratively, first and second pipeline contact gates (not shown) will be provided on the surfaces of the first and second pipeline contacts PC1, PC2.

Illustratively, for convenience of explanation, the conductive lines UW1 to UW8, DW1 to DW4 extending in the first direction are described as word lines. However, bit lines BL1 to BL3 and adjacent upper word lines UW1 and UW8 will be used as string select lines (SSL).

39 is a block diagram illustrating a memory system 1000 including the non-volatile memory devices 100, 200 of FIG. 1 or 14. FIG. 39, the memory system 1000 includes a non-volatile memory device 1100 and a controller 1200. The non-

The non-volatile memory device 1100 will be configured and operated as described with reference to Figures 1-38.

The controller 1200 is connected to the host (Host) and the nonvolatile memory device 1100. In response to a request from the host (Host), the controller 1200 is configured to access the non-volatile memory device 1100. For example, the controller 1200 is configured to control the read, write, erase, and background operations of the non-volatile memory device 1100. The controller 1200 is configured to provide an interface between the non-volatile memory device 1100 and the host (Host). The controller 1200 is configured to drive firmware for controlling the non-volatile memory device 1100.

Illustratively, controller 1200 further includes well known components such as RAM (Random Access Memory), a processing unit, a host interface, and a memory interface. The RAM is used as at least one of an operation memory of the processing unit, a cache memory between the nonvolatile memory device 1100 and the host, and a buffer memory between the nonvolatile memory device 1100 and the host. do. The processing unit controls all operations of the controller 1200.

The host interface includes a protocol for performing data exchange between the host (Host) and the controller 1200. Illustratively, the controller 1200 may be implemented using any of a variety of communication protocols, such as a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI- (Host) interface through at least one of various interface protocols such as a Serial-ATA protocol, a Parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, . The memory interface interfaces with the non-volatile memory device 1100. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system 1000 may be further configured to include error correction blocks. The error correction block is configured to detect and correct errors in data read from the non-volatile memory device 1100 using an error correction code (ECC). Illustratively, the error correction block is provided as a component of the controller 1200. An error correction block may be provided as a component of the non-volatile memory device 1100.

Controller 1200 and nonvolatile memory device 1100 may be integrated into a single semiconductor device. Illustratively, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to form a memory card. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into a single semiconductor device and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM) (SD), miniSD, microSD, SDHC), universal flash memory (UFS), and the like.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into a single semiconductor device to form a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 10 is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 1000 is drastically improved.

As another example, the memory system 1000 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, A mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box A digital camera, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, Ha Is provided as one of various components of an electronic device, such as one of a variety of electronic devices, one of various electronic devices that make up a telematics network, an RFID device, or one of various components that make up a computing system.

Illustratively, non-volatile memory device 1100 or memory system 1000 may be implemented in various types of packages. For example, the nonvolatile memory device 1100 or the memory system 1000 may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package -Level Processed Stack Package (WSP) or the like.

40 is a block diagram illustrating an application example of the memory system 1000 of FIG. 40, a memory system 2000 includes a non-volatile memory device 2100 and a controller 2200. The non- The non-volatile memory device 2100 includes a plurality of non-volatile memory chips. The plurality of nonvolatile memory chips are divided into a plurality of groups. Each group of the plurality of non-volatile memory chips is configured to communicate with the controller 2200 via one common channel. In Fig. 40, a plurality of nonvolatile memory chips are shown as communicating with the controller 2200 through the first through k-th channels CH1 through CHk. Each nonvolatile memory chip is configured similarly to the nonvolatile memory device 100 described with reference to FIGS.

In FIG. 40, it has been described that a plurality of nonvolatile memory chips are connected to one channel. However, it will be appreciated that the memory system 2000 can be modified such that one non-volatile memory chip is connected to one channel.

FIG. 41 is a block diagram illustrating a computing system 3000 including the memory system 2000 described with reference to FIG. 41, the computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, and a memory system 2000 .

The memory system 2000 is electrically coupled to the central processing unit 3100, the RAM 3200, the user interface 3300 and the power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

In Figure 41, the non-volatile memory device 2100 is shown coupled to the system bus 3500 via a controller 2200. [ However, the non-volatile memory device 2100 may be configured to be connected directly to the system bus 3500. [

In Figure 41, it is shown that the memory system 2000 described with reference to Figure 40 is provided. However, the memory system 2000 may be replaced by the memory system 1000 described with reference to FIG.

Illustratively, the computing system 3000 may be configured to include all of the memory systems 1000, 2000 described with reference to Figures 39 and 40. [

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

100, 200; Nonvolatile memory device
110; The memory cell array
BLK1 to BLKz; Memory block
NS; NAND string
Vpgm; Program voltage
Vpass; Pass voltage
Vrd; Select reading voltage
Vread; Unselected read voltage

Claims (10)

A memory cell array including a plurality of memory cells stacked in a direction orthogonal to the substrate;
A row select circuit coupled to the memory cell array through word lines; And
And a ramper for controlling driving signals to be provided to the word lines,
Wherein when the first and second word lines are supplied with the first and second driving signals, respectively, the rising ramps of the first driving signal and the second driving signal have the same non-volatility Memory device. The method according to claim 1,
Wherein the rampers include ramping blocks corresponding to the word lines, and the ramping blocks control a rising ramp of the driving signals to be equal to a rising ramp of a reference driving signal. The method according to claim 1,
Wherein when the first word line is closer to the substrate than the second word line, the ramper controls the rising ramp of the first driving signal so that the rising ramp of the first driving signal and the rising signal of the second driving signal To be equal to each other during a time interval. The method according to claim 1,
The memory cell array
And first and second sub pillars perpendicular to the substrate and vertically stacked on the substrate,
The ramp
At least one first ramping block for adjusting a rising slope of a driving signal provided to a word line adjacent to the substrate among the word lines corresponding to the first sub-pillar; And
And at least one second ramping block for adjusting a rising slope of a driving signal provided to a word line adjacent to the substrate among the word lines corresponding to the second sub-pillar. The method according to claim 1,
Wherein the ramper outputs driving signals which gradually increase to a target voltage. 6. The method of claim 5,
Wherein the ramper adjusts a rising slope of the driving signals by adjusting a transition point of the ramping activation signals. A nonvolatile memory device; And
And a controller configured to control the nonvolatile memory device,
The nonvolatile memory device
A memory cell array including a plurality of memory cells stacked in a direction orthogonal to the substrate;
A row select circuit coupled to the memory cell array through word lines; And
And a ramper for controlling driving signals to be provided to the word lines,
Wherein when the first and second word lines are supplied with the first and second driving signals, respectively, the rising ramps of the first driving signal and the second driving signal are equal to each other during a predetermined time interval, system. 8. The method of claim 7,
Wherein the ramper includes ramping blocks corresponding to the word lines and the ramping blocks control a rising ramp of the driving signals to be equal to a rising ramp of a reference driving signal. 8. The method of claim 7,
Wherein when the first word line is closer to the substrate than the second word line, the ramper controls the rising ramp of the first driving signal so that the rising ramp of the first driving signal and the rising signal of the second driving signal To be equal to each other during a time interval. 8. The method of claim 7,
The memory cell array
And first and second sub pillars perpendicular to the substrate and vertically stacked on the substrate,
The ramp
At least one first ramping block for adjusting a rising slope of a driving signal provided to a word line adjacent to the substrate among the word lines corresponding to the first sub-pillar; And
And at least one second ramping block for adjusting a rising ramp of a driving signal provided to a word line adjacent to the substrate among the word lines corresponding to the second subpillar.

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