TWI489593B - Hot carrier programming of nand flash memory - Google Patents

Description

Hot-loading stylization of the gate flash memory

This invention relates to flash memory technology, and more particularly to flash memory suitable for low voltage stylization and erase operations in an anti-gate configuration.

Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory uses floating gate memory cells. As the density of the memory device increases, the floating gate memory cells are closer together, and the charge interaction stored in the adjacent floating gates causes a problem, thus forming a limitation, so that the floating gate density of the floating gate is used. Unable to upgrade. Another type of memory cell used in flash memory is called a charge trapping memory cell, which uses a charge trapping layer instead of a floating gate. The charge trapping memory cell utilizes a charge trapping material that does not cause interaction between individual memory cells as a floating gate, and can be applied to high density flash memory.

A typical charge storage memory cell includes a field effect transistor (FET) structure including a source and a drain separated by a channel, and a gate separated from the channel by a charge storage structure, wherein the charge storage structure comprises A tunneling dielectric layer, a charge storage layer (floating gate or dielectric layer), and a barrier dielectric layer. Earlier conventional designs, such as SONOS devices, in which the source, drain and channel are formed on the germanium substrate (S), the tunneling dielectric layer is over the germanium oxide (O), and the charge storage layer is formed of tantalum nitride. (N), the barrier dielectric layer is formed of ruthenium oxide (O), and the gate is polycrystalline germanium (S).

Flash memory devices can typically be implemented using either a NAND or a NOR architecture, but can be other architectures, including an AND architecture. This NAND architecture is favored especially for its high density and high speed advantages in data storage applications. The inverse OR gate (NOR) architecture is suitable for other applications such as program storage, because random access is an important functional requirement. In a NAND architecture, the stylization process typically relies on Fuller-Nordheim (FN) tunneling and requires high voltages, typically on the order of 20 volts, and requires high voltage transistors for processing. This extra high-voltage transistor and the transistors used in logic and other data streams are in the same integrated circuit, which increases the complexity of the process. This will increase the manufacturing cost of the device.

Therefore, there is a need to provide a new memory technology that can be programmed with low voltage in a NAND architecture.

The present invention relates to a memory device and a method of operating the same. According to one aspect of the present invention, a memory includes a plurality of memory cells arranged in series in a semiconductor body; a plurality of word lines, each of the plurality of word lines and the plurality of memory cells a corresponding memory cell coupling; and a control circuit coupled to the plurality of word lines. The control circuit is adapted to program a selected memory cell corresponding to a selected word line in the plurality of memory cells. The programming is performed by biasing one of the first and second ends of the plurality of memory cells to a set voltage; reducing the one of the first and second ends applied to the plurality of memory cells The voltage level is from the set voltage to the one-bit threaded voltage; applying a turn-on voltage to the word line corresponding to the unselected memory cell; and applying a stylized voltage to the selected word corresponding to the selected memory cell Yuan line.

The semiconductor body includes a lightly doped substrate region. The doping concentration of the lightly doped substrate region is less than or equal to 5 x ^{10 12} cm ^-2 . The lightly doped substrate region includes an N-type doped region.

Each memory cell includes a respective charge trapping structure. The charge trapping structure can be formed over a lightly doped substrate region. The charge trapping structure includes respective channel oxide layers, each channel having a thickness of less than 90 angstroms.

The stylized voltage applied to the selected word line is less than or equal to 17 volts. The turn-on voltage is in the range of 3 to 8 volts.

Applying the set voltage causes an inversion in the semiconductor body.

The step of biasing one of the first and second ends of the plurality of memory cells is performed in a first time interval, and wherein the step of lowering the voltage level, applying the turn-on voltage, and applying the stylized voltage is It is performed in a second time interval after the first time interval.

Performing biasing one of the first and second ends of the plurality of memory cells while applying a ground voltage level to the other of the first and second ends of the plurality of memory cells and to the plurality of words Each of the lines.

According to another aspect of the present invention, a memory includes a first series arranged in series in a semiconductor body; a second series arranged in series in the semiconductor body; a plurality of word lines, the plurality of characters Each of the word lines in the line is coupled to one of the first series of memory cells and one of the second series of memory cells of the plurality of memory cells; and coupled to the plurality of word lines Control circuit. The control circuit is adapted to program a selected memory cell corresponding to a selected word line in the first string. The stylization can be achieved by applying a one-bit threaded voltage to one of the first and second ends of the first series of memory cells; maintaining the second string of memory cells The first and second ends are at the ground class voltage; applying a turn-on voltage to a word line corresponding to the unselected memory cell; and applying a stylized voltage to the selected word corresponding to the selected memory cell Yuan line.

The semiconductor body includes a lightly doped substrate region. The doping concentration of the lightly doped substrate region is less than or equal to 5 x ^{10 12} cm ^-2 . The lightly doped substrate region includes an N-type doped region.

Each memory cell includes a respective charge trapping structure. The charge trapping structure can be formed over a lightly doped substrate region. The charge trapping structure includes respective channel oxide layers, each channel having a thickness of less than 90 angstroms.

The stylized voltage applied to the selected word line is less than or equal to 17 volts. The turn-on voltage is in the range of 3 to 8 volts.

Applying the set voltage causes an inversion in the semiconductor body.

The control circuit is further configured to bias one of the first and second terminals of the first series of memory cells to a set voltage in a first time interval, and simultaneously apply a ground voltage level to The other of the first and second ends of the first series of memory cells, each of the plurality of word line lines, and the first and second ends of the second series of memory cells . Applying the bit threading voltage, maintaining both the first and second ends of the second serial memory cell at the ground level voltage, applying the turn-on voltage, and applying the stylized voltage are all The second time interval after the first time interval is performed.

Applying the bit to thread the voltage includes decreasing a voltage level of the one of the first and second ends applied to the first series of memory cells from the set voltage to the bit threaded voltage.

The following description of the embodiments of the present invention is described in conjunction with Figures 1 through 8.

Figures 1A and 1B respectively show a cross-sectional view of a plurality of charge-trapping flash memory cells connected in series to form an anti-gate sequence, and a bias diagram for performing FN tunneling stylization, which is in the inverse gate flash memory. Typical operations in the architecture. Figure 1C shows a schematic diagram of the inverted gate train shown in Figures 1A and 1B.

FIG. 1A shows a bias diagram of a reverse-to-gate sequence including a target memory cell (memory cell A in FIG. 1C) on a selected bit line, and FIG. 1B shows that the pair is located on an unselected bit line. The reverse bias diagram of the gate series. A technique for implementing a backlash flash memory using an energy gap engineering SONOS charge trapping technique can be found in U.S. Patent No. 7,315,474, issued toU.S. The reverse gate series can be implemented using a number of different configurations, including fin field effect transistor technology, shallow trench isolation technology, vertical reverse gate technology, and the like. For an example of certain vertical reversal gate structures, see European Patent No. EP 2048709 to Kim et al., entitled "Non-volatile memory device, method of operating same and method of fabricating the same."

Referring to FIG. 1A, the memory cell is formed in a semiconductor body 10. For n-channel memory cells, semiconductor body 10 can be an isolated p-well within a deeper n-well of a semiconductor wafer. Alternatively, the semiconductor body 10 can be isolated by an insulating layer or other similar means. Some embodiments may use p-channel memory cells in which the doping in the semiconductor body 10 is n-type.

The plurality of flash memory cells can be arranged in a series of bit line directions that are orthogonal to the direction of the word line. The word lines 22-27 extend through a number of parallel anti-gate trains. Nodes 12-18 are n-type regions (for n-channel devices) in the semiconductor body and serve as source/drain regions for the memory cells. A first switch formed by a MOS transistor has a gate in the ground select line GSL 21 coupled to a corresponding memory cell having a first word line 22 (WL0 in FIG. 1C) and a semiconductor The n-type region in the body 10 is formed between one of the contacts 11. This contact 11 is connected to the common source line CS 30. A second switch formed by the MOS transistor has a gate in the string select line SSL 28 coupled to the corresponding memory cell having the last word line 27 and formed by the n-type region in the semiconductor body 10. One of the contacts 19 is between. This contact 19 is connected to the bit line BL 31. The first and second switching switches in this exemplary embodiment are MOS transistors, in this example thyristor dielectric layers 7 and 8.

In this illustration, there are six memory cells in this series for the sake of simplicity. In a typical configuration, an inverse gate sequence can contain 16, 32 or more memory bank arrangements. The word lines 22-27 corresponding to these memory cells have a charge trapping structure 9 between the word lines and the channel regions in the semiconductor body 10. The charge trapping structure 9 in this memory cell can be a dielectric charge trapping structure, a floating gate charge trapping structure, or other suitable flash memory structure suitable for programming using the techniques described herein. In addition, no junctions have been developed in embodiments that are inverse gate flash structures in which nodes 13-17, and optionally nodes 12 and 18, may be omitted from this configuration.

FIG. 1A shows a cross-sectional view of a conventional technique NAND architecture flash memory in which FN tunneling is induced to program a biased pattern of memory cells corresponding to word line 24. According to the bias voltage shown here, the ground select line GSL is biased to approximately 0V and the common source line is grounded such that the first switch corresponding to the ground select line GSL 21 is off and the tandem select line SSL bias To about V _CC and the selected bit line is also grounded, so that the second switch corresponding to the serial select line SSL 28 is turned on. Under these conditions, the semiconductor body in region 33 associated with the gate series is precharged to about 0V. The selected word line 24 is biased to a high voltage stylized class V-PGM, which in some embodiments can be on the order of 20-22 volts. Selecting such a high voltage is sufficient to cause hot electrons in the body 10 to tunnel into the charge trapping structure 9 of the selected memory cell. At the same time, the unselected word lines 22, 23, 25-27 are biased to a turn-on voltage V-PASS which is less than a V-PGM that is less than a stylized voltage that can suppress unselected cells in the series. For example, the gate of the memory cell C receives the turn-on voltage V-PASS from the word line 25, and although the memory cell C has a body region that is set to be programmed, the low turn-on voltage V-PASS is still sufficient to interfere with the memory. The stylization process of cell C.

FIG. 1B is a cross-sectional view showing a conventional flash memory (NAND) architecture flash memory, which shares the bias of the uncharacterized bit lines of the gate lines 22 to 27 and the gate series of the gate array. schematic diagram. As can be seen from the figure, all word lines, ground selection lines GSL and serial selection lines SSL are the same as those shown in FIG. 1A. Similarly, the common source line 30 is also grounded. However, the unselected bit lines are biased to a level of approximately V _CC . This will turn off the second switch, which corresponds to the string select line SSL, and decouples the semiconductor body in region 35 from the unselected bit line BL32. As a result, the semiconductor body in region 35 will self-pressurize by the capacitive coupling generated by the voltage applied to word lines 22-27, which can prevent the charge trapping structure in the memory cells of the unselected inverse gate series from being sufficiently disturbed. The electric field is formed. The so-called incremental step pulse programming (ISSP) operation based on capacitive self-pressure is well known in the art.

Although the stylized operations described in Figures 1A-1C can be efficient, they still have certain disadvantages. One problem is that the stylized voltage class V-PGM requires such a high voltage class (eg 20-22 volts). Such high voltages necessitate design limitations on the semiconductor structure of certain memory devices, making the shrinking of semiconductor structures difficult.

Another problem with conventional stylized operations such as those described in Figures 1A-1C is that it only allows a small range of variations in the turn-on voltage V-PASS to prevent interference. On the other hand, if the turn-on voltage V-PASS is too low, there will not be enough capacitive coupling effect to boost the unselected inverse gate series as shown in FIG. 1B, but to the target memory cell. (Memory cell A in Fig. 1C) Memory cells sharing the word line (memory cell B in Fig. 1C) cause interference. On the other hand, if the turn-on voltage V-PASS is too high, hot carrier injection may be generated in the unselected memory cells (memory cell C in Fig. 1C) in the selected gate sequence. As a result, the turn-on voltage V-PASS must be carefully controlled between its upper and lower boundaries. For example, a typical turn-on voltage V-PASS range is between 9 and 11 volts. Such rigorous control can be difficult due to factors such as process or environmental changes.

Another problem with such conventional stylized operations is that sometimes a so-called gate induced drain leakage (GIDL) problem occurs, for example, at the junction between the ground select line GSL and the memory cell of the word line WL0. This gate induced dipole leakage (GIDL) problem is difficult to avoid and can become more severe after the device is miniature.

These and other shortcomings of conventional anti-gate memory devices and stylized operations can be overcome by using the devices and methods described herein. An improved inverse thyristor device can have an inverse thyristor cell similar to that of Figures 1A and 1B, wherein each memory cell includes a charge trapping structure between the doped source/drain regions. However, the anti-gate memory cells disclosed herein are preferably formed over the lightly doped substrate region, for example, having a doping concentration of less than 5 x ^{10 12} cm ^-2 , preferably greater than zero such that a small amount of impurities are present. . This lightly doped substrate allows for inversion at lower voltage levels. In general, the anti-gate memory cell is an N-type device, although a P-type device may also be feasible and can be implemented by those skilled in the art in accordance with the spirit of the present invention. In summary, this disclosure focuses primarily on N-type devices. In an N-type device, the source/drain regions comprise N ⁺ doped regions, for example formed as buried diffusion regions. In such cases, the lightly doped regions are N ^- type doped, which can help with electron inversion.

Moreover, the memory devices and stylized operations disclosed herein may allow for the reduction of the stylized voltage class V-PGM, for example, the stylized voltage class V-PGM may be less than or equal to 17 volts. For example, a stylized voltage class V-PGM can be achieved between 13V ≦V-PGM ≦ 17V. In the apparatus and stylized operations described herein, the channel potential (Vch) can be boosted to 0.6 times or 0.7 times the stylized voltage class V-PGM due to very low substrate doping. For example, a 13V stylized voltage can boost the channel potential to approximately 7 or 8V, which can induce a hot carrier to be injected into the memory cell's storage node. As a result, a smaller turn-on voltage V-PASS can be used, for example, between 3V ≦V-PASS ≦ 8V, which can help suppress gate induced gate leakage (GIDL). In addition, the same turn-on voltage V-PASS can be used for stylization and read operations.

Figures 2A and 2B show an embodiment of such a reverse flash memory device. Figure 2A shows a cross-sectional view of a plurality of dielectric charge trapping flash memory cells arranged in series to form a portion of the gate sequence, and Figure 2B shows the inverse gate series 101 and 103 including the memory cells shown in Figure 2A. Schematic diagram.

The reverse gate trains 101 and 103 include first and second switch switches respectively corresponding to the ground selection line GSL and the tandem selection line SSL, which are similar to those shown in FIGS. 1A and 1B, each of which is composed of a gold oxide half. A transistor is formed, the transistor having a gate connected between a memory cell and a contact, wherein the contact is formed by an n-type region formed in the semiconductor body 10. The ground selection line GSL in this case can be connected to the common source line CS; in this case, the series selects the line SSL, which can be connected to the bit line BL. Referring to Figure 2A, each memory cell is connected to a respective word line WL, such as word line 23-25 shown in Figure 2A. Each of these memory cells also includes a respective charge trapping structure 9 between the word line WL and the channel region within the semiconductor body 10. For n-channel memory cells, semiconductor body 10 can be an isolated p-well within a deeper n-well of a semiconductor wafer. Alternatively, the semiconductor body 10 can be isolated by an insulating layer or other similar means. Some embodiments may use p-channel memory cells in which the doping in the semiconductor body 10 is n-type.

The plurality of flash memory cells are arranged in a series arranged along a direction of the bit line orthogonal to the direction of the word line. The word line WL extends through a number of parallel anti-gate trains. For example, the node 14-15 shown in FIG. 2A is formed by an n-type region (for an n-channel device) in the semiconductor body 10 and serves as a source/drain region of the memory cell.

In this illustration, there are six memory cells in this series for the sake of simplicity. In a typical configuration, an inverse gate sequence can contain 16, 32 or more memory bank arrangements. The word lines WL0-WL5 corresponding to these memory cells have a charge trapping structure 9 between the word lines and the channel regions in the semiconductor body 10.

It must be noted that the memory device shown in FIG. 2A may include a lightly doped substrate region 40 to erase the inversion of a minority carrier such as an electron in an n-channel device. In other words, the inversion process can occur at a relatively lower voltage level than devices that are conventionally do not have a lightly doped substrate region 40. This lightly doped substrate region 40 can be doped with the same conductivity type as the source/drain regions 14 and 15. For example, for an n-channel device, the lightly doped substrate region 40 can be an n ^- doped region. For embodiments comprising the lightly doped substrate region 40, the lightly doped region may have a doping concentration of less than or equal to 5 x ^{10 12} cm ^-2 . This lightly doped region 40 can be formed using, for example, a known diffusion process.

The charge trapping structure 9 in this memory cell can be a dielectric charge trapping structure, a floating gate charge trapping structure, or other suitable flash memory structure suitable for programming using the techniques described herein. In addition, no junctions have been developed in embodiments that are inverse gate flash structures in which nodes 13-17, and optionally nodes 12 and 18, may be omitted from this configuration.

FIG. 2B is a schematic diagram showing the biasing of a plurality of dielectric charge trapping flash memory cells in series to form the anti-gate trains 101 and 103 and their stylized operation. In FIG. 2B, the inverse gate train 101 is a selected memory string including a target memory cell (memory cell A) on the word line WL2 for program operation. The inverse gate train 103 is an unselected memory string connected to an unselected bit line BL1. As compared with Figure 1C, it can be seen that the stylized bit line and the stylized interfering bit line voltage system in Figure 2B are the opposite of those in Figure 1C.

FIG. 3 is a timing diagram showing an example of the operation signal of the second figure and the operation of the gate sequence 101. More specifically, the unselected word line signal 105, the selected word line signal 106, the tandem selection line SSL signal 107, and the ground selection line GSL signal 108 are shown in FIG. To program the target memory cell A, the unselected word line signal 105 is applied to the unselected word lines WL0, WL1 and WL3~WL5, and the selected word line signal 106 is applied to the selected word line WL2, the serial selection line SSL signal. The self-bit line BL0 is applied to the substrate through the serial selection switch, and the ground selection line GSL signal 108 is applied to the substrate from the common source line CS through the ground selection switch.

At time t0, the reverse gate train 101 is in a ready state, and its signals 105 to 108 are all set to 0V. At or before time t1, the stylized operation is initiated, for example, by a known memory control system by internal commands. In response, as shown in FIG. 2B, a voltage of about Vcc is applied to the string selection line SSL, the series selection switch is turned on, and a voltage of ≦0V is applied to the ground selection line GSL to turn off the ground selection switching. switch. At time t1, the serial select line SSL signal 107 includes a set pulse 111 applied to the substrate of the selected reverse gate train 101 through the bit line BL0. This set pulse 111 exceeds Vcc by a predetermined value. For example, some voltage ranges are at the threshold voltage <Vcc < set pulse 111 of the serial select line SSL. The set pulse 111 creates a situation in which the threshold voltage of the tandem selection switch is higher than that of the gate, and has the effect of drawing electrons into the channel region, in other words, it initially initiates this inversion process in the series. . Note that this effect does not occur in the unselected series 103 where the bit line BL1 is applied with 0V.

At time t2, when the stylized voltage is applied to the selected word line WL2 of the memory cell A, the thermal electrons in the memory cell A close to or in the channel are pulled into the charge trapping structure 9 of the memory cell A. It must be noted that the voltage classes in Figure 3 are not drawn to scale and must be understood to be V-PGM > V-PASS. At time t2, V-PASS is applied to the unselected memory cells, but V-PASS is not strong enough to allow hot electrons to overcome the charge trapping structure that is captured into unselected memory cells such as memory cells B and C. The required height of the barrier. Finally, at time t3, all voltages return to 0V and this stylization is complete. Those skilled in the art should understand that certain periods of time between t2 and t3 may be selected to allow proper time for tunneling of hot electrons into the charge trapping structure 9, and may vary depending on factors such as device size and material. And change.

Next, please refer to Figures 4A and 4B, which show examples of stylized voltages and channel oxide thicknesses that can be used as specific applications for the devices shown in Figures 2A and 2B. For example, as shown in FIG. 4A, in some embodiments, a staging voltage of approximately 17V can be used as the V-PGM, and the turn-on voltage V-PASS is approximately 7-13V. As shown in Fig. 4A, a significant number of electrons are injected into the charge trapping structure 9 of the selected memory cell A, while only a few memory cells B are not selected.

Figure 4C shows a schematic cross-sectional view of a memory cell of an embodiment showing an enlarged view of an exemplary charge trapping structure 9 associated with word line 24 memory cells. The other memory cells are the same as those shown in Fig. 4C, so only one memory cell is shown for the sake of simplicity. The charge trapping structure 9 includes a channel oxide layer 9c directly over the substrate 10 or, more specifically, over the lightly doped region 40 of the substrate. Thereafter, a floating gate (charge storage) layer 9b is directly provided over the channel oxide layer 9c. A barrier dielectric layer 9a is provided directly over the floating gate layer 9b. The control gate 24 is directly over the blocking dielectric layer 9a. Thus, for example, the charge trapping structure 9 can be formed using a structure of yttrium-yttria-yttria-yttria-yttria (SONOS). However, other charge trapping structures can also be used.

Figure 4B shows that the stylization operation of the present invention can advantageously allow a relatively thick channel oxide layer to be present in the charge trapping structure 9 of the memory cells shown in Figures 2A and 2B. For example, the thickness T9c of the channel oxide layer 9c may be in the range of 79 to 91 angstroms. A thicker channel oxide layer may require a slightly longer stylized time (e.g., a longer time in Figure 3 between t2 and t3), so it is preferred that the T9c thickness be less than 90 angstroms. However, memory cells with thicker channel oxide layers can have the advantage of longer shelf life, so other thicknesses can be used.

Figure 5 shows a comparison of the conventional inverse gate memory string with the word line WL0 distribution of the present invention. As shown in FIG. 5, since the anti-gate flash memory device of the present invention has a lower stylized voltage V-PGM and a turn-on voltage V-PASS voltage class than the conventional anti-gate memory device, the inverse gate of the present invention Flash memory devices can have the advantage of significantly reducing the distribution of word line WL0 due to the elimination of gate induced drain leakage (GIDL), which is still sufficient to generate hot carriers in this region.

Fig. 6 is a view showing the energy band of the present invention for selecting how to generate a hot carrier injection when the memory cell A is programmed. It must be noted that Figure 6 shows the electron injection as it occurs in the N-channel device. Those skilled in the art will appreciate that hole injection is a P-channel device. During the stylization operation, the higher tandem select pulse 111 provides energy to the electrons in the substrate, including electrons in the lightly doped substrate region 40. The inter-band tunneling accelerates the electrons and these electrons become hot electrons. The application of the stylized voltage V-PGM attracts these hot electrons, providing sufficient energy to overcome the energy barrier in the channel oxide layer, allowing hot electrons to be injected into the floating gate (FG) layer.

Figure 7 shows the results of the experimental data showing how to achieve a sufficient threshold voltage Vt difference to allow determination of whether a memory cell is programmed or erased. For example, in Fig. 7, the erased memory cell B can be distinguished from the memory cell A because the threshold voltage difference therebetween is about 3.5V.

Figure 8 shows a simplified schematic of an integrated circuit that uses the hot carrier described herein to inject a programmed inverse gate flash memory. The integrated circuit 210 includes a memory array 212 that uses charge trapping or floating gate memory cells, which are formed, for example, on a semiconductor substrate. A word line (or column) ground selection and serial selection decoder (including a suitable driver) 214 is coupled to the plurality of word lines 216, the string selection line, and the ground selection line and electrically communicated, and along the memory The arrays 212 are arranged in the column direction. The bit line (row) decoder and driver 218 is electrically coupled to the plurality of bit lines 220 and arranged along the row direction of the memory array 212 to read data or write data from the memory cells of the array 212. The address is provided by bus bar 222 to word line and string select decoder 214 and bit line decoder 218. The sense amplifier and data input structures in block 224, including current sources for read, program, and erase modes, are coupled to bit line decoder 218 via data bus 226. The data is supplied to the data input line 228 by the input/output ports on the integrated circuit 210, or is input to the data input structure in block 224 by other internal/external data sources of the integrated circuit 210. Other circuits 230 are included within integrated circuit 210, such as a general purpose processor or special purpose application circuit, or a combination of modules to provide system single chip functionality supported by the array. The data is provided by the sense amplifier in block 224, via the data output line 232, to the integrated circuit 210, or to other data terminals internal/external to the integrated circuit 210.

The controller 234 used in this embodiment uses a bias adjustment state mechanism to control the application of the bias voltage adjustment supply voltage and current source 236, such as reading, programming, erasing, erasing confirmation, and stylization. Verify that the voltage or current is applied to the word line or bit line and control the operation of the word line/source line using the access control flow. The controller also applies a switching sequence to induce the hot carrier stylization described herein. Controller 234 can be implemented using special function logic circuitry well known in the art. In an alternate embodiment, the controller 234 includes a general purpose processor that can be used in the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller 234 is a combination of special purpose logic circuitry and a general purpose processor.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

This paragraph is only relevant to US 37 CFR 1.77 and is therefore not translated.

7, 8. . . Gate dielectric layer

9. . . Charge trapping structure

10. . . Semiconductor body

11, 19. . . contact

12~18. . . node

twenty one. . . Ground selection line GSL

22~27. . . Word line

28. . . Serial selection line SSL

30. . . Common source line CS

31. . . Bit line

32. . . Unselected bit line

40. . . Lightly doped substrate area

101, 103. . . Reverse gate train

210. . . Integrated circuit

212. . . Anti-gate flash memory

214. . . Word line/serial selection decoder and driver

216. . . Word line

218. . . Bit line decoder

220. . . Bit line

222, 226‧‧ ‧ busbar

224‧‧‧Sense Amplifier/Data Entry Structure

234‧‧‧ Controller (hot carrier injection stylized, FN erase)

236‧‧‧ bias adjustment supply voltage

228‧‧‧ data input line

230‧‧‧Other circuits

232‧‧‧ data output line

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

Figures 1A and 1B show a cross-sectional view of a selected reverse gate train and an unselected reverse gate train, respectively, using a conventional stylized operational bias.

Figure 1C shows a schematic diagram of the inverted gate train shown in Figures 1A and 1B.

Figure 2A shows a cross-sectional view of a portion of a reverse flash memory string in accordance with an embodiment of the present invention.

Figure 2B shows a schematic diagram of a reverse gate flash memory string in accordance with an embodiment of the present invention.

Figure 3 is a diagram showing an example timing diagram of the operation signals of the reversed gate sequence of the 2A and 2B diagrams.

The graphs of Figures 4A and 4B show examples of stylized voltages and channel oxide thicknesses that can be used as specific applications for the devices shown in Figures 2A and 2B.

Figure 4C is a schematic cross-sectional view of a memory cell of an embodiment showing an enlarged view of an exemplary charge trapping structure.

Figure 5 shows a comparison of the conventional inverse gate memory string with the word line WL0 distribution of the present invention.

Fig. 6 is a view showing the energy band of the present invention in which a hot carrier injection occurs during a stylized operation.

Figure 7 shows the results of the experimental data showing how to achieve a sufficient threshold voltage Vt difference to allow determination of whether a memory cell is programmed or erased.

Figure 8 is a block diagram showing the integrated circuit of a hot carrier injection stylized inverse gate flash memory as described in the present invention.

101, 103. . . Reverse gate train

Claims (24)

A memory comprising: a plurality of memory cells arranged in series in a semiconductor body; a plurality of word lines, each of the plurality of word lines being coupled to a corresponding memory cell of the plurality of memory cells And a control circuit coupled to the plurality of word lines, the control circuit being adapted to program a selected memory cell corresponding to a selected word line of the plurality of memory cells by biasing the plurality of memory cells a series of selection lines of the memory cells to a set voltage; reducing a voltage level of the one of the first and second ends applied to the plurality of memory cells from the set voltage to a bit-threaded voltage; applying a turn-on voltage to a word line corresponding to the unselected memory cell; and applying a stylized voltage to the selected word line corresponding to the selected memory cell; wherein the bit threaded voltage is greater than the string A threshold voltage of the line is selected, and the stylized voltage is greater than the turn-on voltage. The memory of claim 1, wherein the semiconductor body comprises a lightly doped substrate region. The memory of claim 2, wherein the doped substrate region has a doping concentration of less than or equal to 5 x ^{10 12} cm ^-2 . The memory of claim 2, wherein the lightly doped substrate region comprises an N ^- type doped region. The memory of claim 1, wherein the plurality of memory cells are Each memory cell includes a respective charge trapping structure. The memory of claim 5, wherein the charge trapping structure is formed over a lightly doped substrate region. The memory of claim 5, wherein the charge trapping structure comprises a respective channel oxide layer, each channel oxide layer having a thickness of less than 90 angstroms. The memory of claim 1, wherein the stylized voltage applied to the selected word line is less than or equal to 17 volts. The memory of claim 8, wherein the turn-on voltage is in the range of 3 to 8 volts. The memory of claim 1, wherein applying the set voltage results in inversion in the semiconductor body. The memory of claim 1, wherein the step of biasing one of the first and second ends of the plurality of memory cells is performed in a first time interval, and wherein the voltage class is lowered The step of applying the turn-on voltage and applying the stylized voltage is performed in a second time interval after the first time interval. The memory of claim 1, wherein the biasing of one of the first and second ends of the plurality of memory cells simultaneously applies a ground voltage level to the first of the plurality of memory cells. The other of the second ends and to each of the plurality of word lines. A memory comprising: a first series of a plurality of memory cells arranged in series in a semiconductor body; a second series of a plurality of memory cells are arranged in series in the semiconductor body; a plurality of word lines, each of the plurality of word lines and the first string of the plurality of memory cells One of the column memory cells and one of the second serial memory cells are coupled; and a control circuit coupled to the plurality of word line lines, the control circuit being adapted to program the plurality of memory cells by the following steps a selected memory cell corresponding to a selected word line in the first series: biasing a set voltage to a series of select lines in the first serial memory cell; reducing a voltage level applied to the serial select line From the set voltage to the one-bit threaded voltage, the bit threaded voltage is greater than a threshold voltage of the string select line; maintaining both the first and second ends of the second string of memory cells The ground-level voltage; applying a turn-on voltage to a word line corresponding to the unselected memory cell; and applying a stylized voltage to the selected word line corresponding to the selected memory cell, the stylized voltage being greater than the turn-on Voltage. The memory of claim 13, wherein the semiconductor body comprises a lightly doped substrate region. The memory of claim 14, wherein the doped substrate region has a doping concentration of less than or equal to 5 x ^{10 12} cm ^-2 . The memory of claim 14, wherein the lightly doped substrate region comprises an N ^- type doped region. The memory of claim 13, wherein each of the plurality of memory cells comprises a respective charge trapping structure. The memory of claim 17, wherein the charge trapping structure is formed over a lightly doped substrate region. The memory of claim 17, wherein the charge trapping structure comprises a respective channel oxide layer, each channel oxide layer having a thickness of less than 90 angstroms. The memory of claim 13, wherein the stylized voltage applied to the selected word line is less than or equal to 17 volts. The memory of claim 20, wherein the turn-on voltage is in the range of 3 to 8 volts. The memory of claim 13, wherein applying the set voltage results in inversion in the semiconductor body. The memory of claim 13, wherein the control circuit is further configured to bias one of the first and second ends of the first series of memory cells in a first time interval Setting a voltage to a voltage, and simultaneously applying a ground voltage level to the other of the first and second ends of the first series of memory cells, each of the plurality of word lines, and the second Aligning both the first and second ends of the memory cell. The memory of claim 23, wherein the bit threading voltage is applied, maintaining the first and second ends of the second serial memory cell at the ground class voltage, applying the The turn-on voltage and the step of applying the stylized voltage are all performed in a second time interval after the first time interval.