CN100390966C - Operation scheme for spectrum shift in charge trapping non-volatile memory - Google Patents
Operation scheme for spectrum shift in charge trapping non-volatile memory Download PDFInfo
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- 238000001228 spectrum Methods 0.000 title description 6
- 238000000034 method Methods 0.000 claims abstract description 86
- 238000009826 distribution Methods 0.000 claims description 71
- 239000000758 substrate Substances 0.000 claims description 67
- 238000005516 engineering process Methods 0.000 claims description 51
- 239000000463 material Substances 0.000 claims description 30
- 238000012795 verification Methods 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 18
- 230000005684 electric field Effects 0.000 claims description 14
- 230000006870 function Effects 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 230000005611 electricity Effects 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims 1
- 239000002210 silicon-based material Substances 0.000 claims 1
- 230000005641 tunneling Effects 0.000 abstract description 18
- 230000009467 reduction Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 66
- 238000002347 injection Methods 0.000 description 49
- 239000007924 injection Substances 0.000 description 49
- 238000003860 storage Methods 0.000 description 39
- 230000008859 change Effects 0.000 description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 30
- 239000002784 hot electron Substances 0.000 description 24
- 230000000694 effects Effects 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 239000000377 silicon dioxide Substances 0.000 description 15
- 235000012239 silicon dioxide Nutrition 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- -1 silicon oxide nitride Chemical class 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 239000007787 solid Substances 0.000 description 9
- 230000007246 mechanism Effects 0.000 description 8
- 238000004321 preservation Methods 0.000 description 7
- 230000014509 gene expression Effects 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000009471 action Effects 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- FEWHDZOJQQLPEN-UHFFFAOYSA-N [O].[N].[O] Chemical compound [O].[N].[O] FEWHDZOJQQLPEN-UHFFFAOYSA-N 0.000 description 4
- 230000002688 persistence Effects 0.000 description 4
- 229920006395 saturated elastomer Polymers 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 230000006698 induction Effects 0.000 description 3
- 230000000977 initiatory effect Effects 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 206010010774 Constipation Diseases 0.000 description 2
- 240000002853 Nelumbo nucifera Species 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 2
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 2
- 230000000386 athletic effect Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 210000004392 genitalia Anatomy 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000006386 neutralization reaction Methods 0.000 description 2
- 238000006396 nitration reaction Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 238000003723 Smelting Methods 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000005524 hole trap Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- DEPMYWCZAIMWCR-UHFFFAOYSA-N nickel ruthenium Chemical compound [Ni].[Ru] DEPMYWCZAIMWCR-UHFFFAOYSA-N 0.000 description 1
- 229910001000 nickel titanium Inorganic materials 0.000 description 1
- HLXZNVUGXRDIFK-UHFFFAOYSA-N nickel titanium Chemical compound [Ti].[Ti].[Ti].[Ti].[Ti].[Ti].[Ti].[Ti].[Ti].[Ti].[Ti].[Ni].[Ni].[Ni].[Ni].[Ni].[Ni].[Ni].[Ni].[Ni].[Ni].[Ni].[Ni].[Ni].[Ni] HLXZNVUGXRDIFK-UHFFFAOYSA-N 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- KNVAYBMMCPLDOZ-UHFFFAOYSA-N propan-2-yl 12-hydroxyoctadecanoate Chemical compound CCCCCCC(O)CCCCCCCCCCC(=O)OC(C)C KNVAYBMMCPLDOZ-UHFFFAOYSA-N 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000013112 stability test Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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Abstract
A method of operating a memory cell comprises applying a first procedure (typically erase) to establish a low threshold state including a first bias arrangement causing reduction in negative charge in the charge trapping structure, and a second bias arrangement tending to the induce balanced charge tunneling between the gate and the charge trapping structure and between the charge trapping structure in the channel. A second procedure (typically program) is used to establish a high threshold state in the memory cell, including a third bias arrangement that causes an increase in negative charge in the charge trapping structure.
Description
Technical field
The invention relates to can the erase nonvolatile memory of (electrically programmable anderasable) of a kind of electric codified, and the charge capturing memory of settling relevant for a kind of tool bias voltage (charge trapping memory) particularly, except the operation of rising and reduction start voltage, also can be used for revising the electric charge in the memory.
Background technology
The electricity codified non-volatile memory technologies of can erasing is based on the technology of charge storing structure, and for example EEPROM and flash memory are usually used in the various modern Application.Many memory cell structures (memorycell structure) all are used for EEPROM and flash memory.Because of the simplification and the extensibility (scalability) of semiconductor technology,, the interest of the memory cell structure of tool charge-trapping dielectric layers is just increased gradually along with dwindling of integrated circuit size.The memory cell structure of above-mentioned tool charge-trapping dielectric layers comprises that for example industry name is called structures such as nitrogenize read-only memory (NROM), silicon oxide nitride oxide silicon (SONOS) and PHINES.The mode of these memory cell structure storage datas is by the mode of catching electric charge in charge-trapping dielectric layers such as for example silicon nitride.When negative electrical charge was captured, the start voltage of memory cell just increased, and during negative electrical charge in removing charge-trapping dielectric layers, the start voltage of memory cell just descends.
Traditional silicon oxide nitride oxide silicon (SONOS) element is to use ultra-thin bottom oxide, for example is less than 3 nanometers (nanometer), and biasing is arranged to cause the Direct Tunneling Effect that passage is erased.Though use the speed of erasing of this technology very fast, the charge leakage of the ultra-thin bottom oxide of break-through (charge leakage) can cause electric charge to keep deleterious.
Nitrogenize read-only memory (NROM) element uses more above-mentioned thick bottom oxide in order to prevent charge loss, for example above 3 nanometers and usually about 5 to 9 nanometers.Replace Direct Tunneling Effect, district's interband tunnelling causes that hot hole injects (band-to-band tunneling induced hot hole injection; BTBTHH) can be used to the memory cell of erasing.Yet hot hole injects the initiated oxidation damage layer, causes the charge loss (charge loss) of high start voltage unit, with the electric charge increase of low start voltage unit.In a nearlyer step, because the electric charge that is difficult to erase in the charge-trapping structure increases, programming was bound to increase gradually with the time of erasing of erase period.Because hole decanting point and electronics decanting point can not overlap and meet, the accumulation of electric charge can increase, some electric charges even also existence still after erase pulses.In addition, when the section of nitrogenize flash memory (NROM) element is erased (sector erase), because difference in operation (for example passage normal manner difference), can cause the speed of the erasing difference of each memory cell.The difference of the above-mentioned speed of erasing causes very large erased status start voltage to distribute (Vt distribution), and the some of them memory cell is transformed into and is difficult to erase, and some memory cell are excessively erased again.Therefore after experiencing many programmings and erase period, target start voltage window (target threshold window) is closed, and the persistence variation of memory cell.If the continuous minification of this technology, this phenomenon can become more serious.
Further specify, the charge capturing memory element grasps electric charge on shallow energy rank of electric charge capture layer (shallowenergy level) and dark energy rank (deep energy level).The electronics that is captured on shallow energy rank, its speed ratio that removes is faster at the electronics on dark energy rank.Yet the electronics on shallow energy rank has electric charge to cannot say for sure an important difficult problem of depositing.Preserve the electronics that preferably adopts dark rank to be captured in order to keep good electric charge.
Therefore, memory cell exists one to need, and its start voltage that can repeatedly programme and erase and need not bear behind the erase operation for use increases, and abdicates the memory cell in the non operating state.This needs also explanation need improve electric charge preservation and Reliability.
Summary of the invention
The invention provides the method for a kind of operation store unit and the integrated circuit mechanism with this memory cell, it has improved memory cell persistence and Reliability.The charge balance operation of charge capturing storage unit is below described.This charge balance operation comprises bias voltage arrangement (bias arrangement), it comprises that electric field from the grid to the passage assists electronics to penetrate (E-field assisted electron ejection) and/or in the hole direct Tunneling (directtunneling) of thin end dielectric layer (thin bottom dielectrics), assist electronics injection (E-fieldassisted electron injection) and balance by the electric field from grid to the charge-trapping structure, above-mentioned injection mode comprises that the negative-gate voltage that relative substrate is provided (can provide-V
GOr positive substrate voltage+V
SUS, or combination-V
GWith+V
SUS), with being provided, source electrode and grounded drain or one hang down positive voltage.Voltage difference from grid to the substrate passage, it is used to finish the charge balance operation, is to be limited in to be higher than-0.7 volt of (V)/nanometer (nanometer) approximately preferably about-1.0 volts/nanometer of following examples.So, for having the memory cell of gate electrode, top oxide layer, charge-trapping and bottom oxide, the grid that is used for the charge balance operation is to substrate bias, it is the effective oxide thickness that approximates above-mentioned top oxide layer, charge-trapping and bottom oxide combination, is about-0.7 volt/nanometer and arrives about-1.1 volts/nanometer.
When charge balance was operated, grid injects (gate injection) and electronics removes (electronde-trapping) meeting generation to set up dynamic equilibrium (dynamic balance) or equilibrium state (equilibrium state).Grid injects the seizure hole that electronics can and be left behind after hot hole is erased.Therefore, the charge balance operation can provide " electronics smelting " (the electrical annealing) of the last one, injects the injury that causes to minimize hot hole.Stability test shows that also charge balance operation can reduce the charge loss because of being caused after repeatedly programming and the erase period in a large number.
Method according to technology proposition of the present invention, comprise: by first bias voltage settle to reduce memory cell start voltage, settle the start voltage of rising memory cell and provide the 3rd bias voltage to settle grid by second bias voltage to memory cell, it for example is charge balance pulse (chargebalancing pulse) that above-mentioned the 3rd bias voltage is settled, and settles with second bias voltage with above-mentioned first bias voltage and settles acting in conjunction.Above-mentioned the 3rd bias voltage is settled can produce first electron motion and second electron motion.If grid has a negative voltage to substrate, first electron motion be by grid to charge-trapping structure (injection of electronics grid), and second electron motion is to substrate (electronics is injected into passage) by the charge-trapping structure.When start voltage increased, the first electron motion rate reduced.Or when start voltage reduced, the first electron motion rate raise.When start voltage increased, the second electron motion rate increased.Or when start voltage reduced, the first electron motion rate reduced.Above-mentioned electron motion can make start voltage converge to target start voltage (targetthreshold voltage).The present invention also comprises that bias voltage settles, and it can balancing charge catches the CHARGE DISTRIBUTION in the layer, and when start voltage during near the target start voltage, on the passage length of memory cell, electric charge can focus on a side or the opposite side of passage.
The present invention provides an integrated circuit on the other hand, in the middle of substrate, suprabasil memory cell are arranged, the control circuit that cooperates with memory cell.Each memory cell all have a start voltage with comprise charge-trapping structure, grid, with suprabasil source electrode and drain region.Control circuit comprises by first bias voltage settles the logic rules that reduce start voltage, settles the logic that promotes start voltage by second bias voltage, with the logic of using the arrangement of the 3rd bias voltage.The 3rd bias voltage settles generation first electronics to move, and moves with second electronics that causes start voltage to converge to the convergence magnitude of voltage.
Another embodiment provides an integrated circuit, in the middle of substrate, suprabasil memory cell are arranged, the control circuit that cooperates with memory cell.Each memory cell all have a start voltage with comprise charge-trapping structure, grid, with suprabasil source electrode and drain region.Control circuit comprises by first bias voltage settles the logic rules that promote start voltage, settles the corresponding command logic that reduces start voltage by second bias voltage, settles with the 3rd bias voltage.Settle by second bias voltage, reduce the start voltage of memory cell.The 3rd bias voltage settles generation first electronics to move, and second electronics that causes start voltage to converge to the convergence magnitude of voltage moves.
An embodiment provides an integrated circuit again, in the middle of substrate, suprabasil memory cell are arranged, the control circuit that cooperates with memory cell.Each memory cell all have a start voltage with comprise charge-trapping structure, grid, with suprabasil source electrode and drain region.Control circuit comprises by first bias voltage settles the logic rules that reduce start voltage.First bias voltage is settled the motion of initiation hole, first electronics moves and second electronics moves.About the hole motion, the hole moves on to the charge-trapping structure and reduces the interior start voltage of memory cell.Because the motion of electric charge, start voltage converge to a convergence magnitude of voltage.
In certain embodiments, the 3rd bias voltage is settled the hole is shifted out from electric charge capture layer.Illustrate, the electron motion that enters the charge-trapping structure causes the hole that is captured to combine again with electronics in the charge-trapping structure.
In certain embodiments, before any lifting or reducing the cycle of start voltage, the charge balance bias voltage is settled and is applied in the charge-trapping structure, as balancing charge.Illustrate, before the cycle of any lifting or reduction start voltage, the increase of electronics can promote start voltage.Among one embodiment, before the cycle of any lifting or reduction start voltage, the start voltage of this lifting is than settling getable minimum start voltage also low with second bias voltage for the first time.Among another embodiment, before the cycle of any lifting or reduction start voltage, the start voltage of this lifting is also lower with the verifying voltage of erasing than program verification voltage.
At the embodiment of this description technique, comprise a memory cell operation method in conjunction with the charge-trapping structure.The method promotes in the start voltage of memory cell, has comprised by first bias voltage and settled the start voltage that reduces memory cell utilizing second bias voltage to settle.As if through after a while, the start voltage of central majority promotes with the reduction cycle and takes place or will take place, the 3rd bias voltage is settled and is used to postpone the interior lotus distribution equilibrium of charge-trapping structure.When the charge balance operational applications in this section in the period, a pulse (for example being 1 second among the Yi Xia embodiment) relatively for a long time makes memory cell can reach poised state or almost reaches poised state.Time-histories between the charge balance operation of using the arrangement of the 3rd bias voltage, it can be determined because of the application of various different specific process.For example, above-mentioned time-histories can utilize timer to calculate, the charge balance operation in rule time period.Or above-mentioned time-histories can be programmed and the counting of erase period decides.Or, also can utilize other factors, comprise power initiation and close or other similar mode, come the passage of time (lapse of time) of display element operation.
Embodiments of the invention comprise the method for operation of memory cell, set up low start voltage state to use first technology (for example erasing), it comprises the arrangement of first bias voltage, be used for reducing the negative electrical charge of charge-trapping structure, and second bias voltage settle, be used between grid and charge-trapping structure and in charge-trapping structure and interchannel, causing the balancing charge tunnelling.Second technology (for example programming) is set up the high start voltage state of memory cell, and the 3rd bias voltage that wherein comprises the negative electrical charge increase that causes in the electric charge capture layer is settled.In the technology of setting up low start voltage state, the charge balance pulse is provided, wherein the charge balance pulse may not reach poised state because of the time is too short, so would rather the time enough for a long time (embodiment of back is with 50 to 100 milliseconds) reaching start voltage, and the interior charge balance of charge-trapping structure.
Charge balance described herein can be carried out in any technology with the technology of erasing, and for example can be applied in the response technique that starts the process instruction of erasing, and cans be compared to section and erases.Use the process of erasing of charge balance operation, when this operation can be used for shorter charge balance pulse, pulse did not need to reach poised state but the interior CHARGE DISTRIBUTION balance of tendency balancing charge capturing structure.Illustrate, cause because of the negative electrical charge in the charge-trapping structure in charge balance pulse tendency, and the Cheng Qian of erasing of bigger electronics exit flow before causing the hot hole injection to be flowed, one short relatively charge balance pulse can make the erased status start voltage distribute tight (tighten), allow erase easier.If intercourse, because of the more positive charges in the charge-trapping structure, make charge balance pulse tendency cause that bigger electronics injects the process of erasing of stream after, a short relatively charge balance pulse can neutralize and catch the hole and improve electric charge and preserve.
For the flash memory component of similar nitrogenize read-only memory (NROM-like), the hot hole process of erasing can be used for the section of erasing.In the embodiments of the invention, add charge balance technology and combine the hot hole technology of erasing.Because charge balance technology has the characteristic of oneself's convergence, can help to promote the start voltage and the start voltage that reduces the difficult memory cell of erasing of the memory cell of erasing.Similarly, use the charge balance operation and can make, reach the tight effect of target start voltage distribution by low start voltage state storage unit array.For the memory cell of silicon oxide nitride oxide silicon (SONOS), wear then in conjunction with the FN of charge balance pulse, can be applicable to the technology of erasing.
Other method is to select by erasing in conjunction with charge balance and hot hole, and when the negative-gate voltage bias voltage arrangement of charge balance, that opens source electrode and drain electrode a little engages bias voltage (junction bias).In this situation, hot hole injects, and grid injects with electron back seizure (de-trapping) and carries out simultaneously.Compare with traditional hot hole erasing method, this kind mixes erasing method and shows durability degree and reliability preferably.
The present invention discloses the intelligent rule of erasing.The user can design suitable charge balance and erase sequence, to obtain good durability degree and reliability.Charge balance technique based on the negative-grid tunnelling injects and other bias voltage arrangement in conjunction with hot hole, reaches preferable erased status starting resistor and the acceptable speed of erasing.For crossing erase unit (over-erased cell) and the difficulty unit (hard-to-erasecell) of erasing, charge balance/hot hole is erased and can be restrained both starting resistors simultaneously.
Charge balance operation can be used as electronics annealing process (electrical annealing step) and neutralizes and catch hole (hole trap), improves the element reliability greatly.
Charge balancing method and erasing method can be combined in any stage in the technology of erasing, or can start simultaneously.
Other method embodiment also provides multiple bias voltage to settle.Settle by first bias voltage, can improve the starting resistor of memory cell.The second and the 3rd bias voltage is settled, and is used to the instruction that starting resistor falls in correspondence.Settle by second bias voltage, can reduce the starting resistor of memory cell.The 3rd bias voltage is settled and is comprised a charge balance pulse, is used to cause starting voltage and converges to a convergency value.In certain embodiments, correspond to the instruction that reduces starting resistor, second bias voltage is settled the back to implement the 3rd bias voltage and is settled.In certain embodiments, in order to correspond to the instruction that reduces starting resistor, the 3rd bias voltage is settled and can be implemented before second bias voltage is settled in advance.In certain embodiments, in order to correspond to the instruction of reduction starting resistor, the meeting of arrangement of the 3rd bias voltage shifts to an earlier date before second bias voltage is settled and all implements afterwards.The embodiment that also has other, in order to correspond to the instruction that reduces starting resistor, charge balance the 3rd bias voltage is settled and can be settled synchronization implementation with second bias voltage simultaneously.
Another embodiment provides integrated circuit, the control circuit that it comprises substrate, suprabasil memory cell and is coupled with memory cell.Each memory cell has a starting resistor and comprises charge-trapping structure, grid and be positioned at suprabasil source electrode and drain region.Control circuit comprises by first bias voltage settles the logic rules that promote starting resistor (programming), and settles the counterlogic rule that reduces starting resistor instruction by the second and the 3rd bias voltage.Settle by second bias voltage, the starting resistor of memory cell is lowered.The 3rd bias voltage is settled the balance that causes charge movement, makes starting resistor converge to a target start magnitude of voltage.
In certain embodiments, any lifting with reduced starting resistor before the cycle, the charge balance bias voltage is settled and is applied to the electric charge that increases the charge-trapping structure.For example, any lifting with reduced starting resistor before the cycle, in the charge storing unit capturing structure, the electronics increase of balanced distribution can promote the starting resistor of memory cell.
According to the programming rule of this technology implementation example, comprise the retry period (refill cycle) of electronics seizure spectrum in the charge-trapping structure that changes storage device.Continue and be used to be inclined to after the short charge balance pulse that causes the shallow seizure electronics ejaculation in the charge-trapping structure, retry procedure comprises applied bias voltage settles and increases electricity and catch negative electrical charge in the structure, repeats the negative electrical charge that these bias voltages are settled to be increased in the charge-trapping structure.One or more retry period is used to increase the relevant distribution of catching electronics in the charge-trapping structure more deeply, and is used to keep the target voltage of programming process.The anti-capturing efficiency of shallow energy rank electronics, tendency is faster than dark energy rank electronics.After the charge balance pulse, starting resistor descends, and the programming of electric charge or retry are to be applied on the element then, so that element revert to original program verification start voltage grade.The repeating of charge balance/retry procedure can cause catching spectrum to the skew of dark level electronics, and this phenomenon is named " spectrum is blue to be offset ".Retry procedure can significantly be improved the electric charge preservation effect, even because of programmings and erase period cause the element of great damage also helpful in a large number.Therefore, retry procedure provides the electric charge preservation effect that effective technology is improved the charge-trapping memory element.Further, cooperate retry method, thin dielectric layer also can be used as the top dielectric layer of end dielectric layer, charge-trapping structure and no loss of charge.Thin dielectric layer helps to dwindle electric fishing and catches device size.
Another is executed example one integrated circuit is provided, and it comprises substrate, and memory cell is positioned in the substrate, and control circuit, is coupled to memory cell.Each memory cell has start voltage, and comprises that charge-trapping structure, grid, source electrode and drain electrode are arranged in above-mentioned substrate.Above-mentioned control circuit comprises by retry technology to improve the logic rules of start voltage (programming).
The target start voltage of charge balance operation can decide according to following many parameters, comprise a considerable amount of electric charge tunnellings, this electric charge tunnelling is passed through the top dielectric layer and the charge-trapping structure that arrives from grid, and passes through end dielectric layer and the channel region that arrives from the charge-trapping structure.One being example than the low target start voltage, the injection current that electron tunneling produced from grid to the charge-trapping structure, the ejaculation electric current that electron tunneling produced from the charge-trapping structure to passage also come lowly.In embodiments of the present invention, above-mentioned electric current reduces and can reach with the tunnelling that suppresses the top dielectric layer by the grid material with high work function.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
1A figure illustrates the schematic diagram of charge capturing storage unit before any programming and erase period.
1B figure illustrates the schematic diagram of charge capturing storage unit increase balanced distribution electric charge before programming and erase period of 1A figure.
2A figure illustrates the schematic diagram of charge capturing storage unit after multiple programming and erase period.
2B figure illustrates the schematic diagram of 2A figure charge capturing storage unit after the CHARGE DISTRIBUTION balance.
3A figure illustrates the schematic diagram of charge capturing storage unit after the CHARGE DISTRIBUTION balance.
3B figure illustrates the schematic diagram of the charge capturing storage unit of 3A figure through the channel hot electron injection.
3C figure illustrates the schematic diagram of the charge capturing storage unit genital areas interband tunnelling hot hole injection of 3B figure.
3D figure illustrates the schematic diagram of the charge capturing storage unit of 3C figure through the CHARGE DISTRIBUTION balance.
The 4th figure illustrates charge capturing storage unit after multiple programming and erase period, the flow chart that CHARGE DISTRIBUTION changes.
The 5th figure illustrated before programming and erase period, increased electric charge to charge capturing storage unit, and after programming and erase period, the flow chart that CHARGE DISTRIBUTION changes in the charge capturing storage unit.
The 6th figure illustrates start voltage with respect to programming and erase period number, and the schematic diagram of the start voltage before and after relatively CHARGE DISTRIBUTION changes.
The 7th figure illustrates start voltage with respect to programming and erase period number, and shows that CHARGE DISTRIBUTION changes the schematic diagram of back start voltage consistency (consistency).
The 8th figure illustrates start voltage with respect to the erase period number, and relatively under low start voltage, has/schematic diagram of erase operation for use efficient during no CHARGE DISTRIBUTION change.
The 9th figure illustrates start voltage to change with respect to hold time (retention time), and relatively not programmed and an erase period memory cell with through the schematic diagram of programming repeatedly with the memory cell of erase period.
The 10th figure illustrates start voltage to change (delta threshold voltage) with respect to holding time, and increases electric charge earlier before programming and erase period, then through the schematic diagram of different numbers programmings with the memory cell of erase period.
The 11st figure illustrates to increase the flow chart of electric charge to memory cell before programming and erase period, and after the programming and erase period of a period of time, the schematic diagram that CHARGE DISTRIBUTION changes in the memory cell.
The 12nd figure illustrates the calcspar of integrated circuit according to an embodiment of the invention.
The 13rd figure illustrates the periodic packets of erasing to draw together the flow chart of equalizing pulse.
The 14th figure illustrates the flow chart that another erase period comprises equalizing pulse.
The 15th figure illustrates the corresponding time of start voltage, and the schematic diagram that compares the efficient that start voltage is saturated under different grid voltages.
The 16th figure and the 17th figure illustrate the corresponding time of start voltage, and the schematic diagram that shows CHARGE DISTRIBUTION change bias voltage in the corresponding charge-trapping structure of storage unit starting voltage convergence situation.
The 18th figure illustrates the corresponding time of start voltage, and the schematic diagram that shows its start voltage convergence situation of memory cell of the different passage lengths of tool.
The 19th figure illustrates the programming of the even CHARGE DISTRIBUTION change of the corresponding tool of start voltage and the schematic diagram of erase period number.
The 20th figure illustrates start voltage the correspondence not programming that changes of the even CHARGE DISTRIBUTION of tool and the schematic diagram of erase period number.
The 21st figure is that start voltage changes corresponding schematic diagram of holding time, and the memory cell that changes of contrast tool and the even CHARGE DISTRIBUTION of tool not.
The 22nd figure illustrates the schematic diagram that utilizes the charge capturing storage unit that mixes bias voltage, wherein mixes the CHARGE DISTRIBUTION that bias voltage can reduce storage unit starting voltage simultaneously and change electric charge capture layer.
The 23rd figure illustrates the corresponding time of start voltage, and relatively the tool difference is mixed the schematic diagrames of the memory cell of bias voltage.
The 24th figure and the 25th figure illustrate to reduce before and after the start voltage process schematic diagram that CHARGE DISTRIBUTION changes in the electric charge capture layer.
The 26th figure illustrates to provide one to mix the schematic diagram of bias voltage with the operation store unit, wherein mixes CHARGE DISTRIBUTION and the start voltage that reduces memory cell that bias voltage can change electric charge capture layer simultaneously.
The 27th figure is the flow chart that illustrates the programming operation of tool retry period of the present invention (refill cycle).
The 28th figure illustrates the start voltage correspondence to erase the time schematic diagram of the charge balance pulse of the programming operation of tool retry period.
The 29th figure illustrates according to the 28th diagram data, the schematic diagram of the corresponding programming operation embodiment of start voltage retry period.
The 30th figure is the charge balance pulse that illustrates at a programming operation embodiment, the erase schematic diagram of time of start voltage correspondence.
The 31st figure illustrates according to the 30th diagram data, the schematic diagram of the corresponding programming operation embodiment of start voltage retry period.
The 32nd figure is the memory cell that illustrates having under retry operation and the no retry operation, the feature schematic diagram that its data are preserved.
The 33rd figure is energy rank (energy level) schematic diagram that illustrates charge capturing storage unit of the present invention.
[main element label declaration]
110,210,310: grid
120: the top dielectric structure
130,230,330: the charge-trapping structure
140: end dielectric structure
150,160,250,260:n+ type ion doped region
170,270,370:p type ion doped region
220,320,340: oxide layer
350: source electrode
360: drain electrode
332: electronics
333,334: the hole
410,510,1110,2410,2510,2610: new memory cell (new cell)
420,520,2420,2520,2620: memory cells (program cell)
430,530,2430,2530: the memory cell of erasing (erase cell)
440,540,1140: decision is programmed and the erase period time finishes? (End of programand erase cycle interval?)
450,515,550,1115,1150,1306,1401,1407,2440,2525,2630,2707: provide bias voltage to settle with balancing charge (Apply bias arrangement for chargebalancing)
1120: programming and imminent time started of erase period (Begin interval withinwhich program and erase cycles are likely to occur)
1250: integrated circuit
1200: memory array
1201: column decoder (row decoder)
1202: word line
1203: row decoder (column decoder)
1204: bit line
1205,1207: bus
1206: induction amplifier/data input structure (sense amplifier/data-instructure)
1208: bias voltage is settled provides voltage
1209: bias voltage is settled stater
1211: Data In-Line (data-in line)
1212: DOL Data Output Line (data-out line)
1300,1400: the order of erasing (erase command)
1301,1402: provide bias voltage to settle to cause that hot hole injects
1302,1307,1403,1408,2702: not by checking? (pass verify?)
1308,1409: erase and finish (erase done)
1305,1406,2705: failure
2700: program command (program command)
2701: provide bias voltage to settle to cause that electronics injects
2709: (program done) finished in programming
Embodiment
Please refer to 1A figure, it illustrates the schematic diagram of charge-trapping (charge trapping) memory cell (memorycell).Substrate comprises n+ type ion doped region (n+doped region) 150 and 160 among the figure, and p type ion doped region (p-doped region) 170, and they are between n+ type ion doped region 150 and 160.Memory cell also comprises end dielectric structure (bottom dielectric structure) 140, charge-trapping structure (charge trapping structure) 130, top dielectric structure (topdielectric structure) 120 and grid 110, wherein above-mentioned end dielectric structure 140 is positioned in the substrate, charge-trapping structure 130 be positioned at bottom oxide (bottomoxide), top dielectric structure 120 on the end dielectric structure 140 be positioned at top oxide layer (top oxide) on the charge-trapping structure 130, to be positioned on the top dielectric structure 120 with gate pole 110.The top dielectric layer is the silicon dioxide (silicon dioxide) and silicon oxynitride (siliconoxynitride) or other similar high-k material, for example alundum (Al (Al of about 5 to 10 nanometers (nanometers) of a thickness preferably
2O
3).End dielectric layer is silicon dioxide and silicon oxynitride or other similar high-k material of about 3 to 10 nanometers of thickness preferably.Electric charge capture layer preferably silicon nitride (siliconnitride) or other similar high-k material of about 3 to 9 nanometers of thickness comprises metal oxide, for example alundum (Al (Al
2O
3), HfO
2Or the like.The charge-trapping structure can be discontinuous accumulate bag (pocket) or the particle of charge-trapping material or pantostrat as shown in the figure.Charge-trapping structure 130 has the electric charge that is captured, and for example electronics 131.
For example, the memory cell of nitrogenize read-only memory unit (NROM-like cell) has the bottom oxide of 3 to 10 nanometer thickness, the electric charge capture layer of 3 to 9 nanometer thickness and the top oxide layer of 5 to 10 nanometer thickness.For example, the memory cell of silicon oxide nitride oxide silicon (SONOS) unit has the bottom oxide of 1 to 3 nanometer thickness, the electric charge capture layer of 3 to 5 nanometer thickness and the top oxide layer of 3 to 10 nanometer thickness.
In certain embodiments, the work function of grid material (work function) needs the essential work function (intrinsic work function) than n type silicon also big or greater than 4.1 electron-volts (eV), preferably, comprise greater than about 5 electron-volts greater than about 4.5 electron-volts.Preferable grid material comprises p type polysilicon (p-type poly), titanium nitride (TiN), metal nitride, and the metal of other big work function and material.In addition, other is applicable to the material with big relatively work function of present embodiment, also comprise metal for example ruthenium (Ru), iridium (Ir), nickel (Ni) and cobalt (Co) etc., and comprise metal alloy for example ruthenium nickel alloy and Nitinol etc., and comprise for example ruthenic oxide (RuO of metal nitride, metal oxide
2), but be not defined as the above-mentioned metal of mentioning, metal alloy and metal oxide.The high work function grid material can produce higher injection barrier (injection barriers) to electron tunneling (electron tunneling) than traditional n type polysilicon bar utmost point.With silicon dioxide is the n type polysilicon bar utmost point of top dielectric layer, and its injection barrier is approximately 3.15 electron-volts.So the embodiment of the invention is used for the material of grid and top dielectric layer, have and be higher than 3.15 electron-volts injection barrier, for example be higher than 3.4 electron-volts, preferably be higher than 4 electron-volts.It with silicon dioxide the p type polysilicon bar example very of top dielectric layer, injection barrier is approximately 4.25 electron-volts, the start voltage (threshold) of the convergence unit (convergedcell) that it produced, the n type polysilicon bar utmost point that can with silicon dioxide be the top dielectric layer reduce about 2 volts, after 1B figure can more go through.
In 1A figure, not through programming and erase period, for example, the electric charge that is captured only is the product of manufacture of semiconductor to memory cell as yet.In memory cell array, the quantity of the electric charge that is captured that manufacturing operation produced can arbitrarily change.
Sentence general use with this, programming cycle preferably improves the start voltage of memory cell, and erase period preferably reduces the start voltage of memory cell.Yet the product and the method for above-mentioned two steps are contained in the present invention, and comprise product and method that programming cycle reduces storage unit starting voltage and erase period raising storage unit starting voltage two steps.
Please refer to 1B figure, it illustrates the schematic diagram of the charge capturing storage unit of 1A figure, and wherein electric charge is added to before programming and the erase period.Current potential 0V places in source electrode 150, drain electrode 160 and the substrate 170, and current potential-20V places on the grid 110, and it can provide bottom oxide one about 0.7 to 1.0 volt/nanometer (Volts/nm) or bigger electric field.This bias voltage is the CHARGE DISTRIBUTION that is used for balancing charge capturing structure 130, it is by the electron injection current (electron injectioncurrent) of conducting from the grid to the electric charge capture layer, and conducting electronics of (channel) from the electric charge capture layer to the passage penetrates electric current (electron ejection current), after time enough arrives a dynamic balance, this moment, the start voltage of memory cell can converge to target (target) start voltage, distributed and produce charge balance in passage length.In memory cell channel, this bias voltage is symmetrical distribution haply.When memory cell originally had a little charge, this bias voltage can increase electric charge, and for example electronics 132, in charge-trapping structure 130.Yet before element was programmed and erases, the charge-trapping amount of charge-trapping structure can be changed in the memory cell array.The bias voltage of 1B figure, the charge-trapping amount of meeting equilibrium establishment in memory cell is in reasonable endurable scope.The target start voltage of 1B figure bias voltage is the equilibrium condition that penetrates electric current according to electron injection current and electronics.The balance of the charge-trapping amount of charge-trapping structure can be kept certain value under bias condition.According to top oxide layer, bottom oxide, grid and charge-trapping structure, when reaching the dynamic equilibrium condition, the start voltage of memory cell is the function of electric nuclear amount in the charge-trapping structure.Equilibrium condition preferably, the electronics of grid penetrates electric current greater than electron injection current, makes the target start voltage reduce.When can allowing reading cells, lower target start voltage under lower operating voltage, carries out.So the embodiment of the invention is utilized the grid material of high work function, for example p doped polycrystalline silicon, or high-k top oxidation material, for example Al
2O
3, or in conjunction with above-mentioned both, to reach lower target start voltage.
The grid of equalizing pulse among the embodiment (balancing pulse) is effective oxide thickness (the effective oxide thickness according to the dielectric stack layer to bias voltage (gate-to-substrate bias) size of substrate; EOT) determine.Above-mentioned dielectric stack layer comprises top dielectric layer, charge-trapping structure and end dielectric layer, and effective oxide thickness is meant at silicon dioxide permittivity (permittivity) and makes thickness after the normalized (normalized).For example, when top dielectric layer, charge-trapping structure and end dielectric layer comprised silicon dioxide, silicon nitride, silicon dioxide respectively, this stack architecture was oxygen nitrogen oxygen stack layer (ONO stack).With oxygen nitrogen oxygen stack layer is example, and effective oxide thickness (EOT) promptly equals the top oxidated layer thickness, adds bottom oxide thickness, adds that nitration case thickness multiply by the silica permittivity and divided by the silicon nitride permittivity.So the bias voltage of nitrogenize read-only memory unit (NROM-likecell) and silicon oxide nitride oxide silicon (SONOS) charge storing unit equalizing pulse (chargebalancing pulse) can determine as follows:
1. the bottom oxide thickness of the nitrogenize read-only memory unit that herein is described to (NROM-like cell) is greater than 3nm, the dielectric stack layer has effective oxide thickness (for example 10nm is to 25nm), and bottom oxide thickness is to be used to avoid the direct Tunneling (direct tunneling) of hole from substrate greater than 3nm.Grid to substrate have a bias voltage (for example-12Volts to-24Volts), and voltage divided by effective oxide thickness system greater than 0.7V/nm, preferably about 1.0V/nm adds and subtracts 10%.
The effective oxide thickness of the oxygen nitrogen oxygen layer (ONO) of nitrogenize read-only memory unit is calculated as follows:
The minimum value maximum
Top oxidated layer thickness (permittivity=3.9) 5nm 10nm
Silicon nitride layer thickness (permittivity=7) 3nm 9nm
Bottom oxide thickness (permittivity=3.9) 3nm 10nm
Amount to 5+3*3.9/7+3=10nm 10+9*3.9/7+10=25nm
2. the bottom oxide thickness of the silicon oxide nitride oxide silicon that herein is described to (SONOS) memory cell is less than 3nm, the dielectric stack layer has an effective oxide thickness (for example 5nm is to 16nm), and bottom oxide thickness is to allow the direct Tunneling of hole from substrate less than 3nm.Grid to substrate have a bias voltage (for example-5Volts to-15Volts), and voltage is greater than 0.3V/nm divided by effective oxide thickness, preferably about 1.0V/nm adds and subtracts 10%.
The effective oxide thickness of the oxygen nitrogen oxygen layer (ONO) of silicon oxide nitride oxide silicon memory cell is calculated as follows:
The minimum value maximum
Top oxidated layer thickness (permittivity=3.9) 3nm 10nm
Silicon nitride layer thickness (permittivity=7) 3nm 5nm
Bottom oxide thickness (permittivity=3.9) 1nm 3nm
Amount to 3+3*3.9/7+1=5.7nm 10+5*3.9/7+3=15.8nm
For the material that is different from silicon dioxide and silicon nitride, the calculating of effective oxide thickness is the same, and the normalization of this material thickness is according to the value of silicon dioxide permittivity divided by this material permittivity.
2A figure system illustrates the schematic diagram of charge capturing storage unit after multiple programming and erase period.Wherein, substrate comprises n+ doped region 250 and 260, and p doped region 270, and they are between n+ doped region 250 and 260.Memory cell also comprises and is positioned at suprabasil oxide layer 240, is positioned at the electric charge capture layer 230 on the oxide layer 240, and another oxide layer 220 is positioned on the electric charge capture layer 230, and is positioned at the grid 210 on the oxide layer 220.Owing to the bias voltage that programming and erase period are required is different, and because when using the channel hot electron injection method, particularly erase period district's interband tunnelling that can not influence causes when hot electron injects (band-to-band tunneling induced hot electron injection), electronics can be trapped in the electric charge capture layer 230, multiple programming and erase period are stayed the electric charge that is captured in the electric charge capture layer 230, for example electronics 231 and 232.
2B figure illustrates 2A figure charge capturing storage unit, changes the back and schematic diagram after 1B schemes described bias voltage is provided in CHARGE DISTRIBUTION.In this example, voltage 0V places in source electrode 250, drain electrode 260 and the substrate 270, and voltage-20V places on the grid 210.Bias voltage can be used for the CHARGE DISTRIBUTION in the balancing charge seizure layer 230 herein, it is by removing unnecessary electronics after programming and erase period, for example electronics 232, or bring out from grid 210 to electric charge capture layer 230 electron injection current, or bring out from electric charge capture layer 230 to grid 210 electronics and penetrate electric current, behind time enough, it can cause the dynamic equilibrium or the balance of power at last, and the start voltage of memory cell can converge to the target start voltage, distributes so produce charge balance in passage length.Above-mentioned bias voltage on memory cell channel roughly is symmetrical distribution.
Method having thus described the invention comprises the start voltage that reduces memory cell by first bias voltage, improves the start voltage of memory cell by second bias voltage, and provides grid three bias voltage corresponding with first and second bias voltages.Above-mentioned the 3rd bias voltage can cause first motion and second motion of electronics.If grid has a negative voltage to substrate, first motion of electronics is from the grid to the electric charge capture layer, and second motion of electronics is from the electric charge capture layer to the substrate.If grid has a positive voltage to substrate, first motion of electronics is from the substrate to the electric charge capture layer, and second motion of electronics is from the electric charge capture layer to the grid.When start voltage raise, first rate of motion of electronics reduced, otherwise when start voltage reduced, first rate of motion of electronics increased.And when start voltage raise, second rate of motion of electronics also increased, otherwise when start voltage reduced, second rate of motion of electronics also reduced.Above-mentioned electronic motion can make start voltage converge to a desired value.Bias voltage is the CHARGE DISTRIBUTION that is used to be equilibrated in the electric charge capture layer, when start voltage during near this desired value, and in the passage length of memory cell, the also corresponding side that focuses on passage of electric charge.
3A-3D figure is after illustrating the CHARGE DISTRIBUTION of multiple programming and erase period, stays electric charge is caught layer in charge storing unit schematic diagram.
3A figure illustrates the schematic diagram of charge capturing storage unit after the CHARGE DISTRIBUTION balance.Wherein, substrate comprises n+ doped region 350 and 360, and p doped region 370, and they are between n+ doped region 350 and 360.Memory cell also comprises and is positioned at suprabasil oxide layer 340, is positioned at the electric charge capture layer 330 on the oxide layer 340, and another oxide layer 320 is positioned on the electric charge capture layer 330, and is positioned at the grid 310 on the oxide layer 320.
3B and 3C figure illustrate memory cell to settle schematic diagram in the programming and the bias voltage of erase period respectively.
3B figure system illustrates the schematic diagram of the memory cell of 3A figure through channel hot electron (CHE) injection.Voltage 0V places on the source electrode 350, and voltage 5.5V places in the drain electrode 360, and voltage 8V places on the grid 310.Bias voltage can produce channel hot electron herein, and for example electronics 332, and electronics 332 can be by the channel transfer of p doped region 370 zone near drain electrode 360 in the electric charge capture layer 330.Electronics 331 is the example that is sent to electric charge capture layer 330 through injection.Bias voltage as for other is settled, and for example sets up high start voltage state or via the multiple high start voltage state of multiple operation, then is exposed among other the embodiment.Representational bias voltage is settled and is comprised that passage initialization secondary electron injects (channel initiatedsecondary electron injection; CHISEL), source terminal is injected (source sideinjection; SSI), the drain avalanche hot electron injects (drain avalanche hot electroninjection; DAHE), pulse wave swashs towards substrate hot electron injection (pulse agitated substrate hotelectron injection; PASHEI), the postivie grid electric field is assisted (Fowler-Nordheim) tunnelling (positive gate E-field assisted tunneling) and other bias voltage arrangement etc.
3C figure is that the memory cell genital areas interband tunnelling that illustrates 3B figure causes the schematic diagram that hot hole injects.Voltage-3V places on the grid 310, and voltage 0V places on the source electrode 350, and voltage 5.5V places in the drain electrode 360, and voltage 0V places on the p doped region 370 of substrate.The bias voltage district interband tunneling effect that can pass through hole (for example the hole 334) produces hot electron and injects herein, and hole 334 can be sent in the electric charge capture layer 330 zone near drain electrode 360 by drain electrode 360.Hole 333 is the example of catching through injection at electric charge capture layer 330.The hole iunjected charge is caught layer 330 and the zone of reduction electron concentration, and zone incomplete and that electronics injects is complementary.Therefore, after repeatedly programming and erase period, just have some electron concentrations and be accumulated in the electric charge capture layer 330, this kind situation can be disturbed reaching of low start voltage state, or reduces the durability of element.The bias voltage of other erase period (for setting up the bias voltage of low start voltage state) comprise the negative-grid electric field assist tunnelling (produce the voltage that electronics penetrates and can't cause from the effective electronics of grid and inject), electronics by the electric charge capture layer direct Tunneling to bottom oxide or hole by the bottom oxide direct Tunneling to electric charge capture layer or the like.
3D figure illustrates the schematic diagram that can reach minimum start voltage when the electron concentration 335 that is captured in the memory cell of 3C figure is not influenced by injected hole.By the bias voltage of the charge balance shown in 1B figure is provided, the electron distributions of electric charge capture layer can change, and the seizure electric charge that reduces or erase unnecessary distributes to reach charge balance.In this example, when voltage-20V places on the grid 310, in channel region by the voltage of grid to substrate, value divided by the effective oxide thickness (EOT) of top dielectric layer, charge-trapping structure and end dielectric layer, for nitrogenize read-only memory unit (NROM-like cells), this value is greater than 0.7V/nm, preferably about 1V/nm; For silicon oxide nitride oxide silicon (SONOS) unit, this value is greater than 0.3V/nm, preferably about 1V/nm.Voltage 0V places source electrode 350, drain electrode 360 and part substrate 370 for example on the passage.This bias voltage can produce the change of electron distributions in electric charge capture layer 330, the change of electron distributions comprises that unnecessary electric charge is removed, with and/or increase electronics.Assist mobile mechanisms such as tunnelling by electric field, electric charge, for example electronics 331, can be sent to electric charge capture layer 330 by grid 310.Above-mentioned electric charge is the hole of being caught in electric charge capture layer 330 mending, and for example electronic 333 remove.Assist mobile mechanisms such as tunnelling by electric field, electric charge, for example electronics 335, then can catch the zone of injecting away from the hole by being mended originally, are sent to the p doped region 370 from electric charge capture layer 330.In fact, the electric field that produced under this bias voltage is assisted tunnelling, can be by electric charge capture layer 330 to channel region and pass whole passage.This bias voltage can be equilibrated at the CHARGE DISTRIBUTION of electric charge capture layer 330, by removing unnecessary electronics after programming and erase period, for example electronics 335, or bring out electron injection current from the grid to the electric charge capture layer, or the electronics that brings out from the electric charge capture layer to the grid penetrates electric current, and behind time enough, it can cause the dynamic equilibrium or the balance of power at last, and the start voltage of memory cell can converge to the target start voltage, distributes so produce charge balance in passage length.Above-mentioned bias voltage on memory cell channel roughly is symmetrical distribution.If bias voltage is provided as a long pulse ripple, about 0.5 to 1.0 second degree, charge balance distributes can be shown in 3A figure; If bias voltage is provided as a short pulse wave, the degree of about 1 to 50 millisecond (millisecond), CHARGE DISTRIBUTION possibly can't reach the state of balance.
The 4th figure illustrates at charge capturing storage unit after programming and erase period the flow chart that CHARGE DISTRIBUTION changes.New memory cell 410 does not experience programming and erase period as yet.In step 420 and 430, memory cell can be programmed and erase by first and second bias voltages.Does the time-histories (interval) that need determine to programme and erase finish in step 440? above-mentioned time-histories is that the number by calculation and programming and erase period decides.If time-histories finishes as yet, then memory cell experiences the programming and the erase period of step 420 and 430 once more.Otherwise, in step 450, settle by the 3rd bias voltage, CHARGE DISTRIBUTION can be changed in the memory cell, this moment in channel region by the voltage of grid, divided by the value of the effective oxide thickness (EOT) of top dielectric layer, charge-trapping structure and end dielectric layer, for nitrogenize read-only memory unit (NROM-like cells) to substrate, this value is greater than 0.7V/nm, preferably about 1V/nm; For silicon oxide nitride oxide silicon (SONOS) unit, this value is greater than 0.3V/nm, preferably about 1V/nm.
At different embodiment, first bias voltage and second bias voltage can produce one or repeatedly electric field assists that tunnelling, hot electron inject that for example channel hot electron (CHE) is injected, passage initialization secondary electron injects (CHISEL) and/or hot hole and inject and for example distinguish the interband tunnelling and cause that hot hole injects (BTBTHH) respectively.In the bias voltage of difference was settled, the electric charge mobile mechanism can be identical, can also be different.Yet, even the electric charge mobile mechanism is identical in different bias voltages is settled, first bias voltage, second bias voltage are equipped with different bias voltages in memory cell respectively with the 3rd bias voltage, also have different from voltage (combination of voltages) respectively at each end points of memory cell.
During the more disclosed embodiment of the present invention comprised: in memory cell, it was that negative voltage is placed on the grid with respect to source electrode, drain electrode and substrate that the 3rd bias voltage is settled; First bias voltage is settled and is produced the hot hole injection; And second bias voltage settle to produce hot electron and inject.Or first bias voltage is settled and is produced the hot hole injection; Second bias voltage is settled and is produced the hot electron injection; And the 3rd bias voltage settle to produce electric field and assist tunnelling.Or first bias voltage is settled and is produced the hot hole injection; Second bias voltage is settled and is produced the hot electron injection; And the 3rd bias voltage to settle be that the negative voltage with respect to source electrode, drain electrode and substrate is placed on the grid, wherein, for nitrogenize read-only memory (NROM-like) unit, this negative voltage is greater than 0.7V/nm divided by the value of the effective oxide thickness (EOT) of dielectric stack layer; For silicon oxide nitride oxide silicon (SONOS) unit, this negative voltage is greater than 0.3V/nm divided by the value of the effective oxide thickness (EOT) of dielectric stack layer, preferably about 1V/nm.
The 5th figure illustrated before programming and erase period, increased electric charge to charge capturing storage unit, or after programming and erase period, the flow chart that CHARGE DISTRIBUTION changes in the charge capturing storage unit.This flow process and the 4th figure are quite similar.Yet, before programming and erase period, that is before step 520 and 530, in the step 515, electric charge is to increase in the memory cell by aforesaid charge balance pulse, after step 515, start voltage is less than programming and erase period start voltage afterwards, and less than the program verification voltage (program verify voltage) of memory cell and the verifying voltage (erase verify voltage) of erasing.
The 6th figure illustrates start voltage with respect to the schematic diagram of programming with the erase period number, and the schematic diagram of the start voltage before and after relatively CHARGE DISTRIBUTION changes.Before CHARGE DISTRIBUTION changed, memory cell had experienced the programming and the erase period of different numbers.The situation of data point 610 (hollow dots hollow dot) representative memory cell before CHARGE DISTRIBUTION changes, data point 610 comprises data set 630,640,650 and 660.Data set 630 expressions, before the operation of carrying out the CHARGE DISTRIBUTION change, memory cell experiences 500 times programming and erase period earlier.Data set 640 expressions, through after first programming and erase period of 1000 times, before the operation of carrying out the CHARGE DISTRIBUTION change, programming and erase period that the memory cell experience is 1000 times.Data set 650 expressions, through after first programming and erase period of 10,000 times, before the operation of carrying out the CHARGE DISTRIBUTION change, programming and erase period that the memory cell experience is 10,000 times.Data set 660 expressions, through after first programming and erase period of 100,000 times, before the operation of carrying out the CHARGE DISTRIBUTION change, programming and erase period that the memory cell experience is 50,000 times.Along with data set 630,640, the increase of 650 and 660 programming and erase period number, carry out the operation of CHARGE DISTRIBUTION change before, the start voltage of memory cell can increase.Data point 620 (solid dot solid dot) representative memory cell utilizes the bias voltage of 3D figure to settle the change situation of CHARGE DISTRIBUTION.Show among the figure that all data points 610 except data set 630, all surpass the verifying voltage 3.8V that erases, with line 670 expressions.Data set 660 all surmounts program verification voltage 5.3V, with line 680 expressions.Data set 630,640,650 and 660 show the interference in various degree to minimum start voltage in the memory cell.The operation that data point 620 demonstration CHARGE DISTRIBUTION change successfully reduces the start voltage of memory cell to erasing the verifying voltage line below 670, the data point after experience surpasses 1,000,000 programmings and erase period is not inconsistent.Show among the figure, along with the increase of programming, to the also and then increase of interference of minimum start voltage with the erase period number.So, the data that produced at the 6th figure, the charge balance bias voltage meeting target of 3D figure is in the scope that 1000 programmings and erase period take place, and the bias voltage of erasing of keeping memory cell is lower than the target start voltage, and this target start voltage is set by the verifying voltage of erasing (line 670).
The 7th figure illustrates storage unit starting voltage with respect to the schematic diagram of programming with the erase period number, and show the conforming schematic diagram of start voltage behind the charge balance bias voltage is provided, above-mentioned charge balance bias voltage is meant through 100 subchannel hot electrons and injects after (CHE) and district's interband tunnelling cause that hot hole injects (BTBTHH) programming and erase period, adds one and be about 0.5 second negative voltage pulse on grid.The start voltage of data point 710 (solid dot) representative behind programming operation, the start voltage of data point 720 (hollow dots) representative behind erase operation for use.As shown in FIG., this sentences through 1,000,000 programmings is example with erase period, all maintains below the 3.7V through the start voltage after the erase period.
The 8th figure illustrates the schematic diagram of start voltage with respect to the erase period number, and is relatively hanging down under the start voltage, has/effect of erase operation for use when no CHARGE DISTRIBUTION changes.The state of data point 810 (solid dot) representative memory cell before the negative electrical charge balancing run changes CHARGE DISTRIBUTION.Before the negative electrical charge balancing run, the start voltage of memory cell only can't fully reduce by erase pulses, even the erase pulses of having carried out many times also is the same.The state of data point 820 (hollow dots) representative behind the negative electrical charge balancing run.Show among the figure, the interference that the very fast removing of negative electrical charge balancing run is produced by programming and erase period, and the start voltage value is reduced effectively.
The 9th figure system illustrates start voltage and changes schematic diagram with respect to hold time (retention time), and relatively not programmed and an erase period memory cell with through the schematic diagram of programming repeatedly with the memory cell of erase period.Stitching (trace) 910 is represented the memory cell of not programmed and an erase period, so that electric charge is kept (charge retention) is fairly good.Data set 920 and 930 is represented once the memory cell of 150,000 programmings with erase period, and wherein per 900 programmings are just carried out the negative electrical charge balancing run one time with erase period.The memory cell that electric charge is kept detection is just carried out in data set 920 representatives at once behind the negative electrical charge balancing run.Relatively, the memory cell that electric charge is kept detection is just carried out in data set 930 representatives before the negative electrical charge balancing run.For accelerated charge is kept detection, add at grid-voltage of 10V, make it quicken to discharge the electronics that is captured from the charge-trapping structure.Because the bigger relatively poor electric charge of start voltage representative is kept, show among the figure that the negative electrical charge balancing run has improved charge storing unit and kept.
The 10th figure illustrates start voltage to change (delta threshold voltage) with respect to the schematic diagram of holding time, and before programming and erase period, carry out the negative electrical charge balancing run earlier, then through the schematic diagram of different numbers programmings with the memory cell of erase period.Data point 1000 (solid dot) is represented the memory cell of not programmed and an erase period.Data point 1010 (hollow triangle), data point 1020 (open squares) and data point 1030 (open diamonds) are represented experience 150 respectively, 000 programming and erase period, 200,000 programming and erase period and 1,000, the memory cell of 000 programming and erase period, wherein per 1000 programmings are just carried out the negative electrical charge balancing run one time with erase period.Electric charge is kept and detected is to carry out after the operation that CHARGE DISTRIBUTION changes at once.What can see is, to experiencing respectively 150,000 times, 200,000 times and 1,000, the memory cell of 000 programming and erase period is periodically carried out the negative electrical charge balancing run and can be produced stable haply electric charge and keep.
The 11st figure illustrates to increase the flow chart of electric charge to memory cell before programming and erase period, and the CHARGE DISTRIBUTION in the memory cell changes after a period of time.The still not programmed and erase period of one new memory cell 1110.In step 1115,, increase electric charge in memory cell by the charge balance pulse is provided.In step 1120, after a period of time, programming is about to take place with erase period.Settle by first and second bias voltages, programming takes place with erase period.In step 1140, whether this section period finishes in decision.If not, this section period then continues.The 3rd bias voltage is settled and to be comprised the negative-gate voltage pulse and at charge-trapping structure and interchannel ejaculation electric current, above-mentioned negative-gate voltage is the passage with respect to substrate, distribute with balancing charge by the injection current of grid, and above-mentioned ejaculation electric current passes whole passage in fact to passage.In certain embodiments, the pulse length that pulse has is that start voltage to the target that is enough to restrain memory array restrains start voltage, and the pulse length of pact-20V is between 0.5 to 1.0 second in this example.
The 12nd figure is the calcspar that illustrates the integrated circuit of one embodiment of the invention.Integrated circuit 1250 comprises memory array 1200, and it is included in local charge capturing storage unit at semiconductor-based the end.Column decoder (row decoder) 1201 couples with word line (wordline) 1202, and above-mentioned word line is to arrange along the row of memory array 1200 (row).Row decoder (column decoder) 1203 couples with bit line (bitline) 1204, and above-mentioned word line is to arrange along the row of memory array 1200 (column).Address (address) is to arrange to give row decoder 1203 and column decoder 1201 by bus (bus) 1205.Induction amplifier in square 1206 (sense amplifier) and data input structure (data-instructure) are to be coupled to row decoder 1203 by data/address bus (data bus) 1207.Data from the output/inbound port (input/output port) of integrated circuit 1250, or other is the data input structures that transfer in the square 1206 by Data In-Line (data-in line) 1211 at integrated circuit 1250 inner or outside Data Sources.The data of induction amplifier from square 1206 are to transfer to the output/inbound port of integrated circuit 1250 by DOL Data Output Line (data-out line) 1212, or transfer to integrated circuit 1250 inner or outside data destinations.Bias voltage arrangement stater 1209 may command bias voltages are settled voltage 1208 are provided, and for example erase verifying voltage and program verification voltage, first and second bias voltages settle the start voltage and the arrangement of the 3rd bias voltage that are used for the limit journey and reduce memory cell to be used to change the CHARGE DISTRIBUTION that memory cell electric charge benefit is caught structure.
The 13rd figure and the 14th figure illustrate application of the present invention, erase cycle or other technology to set up the low flow chart that opens the memory cell of beginning state in conjunction with one.In the 13rd figure, at first, in the square 1300, erase period is carried out initialization by the order of erasing (erase command).Convenient for teaching herein, in erase period, pointer n is made as 0.In certain embodiments, the order of erasing is corresponding to " quickflashing " regional erase operation for use (flash sector eraseoperation) in flash memory component (flash memory).Respond the order of erasing, bias voltage technology can be set up.In one embodiment, first operation provides bias voltage arrangement in the bias voltage technology, and it causes that in memory cell region hot hole injects (square 1301).For example, character online Jia Yue-3 is to the bias voltage of-7V in the zone, with the online bias voltage that adds approximately+3 to+7V in the position of the drain coupled of memory cell, be ground connection at the online bias voltage that adds of source electrode, and also ground connection of the channel region of substrate with the source-coupled of memory cell.In the zone of erasing, the side that above-mentioned bias voltage arrangement meeting closes on drain electrode end in the charge-trapping structure causes that hot hole injects.After providing hot hole to inject bias voltage to settle, stater (state machine) or other logical circuit be by carrying out the verification operation of erasing, with the whether success of decision erase operation for use.So, in next step (square 1302), can determine whether memory cell is by the verification operation of erasing.If memory cell is not by the verification operation of erasing, index n can increase (square 1303), and whether decision index n is increased to predetermined maximum number of attempts order N (square 1304).If reached maximum number of attempts order N, and memory cell is not yet by erasing verification operation, so just this technology is failed (square 1305).If go back no show maximum number of attempts order N (square 1304), then technology is got back to square 1302, inject the bias voltage arrangement to attempt hot hole once more.If by the verification operation of erasing, then provide the charge balance biased operation in square 1302 memory cell, shown in 1B figure, it can produce simultaneously, and hot electron injects and ejaculation electric current (square 1306).Above-mentioned charge balance biased operation comprises the negative-gate voltage pulse, its pulse length that has between 10 to 100 milliseconds, preferably about 50 milliseconds.This pulse is desired balancing charge and is distributed and neutralization seizure hole, and it is enough to improve the persistence and stability of memory cell.After the charge balance biased operation, the verification operation of erasing can repeat (square 1307) again.If memory cell is not by checking, flow process can increase the number of index n, and whether decide to reattempting or failing according to reaching maximum number of attempts order N via the loop to square 1303.In square 1307, if memory cell is by checking, then technology constipation bundle (square 1308).
In the 14th figure, erase period is carried out initialization (square 1400) by the order of erasing.Convenient for teaching herein, in erase period, pointer n is made as 0.In certain embodiments, the order of erasing is corresponding to " quickflashing " regional erase operation for use in flash memory component.Respond the order of erasing, bias voltage technology can be set up.In this example, after the order of erasing, provide the charge balance bias voltage to settle, it can cause that hot electron injects and electronics penetrates electric current (square 1401).Above-mentioned charge balance biased operation comprises a negative-gate voltage pulse, its pulse length that has between 10 to 100 milliseconds, preferably about 50 milliseconds.When balancing charge distributed, above-mentioned charge balance bias voltage can make that the quantity of store charge converges to the target start voltage in the memory cell.In other embodiments, above-mentioned charge balance biased operation comprises a negative-gate voltage pulse, and its pulse length that has is between 500 to 1000 milliseconds, to reach the poised state of catching electric charge in each erase period.The length of each negative-gate voltage pulse is the time budget (timing budget) that allows of the embodiment, erase period according to each memory cell, provide hot hole to inject length and other parameter that bias voltage settles selects.Next step operation provides a bias voltage and settles, and injects (square 1402) to cause hot hole.For instance, in the zone character online Jia Yue-3 to the bias voltage of-7V, with the online bias voltage that adds approximately+3 to+7V in the position of drain coupled, and with the online bias voltage that adds of the source electrode of source-coupled be ground connection, and also ground connection of the channel region of substrate.In the zone of erasing, the side that above-mentioned bias voltage arrangement meeting closes on drain electrode end in the charge-trapping structure causes that hot hole injects.Settle because the hot hole of aforementioned square 1401 injects bias voltage, the present invention can reach more uniform result.After providing hot hole to inject bias voltage to settle, stater or other logical circuit be by the execution verification operation of erasing, with the whether success of decision erase operation for use.So, in next step (square 1403), can determine whether memory cell is by the verification operation of erasing.If memory cell is not by the verification operation of erasing, index n can increase (square 1404), and whether decision index n is increased to predetermined maximum number of attempts order N (square 1405).If reached maximum number of attempts order N, and memory cell is not yet by erasing verification operation, so just this technology is failed (square 1406).If go back no show maximum number of attempts order N (square 1405), then technology is got back to square 1402, inject the bias voltage arrangement to attempt hot hole once more.If at square 1403, memory cell then provides the second charge balance biased operation by the verification operation of erasing, it can produce simultaneously, and hot electron injects and ejaculation electric current (square 1407).Above-mentioned charge balance biased operation comprises the negative-gate voltage pulse, its pulse length that has between 10 to 100 milliseconds, preferably about 50 milliseconds.This pulse is desired balancing charge and is distributed and neutralization seizure hole, and it is enough to improve the persistence and stability of memory cell.In certain embodiments, do not use the second charge balance biased operation.In square 1403 pulse length, be that only to carry out the pulse length of a charge balance biased operation than other embodiment also short with the charge balance biased operation of square 1407.After the charge balance biased operation of square 1407, the verification operation of erasing can repeat (square 1408) again.If memory cell is not by checking, flow process can increase the number of index n, and whether decide to reattempting or failing according to reaching maximum number of attempts order N via the loop to square 1404.In square 1408, if memory cell is by checking, then erase period constipation bundle (square 1409).
The 15th figure illustrates the start voltage schematic diagram of corresponding time, wherein the time, the time span that provides to the negative-grid charge balance bias pulse of low start voltage memory cell was provided, the flash memory cell before programming and erase period shown in 1A figure and 1B figure.Video data group 1510 (hollow triangle), 1520 (black triangles), 1530 (hollow dots) and 1,540 four groups of stitchings such as (solid dot) among the 15th figure, it represents the ratio of start voltage convergence under different grid voltages respectively.In this embodiment, the L/W of memory cell size dimension is 0.5 μ m/0.38 μ m, and ONO (oxide layer-nitride layer-oxide layer) stack layer size dimension is 55 dusts (angstrom)/60 dust/90 dusts, and the p+ polysilicon gate.Before programming and erase period, negative-grid charge balance bias pulse comprises and adds negative voltage on the grid, and source electrode, substrate and drain electrode are ground connection.The grid negative voltage of data set 1510 correspondences is-21V; The grid negative voltage of data set 1520 correspondences is-20V; The grid negative voltage of data set 1530 correspondences is-19V; The grid negative voltage of data set 1540 correspondences is-18V.All full the closing of data set 1510,1520,1530 and 1540 start voltage converges to common voltage 1505, about its about 3.8V.The grid negative voltage is high more, all saturated fast more of start voltage.Grid negative voltage with above-mentioned-21V is an example, only about 0.1 to 1.0 second of pulse length, and promptly convergence is complete haply for start voltage.Other embodiment system provides higher grid negative voltage, and the start voltage of corresponding short period reaches the full convergence voltage that closes, or lower grid negative voltage is provided, and the start voltage of corresponding long period reaches the full convergence voltage that closes.Under identical pulse length, the ONO stack layer of thicker dimension or thicker bottom oxide can need the long time, just can make start voltage reach the convergence voltage that is full of, or need higher grid negative voltage, just can make start voltage reach the full convergence voltage that closes.Similarly, under identical pulse length, the ONO stack layer of thin dimension or thin bottom oxide, the short time can be needed, just can make start voltage reach the full convergence voltage that closes, or need lower grid negative voltage, just can make start voltage reach the full convergence voltage that closes.
The 16th figure and the 17th figure illustrate the start voltage schematic diagram of corresponding time, and the convergence situation that shows storage unit starting voltage, and CHARGE DISTRIBUTION changes the schematic diagram of bias voltage in the corresponding charge-trapping structure.The L/W of memory cell size dimension is 0.5 μ m/0.38 μ m herein.
Please refer to the 16th figure, the storage unit starting voltage of still not programmed and erase period, when beginning, just assist (Fowler-Nordheim) tunnelling by the postivie grid electric field, increase the varying number electronics to electric charge capture layer, to produce five groups of stitchings 1610,1620,1630,1640 and 1650 in various degree.After increasing these electronics, the memory cell of stitching 1610, it has the start voltage of about 5.3V, the memory cell of stitching 1620 has about 3.0V start voltage, the memory cell of stitching 1630 has about 2.4V start voltage, the memory cell of stitching 1640 has about 2.0V start voltage, and the memory cell of stitching 1650 has about 1.5V start voltage.Show among the figure that working as memory cell provides-21V grid negative voltage and source electrode, substrate and grounded drain, the variation of corresponding time of start voltage. Corresponding stitching 1610,1620,1630,1640 and 1650 memory cell after operating through the charge balance of 1 second negative gate bias, all converge to the about 3.9V of a common voltage.
Please refer to the 17th figure, four groups of stitchings 1710,1720,1730 and 1740 storage unit starting voltage are by hot carrier charging, comprise that channel hot electron is injected with hot hole to inject, and set up.So the start voltage of stitching 1710 memory cell is brought up to about 4.9V, the start voltage of stitching 1720 memory cell is brought up to about 4.4V, and the start voltage of stitching 1730 memory cell is about 3.3V, the about 3.1V of start voltage system of stitching 1740 memory cell.Show among the figure that working as memory cell provides-21V grid negative voltage and source electrode, substrate and grounded drain, the variation of corresponding time of start voltage. Corresponding stitching 1710,1720,1730 and 1740 memory cell after operating through the charge balance of 1 second negative-grid FN bias voltage, all converge to the about 3.7V of a common voltage.
The 16th figure and the 17th figure show, though the charge movement that different types arranged with the start voltage that changes memory cell to different values, providing is enough to produce electron injection current and electronics penetrates the bias voltage of electric current and the bias voltage that balancing charge distributes, and can make the start voltage of memory cell get back to their convergence voltage.Yet, reduce seizure hole and electronics and can make memory cell be difficult for being erased with unstable.Other embodiment system provides higher grid voltage, is bonded to the convergence required time of voltage so that the minimizing start voltage is full, or lower grid voltage is provided, and restrains the required time of voltage to increase full being bonded to of start voltage.
The 18th figure illustrates the start voltage schematic diagram of corresponding time, and shows to have the memory cell of different passage lengths, the convergence situation of its start voltage.Corresponding stitching 1810 and 1820 memory cell have passage length 0.38 μ m, and corresponding stitching 1830 and 1840 memory cell have passage length 0.50 μ m.Stitching 1820 and 1840 memory cell, be by increase channel hot electron to the charge-trapping structure with the rising start voltage.The start voltage of stitching 1820 memory cell is to be increased to about 5.2V, and the start voltage system of stitching 1840 memory cell is increased to about 5.6V.Corresponding stitching 1810 and 1830 memory cell are then as yet through programming and erase period.Show among the figure when the variation of corresponding time of the start voltage of stitching 1810,1820,1830 and 1840 memory cell is provided-21V grid negative voltage and source electrode, substrate and grounded drain.Corresponding stitching 1830 and 1840 memory cell, the full about 3.8V of a common convergence voltage that is bonded to, corresponding stitching 1810 and 1820 memory cell fullly are bonded to one and restrain the about 3.5V of voltage jointly.The 18th figure shows to have the memory cell of same channels length, can correspondence change the bias voltage of CHARGE DISTRIBUTION, and reach a common convergence voltage.The 18th figure also shows to have the memory cell of different passage lengths, can correspondence change the bias voltage of CHARGE DISTRIBUTION, and reach different convergence voltage.Yet the difference of passage length is not the main cause of influence convergence voltage, so in array, can ignore the influence of the difference of memory cell channel length to the target start voltage.
Above-mentioned passage omits effect (channel roll-off effect), for example, is shown in the zone of label 1850, is corresponding to the memory cell of tool than jitty, and above-mentioned have lower start voltage and lower convergence voltage than jitty.Therefore, the passage length of memory cell then can reduce start voltage and convergence voltage if select less size.In the same manner, the passage length of memory cell is if select bigger size, and start voltage and convergence voltage then can raise.Other embodiment provides higher grid voltage, and start voltage is full to be bonded to the convergence required time of voltage to reduce, or lower grid voltage is provided, and satisfying with the increase start voltage is bonded to the convergence required time of voltage.In addition, the target start voltage can change by the grid material of selecting the tool different work functions, and the material of higher work-functions of wherein having can reduce convergence voltage.Again, convergence voltage can change by the material of selecting to be easy to top oxide layer and one of them generation tunnelling of bottom oxide, and the material that wherein is easy to top oxide layer generation tunnelling can reduce convergence voltage, otherwise then denys.
The 19th figure and the 20th figure show that the bias voltage that balancing charge distributes in memory cell is kept the efficient that can reach start voltage.
The 19th figure shows having regular multiple position (multi-bit) memory cell that changes of CHARGE DISTRIBUTION, the schematic diagram of corresponding programming of start voltage and erase period number of times.Programme for first, represent first to be read, represent second to be read at stitching 1920 (hollow dots) at stitching 1910 (solid dot).Programme for second, represent first to be read, represent second to be read at stitching 1940 (hollow triangle) at stitching 1930 (black triangle).Represent first to be erased and read at stitching 1950 (closed square), represent second to be erased and read at stitching 1960 (hollow square).Programme when one, grid voltage 11.5V keeps 1 microsecond (microsecond), and one of drain/source is 5V, and another is 0V for a drain/source, and substrate is-2.5V.When just programming, in passage initialization secondary electron (CHISEL) athletic meeting generation and the iunjected charge capturing structure.Erase when one, grid voltage-1.8V keeps 1 millisecond, and one of drain/source is 6V, and another is 0V for a drain/source, and substrate is 0V.When just erasing, in hot hole athletic meeting generation and the iunjected charge capturing structure.When erase period, the negative gate bias that is used for balancing charge can offer memory cell, for example provide keep 50 milliseconds of pulses-21V grid voltage and source electrode, substrate and grounded drain.What can see is, the distribution that start voltage can maintain is about 100,000P/E cycle.
The 20th figure is similar to the 19th figure, is the schematic diagram that shows the variation of the programming/erase period number difference start voltages that cause for multiple position memory cell.Yet, being different from the 19th figure, the negative-grid FN bias voltage that causes CHARGE DISTRIBUTION to change is not applied to memory cell in erase operation for use.As a result, repeatedly after the programming/erase period, can improve start voltage in the seizure interference that layer charge caused.Programme when first, first is read at stitching 2010 (solid dot), and second is read at stitching 2020 (hollow dots) then.In second when programming, first is read at stitching 2030 (solid triangle), and second be read at stitching 2040 (hollow triangle).Be read and erase first of stitching 2050 (closed square).Be read and erase second of stitching 2060 (hollow square).When being less than ten programming/erase period numbers, the start voltage of programming and erasing all significantly improves.After 500 number of cycles, if there is not charge balance operation described herein, the start voltage of erasing of memory cell can improve above 1V.
The 19th figure and the 20th figure be common show bestow a bias voltage after, the tendency balance that distributes of electricity 0 lotus in the memory cell, can eliminate or reduce because of repeatedly erase/programming cycle causes the puzzlement of start voltage success rate.Another embodiment is a grid voltage of bestowing higher plate number, reducing the start voltage required time of convergence state that reaches capacity, or bestows a grid voltage than harmonic series, to increase the reach capacity required time of convergence state of start voltage.Other embodiment increases or reduces negative-gate voltage for utilizing, to change the degree that start voltage reaches convergence.
The 21st figure is that start voltage changes corresponding schematic diagram of holding time, and contrast is by bestowing and not bestowing the memory cell that the negative-grid pulse comes balancing charge to distribute.The memory cell of stitching 2110,2120,2130,2140 is all born programming/erase period of 10,000 times.Yet, when the memory cell of stitching 2110,2120 in erase operation for use, jointly at a negative-grid pulse in the stitching 2125 to change the CHARGE DISTRIBUTION in the memory cell.For the memory cell of stitching 2110,2120, at a negative-grid pulse in the stitching 2145, can not bestow memory cell jointly.Preservation is not good because bigger start voltage changes representative data, and the data that the operation of graphical display balanced voltage improves in the memory cell are preserved.Preserve in the test in data, one negative-gate voltage-7V bestows the grid of the memory cell of stitching 2110,2130, and another negative-gate voltage-9V bestows the grid of the memory cell of stitching 2120,2140.Because increase voltage, in stitching 2125, the data preservation state that the memory cell of stitching 2120 experience is more even worse than the memory cell of stitching 2110.Simultaneously, in stitching 2145, the data preservation state that the memory cell of stitching 2140 experience is more even worse than the memory cell of stitching 2130.
The 22nd figure illustrates to utilize to mix the charge capturing storage unit that bias voltage is erased, and can come balance to catch the CHARGE DISTRIBUTION of layer, to reduce the schematic diagram of storage unit starting voltage by hot hole jet and the auxiliary compound mode that penetrates and inject electron stream of electric field.Contain the substrate 2250 and 2260 in Doped n+zone, and the substrate in doping p-zone between the substrate 2250 and 2260 in Doped n+zone.The remaining part of memory cell comprises the oxidation structure 2220 of suprabasil oxidation structure 2240, the charge-trapping structure 2230 on oxidation structure 2240, another charge-trapping structure 2230, with the grid 2210 on oxidation structure 2220.The electromotive force of-21V places grid 2210, and the electromotive force of another 3V places source electrode 2250 and drain electrode 2260, substrate 2270 ground connection.When this mixes bias arrangement, multiple charge takes place move.Observe the one charge movement, hot hole shifts out from source electrode 2250 and drain electrode 2260, enters electric charge capture layer 2230, therefore reduces the start voltage of memory cell.Observe another charge movement, electronics 2233 moves to charge-trapping structure 2230 from grid 2210.Observe another charge movement again, electronics 2273 from charge-trapping structure 2230 to source electrode 2250, substrate 2270 and drain electrode 2260.2230 the moving electron 2233 from grid 2210 to capturing structure, with from capturing structure 2230 to source electrode 2250, the moving electron 2273 of substrate 2270 and drain electrode 2260, all be the example that shifts out electronics from grid.The electromotive force of using can be adjusted according to the application of specific embodiments, needs to consider the size of memory cell and wherein structure, employed material, with target start voltage value etc.As aforementioned, the electronics from the electric charge capture layer to the substrate penetrates electric current, increases significantly during through passage, tends to the CHARGE DISTRIBUTION in the balancing charge capturing structure.From the substrate near source electrode and drain electrode, the hot hole stream of injection tends to increase the rate of change of unit start voltage, when comparing with the auxiliary tunnelling of electric field, can be erased the time faster.
The 23rd figure is a mixing bias voltage at different memory cell, draws the variation diagram of time and start voltage.One negative-grid charge balance bias voltage cooperates the ground potential of source electrode and drain electrode, is applied to the memory cell of stitching 2310.Can reduce the bias voltage that mixes of the start voltage of memory cell and CHARGE DISTRIBUTION that the tendency balancing charge is caught layer simultaneously, be applied to stitching 2320,2330,2340, with 2350 memory cell.For stitching 2310,2320,2330,2340,, bestow grid one negative voltage-21V and substrate ground connection with 2350 memory cell.The memory cell of stitching 2310,0V bestows source electrode and drain electrode.The memory cell of stitching 2320,2.5V bestows source electrode and drain electrode.The memory cell of stitching 2330,3V bestows source electrode and drain electrode.The memory cell of stitching 2340,4V bestows source electrode and drain electrode.The memory cell of stitching 2350,5V bestows source electrode and drain electrode.Source electrode is bestowed in Figure 23 demonstration and bigger voltage is bestowed in drain electrode, and faster reduction start voltage is moved from source electrode and drain electrode in more hole to the charge-trapping structure.Thereby, do the time spent in erase pulses, this mixes bias voltage and causes the combination that hot hole injection current, electron injection current and electronics penetrate electric current.When shorter erase pulses, can act on faster and erase the time.To lack the hot hole injection current is example, and one 0.5 to 1.0 seconds pulse could be set up the convergence start voltage of memory cell among Figure 23.When lacking the hot hole injection current, this jet is caused by bestowing the symmetrical 3V voltage of drain electrode with source electrode, and the example among Figure 23 is restrained in 1 to 50 microsecond.Another embodiment bestows the grid voltage of higher plate number, can reduce start voltage and arrive the convergence required time.Another embodiment is for increasing or reduce negative-gate voltage action time, to adjust the grade that start voltage reaches convergence.Another embodiment changes source electrode and drain voltage, to change the start voltage required time that reduces memory cell.
The 24th figure and the 25th figure show a representative charge storing unit capture operation.Wherein reduce the front and back of storage unit starting voltage, utilize to change, be inclined to the CHARGE DISTRIBUTION that balance is adjusted electric charge capture layer.
The exemplary process of the new memory cell 2410 of programming/erase period had not been experienced in the 24th figure explanation.Stitching 2420 and the programming of 2430 memory cell experience with erase.Among some embodiment, before the operation of programming/erasing for the first time, carry out the charge balance operation that makes electric charge capture layer.In stitching 2440, after the programming/erase period, carry out the charge balance operation of electric charge capture layer.Next, repeat the operation of another section programming/erase.Therefore in the representativeness operation of Figure 24, after programming/erase period, carry out the charge balance operation of electric charge capture layer.In certain embodiments, after programming/erase period each time, all carry out the charge balance operation of electric charge capture layer.
The 25th figure is similar in appearance to the 24th figure.Exemplary process among the 25th figure, the new unit that never experiences the operation of any programming/erase begins.Yet after having replaced memory cell 2520 and erasing, in the programming of memory cell 2520 and erasing between the action of memory cell 2530, balance takes place with the action that changes CHARGE DISTRIBUTION in the electric charge capture layer 2525.In certain embodiments, before the programming/erase period, change is carried out with the charge balance that balancing charge is caught layer for the first time.
The 26th figure shows that mat one mixes the exemplary process that bias voltage carries out charge capturing storage unit, and above-mentioned mixing bias voltage can change the CHARGE DISTRIBUTION and the start voltage that reduces memory cell of electric charge capture layer simultaneously.The exemplary process of the 26th figure is not for passing through the new memory cell 2610 of any programming/erase period.In 2620, memory cell is programmed.In 2630, behind the programming operation, one mixes bias effect in memory cell.This mixes bias voltage and reduces storage unit starting voltage and the CHARGE DISTRIBUTION that changes electric charge capture layer simultaneously.At some embodiment, before the programming/erase period, the charge balance that changes electric charge capture layer has begun effect for the first time.
At some embodiment, Figure 24,25 operates with 26 representativeness and is combined by part.Among one embodiment, before and after the action of erasing of memory cell, charge storing unit distributes and all is changed.In various embodiments, all be applied to the mixing bias voltage before and after the action of erasing of memory cell.Among another embodiment,, change charge storing unit and distribute mixing bias voltage enforcement front and back.
One new charge trapping devices (for example nitrogenize read-only memory or silicon oxide nitride oxide silicon) erasing method is suggested.This device is injected by grid earlier and (Vg) is reset to erased status.Can reach programming operation via many methods, for example channel hot electron, the passage secondary hot electron injection current, the FN that are unlocked wear tunnel, pulse excitation substrate hot electron and other operation.Erasing can be strengthened hot hole (BTBTHH) and inject (being generally used for the nitrogenize read-only memory), wear then as the negative FN that is used for silicon oxide nitride oxide silicon (SONOS) by the tunnelling of district's interband, or the method for operation that removes of other section.In the operation that section removes, an additional channel erase operation for use (adopt negative-gate voltage, forward basic voltage, or both having concurrently), wherein the passage tendency of operation of erasing is caught charge balance in the structure in the balance electric fishing.This passage erase operation for use provides oneself's convergence erasing mechanism.For the memory cell of excessively erasing or being difficult to erase, provide the charge balance revisal.Through charge balance technique thus, the target starting voltage of erased status can be fixed up.Further, the heat of oxide layer or nitration case is caught all and can be neutralized by the electron institute that grid penetrates.Therefore, charge balancing method can reduce the memory cell infringement that causes because of hot hole.Therefore, by in conjunction with charge balance technique and hot hole erasing method, can obtain favorable durability and reliability character.
Charge balance technique and erase operation for use can be applicable to any time or any technology, to promote the effect of erasing in the section erase operation for use.Another kind is chosen as slight adjustment contact bias voltage, introduces the hot hole jet when erasing with passage, can obtain the double effects that passage is erased and erased with hot hole simultaneously.Passage is erased and combining that hot hole is erased, and can promote P/E window and reliability.
Charge balance technique described herein and erase operation for use can be used for the device of similar nitrogenize read-only memory, and central bottom oxide must be enough thick in to stop charge loss.Charge balance technique demonstrates for different passage lengths with the characteristic of erasing conforming trend, and these passages are because Vt removes effect different initial Vt values is arranged.Because being used for the negative-grid FN passage tunnelling of charge balance operation is one dimension tunnelling mechanism, and during by the tunnel symmetry, so have nothing to do with the lateral dimensions size of unit.Therefore, for using charge balance technique described herein and erasing method.The adjustment of critical dimension and reliability and stability improvement can reach at nitrogenize read-only memory pattern device.This technology is for being applicable to the combination of the high starting voltage method of setting up memory cell via the operation of programming or other, shown in the 27th figure.This operation comprises retry operation, wherein memory cell is at first bestowed bias voltage and is caused high starting voltage state, penetrate the charge balance pulse that produces via the electronics of shallow electric charge capture layer then and reduce starting voltage, utilize second pulse to cause electronics again and inject the negative electrical charge that the electronics capturing structure produces and come secondary to fill up.In Figure 27, start technological process via a program command (block 2700).With according to being directed to this point enlighteningly, index n is configured to zero and is used for the retry programming, and index m is configured to zero and is used for calculating and heavily fills up operation.Especially at flash memory, via the technological order of some related application of bit arithmetic.For the response technique instruction, a biased operation is set.In one embodiment, first of biased operation is operating as to be bestowed one and mixes bias voltage and cause electronics and inject, and finishes the programming purpose (section 2701) of memory cell.Illustrate, the secondary electron injection of channel start is caused by mixing bias voltage for the first time.This causes in the memory cell of electron jet in programming, therein a side of charge-trapping structure.After bestowing electronics injection mixing bias voltage, by program verification verify technology, a state device or other logic can determine whether programming operation is successful.Therefore, in the next step, utilize algorithm (rule) to decide memory cell whether by checking technology (section 2702).If by checking, pointer n can not add 1 (section 2703) in the unit, whether algorithm decision pointer arrives predefined maximum reattempt times N (section 2704) then.If reach maximum reattempt times and do not pass through checking, this technology is made as failure (section 2705).If reach the maximum reattempt times of section 2704, this technology can be got back to section 2701 retry electronics and be penetrated the mixing bias voltage.If when block 2702 memory cell are passed through checking, whether reach maximum M (section 2706) via index m, the specific retry cycle-index of algorithm decision is performed.If index m is not equal to M, charge balance pulse meeting is that retry is adjusted, and causes electron injection current, at first is beneficial to shallow electric charge capture layer electronics and penetrates, and aforementioned implementation content (section 2707) please refer to Figure 1B.The charge balance operating operation comprises and is less than a negative-gate voltage pulse of ten milliseconds, adopts one millisecond in the example.A pulse like this can cause that the electronics in shallow seizure energy layer injects admission passage.It is because of in the unit quite highdensity negative electrical charge being arranged in the retry circulation that considerably less electronics penetrates.After the charge balance biased operation, algorithm increases pointer m (section 2708) and returns to two, bestows again and mixes the electron injection current that bias voltage causes section 2701.If memory cell has experienced predetermined retry operation number of times, algorithm just be through with (section 2709).
The embodiment of this technology comprises the described charge balance pulse with reference to the 27th figure, and this pulse must be implemented before the programming/erase period of any device, or before the programming operation described in reference Figure 27.Simultaneously, the embodiment of this technology comprises the 4th, 5,11 figure and the 24-26 figure algorithm that comprises retry operation of describing, and describes as reference Figure 27 in programming operation.
The 28th figure and the 29th figure show the data of the retry operation of the 27th figure, and central technology is mixed bias voltage and caused the passage secondary electron CHISEL injection current of starting.Nitrogenize read-only memory pattern unit and P type polysilicon bar extremely in, via carrying out the data that charge balance pulse (grid voltage-21V cooperates drain electrode, source electrode and substrate to remain on 0V about second) is produced earlier, set up the starting voltage of about 3.8V.Next, many retry operations have just been implemented.Arbitrary retry operation that comprises application mix bias voltage initiation CHISEL injection current is being followed of short duration electric charge equalizing pulse (grid voltage-21V, drain electrode, source electrode and substrate are that 0V keeps about 1 millisecond), and the starting voltage that can set memory cell is to about 5.3V.
The 28th figure shows, at continuous retry (refill) in the operation cycle, at the schematic diagram of corresponding time of start voltage of five charge balance pulses.At the start voltage of stitching 2800, after 1 millisecond charge balance pulse, can fall to 4.9V from 5.3V.In the next retry circulation of stitching 2801, after the charge balance pulse through one millisecond of the second time, start voltage is reduced to 5.1V from 5.3V.The circulation of the retry for the third time of stitching 2802, for through after one millisecond the charge balance pulse for the third time, start voltage is reduced to 5.2V from 5.3V.The 4th retry circulation of stitching 2803, for through after the 4th one millisecond the charge balance pulse, start voltage is reduced to 5.22V from 5.3V.The 5th retry circulation of stitching 2804, for through after the 5th one millisecond the charge balance pulse, start voltage is reduced to 5.23V from 5.3V.
The 29th figure shows the data identical with the 28th figure, and it is continuous retry period that demonstration is fallen the start voltage of each circulation.Therefore, in first retry period, start voltage falls from about 5.3V to about 4.9V.Second retry period, start voltage drops to about 5.1V.Via the 5th retry period, because catch the blue displacement effect of spectrum on the energy rank of electronics, the charge balance pulse of circulation begins saturated, so the loss of charge that short charge balance pulse causes descends.
The 30th figure and the 31st figure are the data display operations that shows the 27th figure retry operation, and central program bias is settled by forward grid voltage injection current, cause passage FN tunnelling current.Nitrogenize read-only memory pattern unit and P type polysilicon bar extremely in, via carrying out charge balance pulse (grid voltage-21V cooperates drain electrode, source electrode and substrate to remain on 0V about second) earlier, set up the starting voltage of an about 3.8V.Next, the retry operation of a number is performed.Each retry operation comprises implements bias voltage arrangement, be used to cause passage FN tunnelling current and set the memory cell starting voltage to about 5.3V, continue and implement a short charge balance pulse (grid voltage-21V cooperates drain electrode, source electrode and substrate to remain on about four milliseconds of 0V).
The 30th diagram system shows in the continuous retry operation, at the start voltage and the time relation schematic diagram of five charge balance pulses.After the charge balance pulse of the start voltage of stitching 2800 through four milliseconds of the first time, drop to 5.05V from 5.3V.The circulation of retry next time at stitching 2801 after the charge balance pulse through four milliseconds of the second time, drops to 5.16V from 5.3V.In the circulation of the retry for the third time of stitching 2802, after four milliseconds charge balance pulse for the third time, drop to 5.22V from 5.3V.In the 4th retry circulation of stitching 2803, after the 4th one millisecond charge balance pulse, drop to 5.22V from 5.3V.In the 5th retry circulation of stitching 2804, after the 5th one millisecond charge balance pulse, drop to 5.25V from 5.3V.
The 31st diagram system shows the data identical with Figure 30, and it is continuous that demonstration is fallen the start voltage of each circulation.Therefore, at first retry operation, start voltage falls from about 5.3V to about 5.05V.At second retry operation, start voltage drops to about 5.16V.Via the 5th retry circulation, because catch the blue displacement effect of spectrum on the energy rank of electronics, the charge balance pulse of circulation begins saturated, so the loss of charge that short charge balance pulse causes descends.
The 32nd figure system shows retry and preserves with the data of the memory cell of no retry processing.Data represented device is through 10,000 programming/erase period, cause infringement that hot hole causes after, the usefulness of device performance.Stitching 3200 is a device without retry, through one millisecond 150.The C stoving time, the start voltage loss surpasses 0.5V.Stitching 3201 is a device without retry, and through same stoving time, the start voltage loss is lower than 0.3V.
The 33rd figure is energy rank (energy level) schematic diagram that shows charge capturing storage unit of the present invention.In this energy rank schematic diagram, first zone 3300 is with respect to suprabasil passage.Second zone 3301 is with respect to end dielectric layer, and main component is a silicon dioxide.The 3rd zone 3302 is mainly the silicon nitride composition with respect to electric charge capture layer.The 4th zone 3303 is with respect to the top dielectric layer, and main component is a silicon dioxide.The 5th zone 3304 relative grids, main component is a high functional material among P type polysilicon or other relevant the present invention.As previously described, the relevant high functional material that is used for grid is higher than the N type polysilicon bar utmost point that cooperates silicon dioxide top dielectric layer in order to make the injection obstacle 3306 of electronics 3305.Function 3307 as shown in figure 33, correspondence move on to the energy value of free electron from the electronics of the conductive strips of grid material.Figure 33 also is presented at electric charge capture layer individually, the shallow and dark electronics 3308 and 3309 of catching.Represented with reference to Figure 27, before the electronics 3309 of dark electric charge capture layer penetrated, the electronics 3308 that a short charge balance pulse tendency causes shallow electric charge capture layer penetrated.3309 pairs of electric charges of electronics at dark electric charge capture layer leak the electric charge preservation characteristics that repellence is preferable and proof is more excellent.For the embodiment that uses retry operation, the thickness of bottom oxide preferably is higher than 3 nanometers for direct Tunneling.Also available other tool high dielectric constant materials of the material of the end and top dielectric layer, for example Al2O3 and HfO2.Similarly, the electric charge benefit is caught layer and also can be used other material.
The negative electrical charge balancing run has the characteristic of start voltage oneself convergence, for the programming/erase period of an array with the big figure that links up, can keep stable start voltage and distribute.Further, because reduce the hot hole infringement of end dielectric layer, can obtain good degree of belief.
By technology and the disclosed the present invention of example of describing in detail before, be in order to illustrate but not the purpose that is confined to is wherein explained.For any those skilled in the art, without departing from the spirit and scope of the present invention, combine when doing various changes, revise and retouching, so protection scope of the present invention is as the criterion when looking the accompanying Claim scope person of defining.
The application's case is advocated the priority about the U.S. Provisional Application case of application on April 26th, 2004 number 60/565,377.The application's case is also advocated the priority about the U.S. Provisional Application case of on April 30th, 2004 application number 60/566,669.
Claims (26)
1. the method for an operation store unit, be included in grid, source electrode and drain electrode in the substrate, and the passage between this source electrode and this drain electrode, also being included in this grid and this interchannel top dielectric layer, charge-trapping structure and end dielectric layer, this operation store element method comprises:
First technology is provided, be used for setting up low start voltage state in this memory cell, comprise the arrangement of first bias voltage, be used for reducing the negative electrical charge of this charge-trapping structure, and comprise that second bias voltage settles, be used between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, causing the balancing charge tunnelling; And
Second technology is provided, is used for setting up high start voltage state, comprise the arrangement of the 3rd bias voltage, be used for increasing the negative electrical charge of this charge-trapping structure in this memory cell.
2. method according to claim 1, wherein this first bias voltage is settled and is comprised that district's interband tunnelling causes that hot hole injects.
3. method according to claim 1, wherein this first bias voltage is settled and is comprised that first pulse causes that with trigger area interband tunnelling hot hole injects, and this second bias voltage is settled and is comprised and second pulse cause the electric charge tunnelling between this grid and this charge-trapping structure and in this charge-trapping structure and this interchannel.
4. method according to claim 1, wherein this top dielectric layer, this charge-trapping structure and this end dielectric layer have a combination effective oxide thickness, this bottom oxide has an effective oxide thickness greater than 3nm, and this second bias voltage is settled and is comprised and provide a negative electricity to be pressed on this grid to this interchannel that it is 0.7V/nm or bigger value divided by this combination effective oxide thickness value that this negative voltage has a voltage.
5. method according to claim 1, wherein this top dielectric layer, this charge-trapping structure and this end dielectric layer have a combination effective oxide thickness, this bottom oxide has an effective oxide thickness greater than 3nm, and this second bias voltage is settled and is comprised and provide a negative electricity to be pressed on this grid this interchannel relatively, it is 0.7V/nm or bigger value divided by this combination effective oxide thickness value that this negative voltage has a voltage, and provide a ground potential in this substrate channel region, and provide a ground potential in this source electrode and this drain electrode.
6. method according to claim 1, wherein this top dielectric layer, this charge-trapping structure and this end dielectric layer have a combination effective oxide thickness, it is 3nm or littler value that this bottom oxide has an effective oxide thickness, and this second bias voltage is settled and is comprised and provide a negative electricity to be pressed on this grid to this interchannel that it is 0.3V/nm or bigger value divided by this combination effective oxide thickness value that this negative voltage has a voltage.
7. method according to claim 1, wherein this top dielectric layer, this charge-trapping structure and this end dielectric layer have a combination effective oxide thickness, it is 3nm or littler value that this bottom oxide has an effective oxide thickness, and this second bias voltage is settled and is comprised and provide a negative electricity to be pressed on this grid to this interchannel, it is 0.3V/nm or bigger value divided by this combination effective oxide thickness value that this negative voltage has a voltage, and provide a ground potential in this substrate channel region, and provide a ground potential in this source electrode and this drain electrode.
8. method according to claim 1, wherein this top dielectric layer, this charge-trapping structure and this end dielectric layer have a combination effective oxide thickness, and this second bias voltage is settled and is comprised and provide a negative electricity to be pressed on this grid to this interchannel that it is that 1.0V/nm adds and subtracts 10% divided by this combination effective oxide thickness value that this negative voltage has a voltage.
9. method according to claim 1, wherein this grid material comprises that a work function is greater than 4.25 electron-volts material.
10. method according to claim 1, wherein this grid material comprises the polycrystalline silicon material of doped p type impurity.
11. method according to claim 1, wherein this second bias voltage arrangement comprises provides first pulse, be used between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, cause the balancing charge tunnelling, and this first bias voltage arrangement provides second pulse after being included in this first pulse.
12. method according to claim 1, wherein this second bias voltage arrangement comprises provides first pulse, be used between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, cause the balancing charge tunnelling, and this first bias voltage arrangement provides second pulse after being included in this first pulse, and this second pulse is to settle according to second bias voltage to comprise that hot hole is injected into this charge-trapping structure.
13. method according to claim 1, wherein this first bias voltage is settled and is comprised that hot hole is injected into this charge-trapping structure, it is between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel that this second bias voltage is settled, cause the balancing charge tunnelling, and wherein this first and second bias voltages arrangement provides single pulse, this single pulse is included in this grid with respect to the negative voltage between this substrate, and this source electrode and should the drain electrode with respect to the positive voltage between this substrate.
14. method according to claim 1, wherein this top dielectric layer, this charge-trapping structure and this end dielectric layer have a combination effective oxide thickness, and this bottom oxide has an effective oxide thickness and works energetically 3nm, and also comprises:
Before any this first technology and this second process cycle, provide a negative electricity to be pressed on this grid this interchannel relatively, it is 0.7V/nm or bigger value divided by this combination effective oxide thickness value that this negative voltage has a voltage.
15. method according to claim 1, wherein this top dielectric layer, this charge-trapping structure and this end dielectric layer have a combination effective oxide thickness, and it is 3nm or littler that this bottom oxide has an effective oxide thickness, and also comprises:
Before any this first technology and this second process cycle, provide a negative electricity to be pressed on this grid this interchannel relatively, it is 0.3V/nm or bigger value divided by this combination effective oxide thickness value that this negative voltage has a voltage.
16. method according to claim 1, wherein this second bias voltage arrangement comprises provides a pulse, with between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, cause the balancing charge tunnelling, this pulse persistance one time-histories is 100 milliseconds.
17. method according to claim 1, wherein this second bias voltage arrangement comprises provides a pulse, with between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, cause the balancing charge tunnelling, this pulse persistance one time-histories is 50 milliseconds.
18. method according to claim 1, wherein this second bias voltage arrangement comprises provides a pulse, with between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, cause the balancing charge tunnelling, this pulse persistance one time-histories is 10 milliseconds.
19. method according to claim 1, wherein this first bias voltage settles the generation hot hole to flow into the first area, this first area is near a side of this passage, and this second technology generation electronics flows into second area, this second area and this first area overlap, and the 3rd bias voltage settle to produce electric field and assist tunnelling, the 3rd this passage of regional extend through and overlap with this first area and this second area in the 3rd zone.
20. method according to claim 1, wherein this first technology comprises according to this first bias voltage arrangement provides first pulse, and carries out verification operation, if this verification operation success, just provide second pulse according to this second bias voltage arrangement.
21. method according to claim 1, wherein this first technology comprises according to this second bias voltage arrangement provides first pulse, after this first pulse, settle so that second pulse to be provided then according to this first bias voltage, and execution verification operation, if just this verification operation failure is this second pulse of retry.
22. method according to claim 1, wherein this first technology comprises according to this first bias voltage arrangement provides first pulse, and carries out verification operation, if this verification operation success, just settle according to this second bias voltage second pulse is provided, and then carry out verification operation.
23. the method for an operation store unit, be included in grid, source electrode and drain electrode in the substrate, and the passage between this source electrode and this drain electrode, also being included in this grid and this interchannel top dielectric layer, charge-trapping structure and end dielectric layer, this operation store element method comprises:
First technology is provided, be used for setting up low start voltage state in this memory cell, comprise the arrangement of first bias voltage, be used for reducing the negative electrical charge of this charge-trapping structure, and comprise that second bias voltage settles, be used between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, causing the balancing charge tunnelling;
Second technology is provided, is used for setting up high start voltage state, comprise the arrangement of the 3rd bias voltage, be used for increasing the negative electrical charge of this charge-trapping structure in this memory cell; And
In a period of time, this first technology or this second technology take place, and provide the charge balance bias voltage to settle, to be equilibrated at the CHARGE DISTRIBUTION in this charge-trapping structure.
24. method according to claim 23, wherein this second bias voltage arrangement comprises provides a pulse, with between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, cause the balancing charge tunnelling, this pulse persistance one time-histories is less than 100 milliseconds; And this charge balance bias voltage is settled and is comprised a pulse is provided that with between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, cause the balancing charge tunnelling, this pulse persistance one time-histories is greater than 500 milliseconds.
25. method according to claim 23, wherein this second bias voltage arrangement comprises provides a pulse, with between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, cause the balancing charge tunnelling, this pulse persistance one time-histories is less than 50 milliseconds; And this charge balance bias voltage is settled and is comprised a pulse is provided that with between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, cause the balancing charge tunnelling, this pulse persistance one time-histories is greater than 500 milliseconds.
26. method according to claim 23, wherein this second bias voltage arrangement comprises provides a pulse, with between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, cause the balancing charge tunnelling, this pulse persistance one time-histories is less than 10 milliseconds; And this charge balance bias voltage is settled and is comprised a pulse is provided that with between this grid and this charge-trapping structure and at this charge-trapping structure and this interchannel, cause the balancing charge tunnelling, this pulse persistance one time-histories is greater than 500 milliseconds.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US56537704P | 2004-04-26 | 2004-04-26 | |
| US60/565,377 | 2004-04-26 | ||
| US60/566,669 | 2004-04-30 | ||
| US10/876,377 | 2004-06-24 |
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| Publication Number | Publication Date |
|---|---|
| CN1700448A CN1700448A (en) | 2005-11-23 |
| CN100390966C true CN100390966C (en) | 2008-05-28 |
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| CNB2005100696451A Active CN100390966C (en) | 2004-04-26 | 2005-04-26 | Operation scheme for spectrum shift in charge trapping non-volatile memory |
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| CN102298971B (en) * | 2011-08-29 | 2014-05-21 | 南京大学 | Operation method for high-density multilevel storage of non-volatile flash memory |
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| US9767914B1 (en) * | 2016-10-10 | 2017-09-19 | Wingyu Leung | Durable maintenance of memory cell electric current sense window following program-erase operations to a non-volatile memory |
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