JPH1131394A - Control method for nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the reliability of a nonvolatile semiconductor memory from being lowered by providing a step injecting electrons in a tunnel insulating film in an erase operation and injecting electrons in a floating gate thereafter to couple holes with electrons to vanish them and to prevent the accumulation of holes even when the holes exist in the tunnel insulating film. SOLUTION: In write operation, electrons being in a floating gate 6 are pulled out into a drain area 2 by a Fowell-Nordheim tunnel phenomenon. At this point, pairs between electrons and holes are generated by an interband tunnel phenomenon and one part of holes 11 is trapped in a tunnel insulating film 5. Here, before executing an erase operation next, a voltage Vcg to be applied on a control gate 8, a voltage Vd to be applied on the drain area 2 and the voltage of a source area 3 and a semiconductor substrate 1 are respectively controlled to 5-12 V, 3-18 V and 0 V. Then, channel hot electrons are made to be generated in the vicinity of the boundary area between the drain area 2 and a channel area 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for controlling a nonvolatile semiconductor memory device, and more particularly to a method for controlling a nonvolatile semiconductor memory device capable of electrically writing and erasing information.

[0002]

2. Description of the Related Art Conventionally, a flash memory has been known as a nonvolatile semiconductor memory device capable of electrically writing and erasing information. This flash memory is a stacked gate nonvolatile semiconductor memory device including a floating gate and a control gate. In this flash memory, data is recorded by utilizing the fact that the threshold voltage seen from the control gate differs between a state where electrons are stored in the floating gate and a state where electrons are not stored in the floating gate. Among these flash memories, one called a DINOR (Divided line NOR) type flash memory is IEICE TRANS. ELECTRON. VOL.E.
77-C NO.8 pp.1279-1285 AUGUST 1994. In the DINOR type flash memory, the state where electrons are accumulated in the floating gate is the erased state. Then, a state where electrons are extracted from the floating gate is a write (program) state. That is, an operation opposite to that of a generally known NOR type flash memory is performed.

FIG. 19 is a sectional structural view for explaining the structure of a conventional DINOR type flash memory. FIG.
9, a conventional DINOR type flash memory will be described below.

Referring to FIG. 19, a conventional DINOR type flash memory includes a source region 103, a drain region 102, a channel region 104, a tunnel insulating film
5, floating gate 106, insulating film 107
And a control gate 108.
On the main surface of the semiconductor substrate 101, a source region 103 and a drain region 102 are formed so as to sandwich the channel region 104. A tunnel insulating film 105 is formed on the channel region 104. On the tunnel insulating film 105, a floating gate 106 is formed. On the floating gate 106, an insulating film 107 is formed. The control gate 10 is formed on the insulating film 107.
8 are formed. Sidewall oxide films 109 are formed on the side surfaces of the tunnel insulating film 105, the floating gate 106, the insulating film 107, and the control gate 108.
a, 109b are formed.

Here, the voltage applied to the control gate 108 is V _cg , the voltage applied to the source region 103 is V _s , the voltage applied to the drain region 102 is V _d ,
The voltage applied to the semiconductor substrate 101 and V _b.

FIGS. 20 and 21 are sectional structural views for explaining a conventional erase and write operation of a DINOR type flash memory.

First, a conventional erase operation of a DINOR type flash memory will be described with reference to FIG. V _cg is 1
0V, -8V the V _s, -8V a V _b, the V _d Float
ing, Fowler-N
ordheim: hereinafter referred to as FN) A tunnel phenomenon occurs, and a channel region 104 is formed through the entire surface of the tunnel insulating film 105.
, Electrons 110 are injected into the floating gate 106. Thus, the electron 1 is stored in the floating gate 106.
10 are accumulated.

Referring to FIG. 21, a conventional write operation of a DINOR type flash memory will be described. V _cg -8V,
The V _d 6V, 0V to V _b, the the V _s and Floating, floating gate 106 and the drain region 10
2, an electron 110 in the floating gate 106 is extracted to the drain region 102. In this manner, the conventional writing and erasing operations of the DINOR type flash memory have been performed.

[0009]

Referring to FIG. 22, D
When performing the write operation of the INOR type flash memory,
The electric field strength between the floating gate 106 and the drain region 102 increases. As a result, a band-to-band tunnel phenomenon occurs.
One pair is generated. Then, part of the holes 111 is trapped in the tunnel insulating film 105.

Next, with reference to FIG.
Executed after the write operation shown in FIG.
The erasing operation to be performed will be described. To perform this erase operation
V _cg, V_s, V_d, V_bThe voltage conditions of FIG.
This is the same as the condition. At this time, the FN tunnel phenomenon
Injecting electrons into the floating gate 106
On the other hand, holes 111 are trapped in the tunnel insulating film 105.
Have been. As described above, the positive
Since the hole 111 is trapped, the floating gate
The electric field strength when injecting electrons into the
It is increased by the holes 111. As a result,
The amount of electrons 110 injected into the port 106 increases. So
Therefore, the threshold voltage after this erase operation is
Extra electrons 110 are injected into the
To get higher. And the book shown in FIGS.
By repeating the write and erase operations, the tunnel insulating film
Holes 111 accumulate in 105, forming a tunnel insulating film.
Quality degrades. This allows the floating gate
After an erase operation of injecting electrons 110 into
The pressure changes and the flash
There has been a problem that the reliability of the moly is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to prevent the quality of a tunnel insulating film from deteriorating and to reduce the reliability of a nonvolatile semiconductor memory device. It is an object of the present invention to provide a method for controlling a nonvolatile semiconductor memory device, which can prevent the occurrence of the problem.

[0012]

According to a first aspect of the present invention, there is provided a method of controlling a nonvolatile semiconductor memory device comprising a floating gate, a tunnel insulating film, first and second source / drain regions, and a control gate. A method of controlling electrons in a nonvolatile semiconductor memory device, the method including: a step of injecting electrons into the tunnel insulating film; and a step of injecting electrons into the floating gate after the step of injecting electrons into the tunnel insulating film. . As described above, since electrons are injected into the tunnel insulating film before injecting electrons into the floating gate, even if holes exist in the tunnel insulating film, the electrons injected into the tunnel insulating film and the holes Are coupled and disappear, so that holes are prevented from being accumulated in the tunnel insulating film. for that reason,
Deterioration of the film quality of the tunnel insulating film can be prevented, so that fluctuation of the threshold voltage of the nonvolatile semiconductor memory device can be prevented. As a result, a decrease in the reliability of the nonvolatile semiconductor memory device can be prevented.

According to a second aspect of the present invention, in the method of the first aspect, the electrons injected into the tunnel insulating film apply a positive voltage to the first source / drain region. Channel hot electrons generated by grounding the second source / drain region. Since channel hot electrons are used as electrons to be injected into the tunnel insulating film, more electrons can be injected into a region of the tunnel insulating film near the first source / drain region. Therefore, when there are many holes in a region near the first source / drain region in the tunnel insulating film, these holes and electrons can be effectively combined and eliminated.
This can prevent holes from accumulating in the tunnel insulating film. For this reason, it is possible to prevent the quality of the tunnel insulating film from deteriorating, thereby preventing the threshold voltage of the nonvolatile semiconductor memory device from fluctuating. As a result, a decrease in the reliability of the nonvolatile semiconductor memory device can be prevented.

According to a third aspect of the present invention, there is provided a method of controlling a nonvolatile semiconductor memory device according to the first aspect, wherein electrons injected into the tunnel insulating film are generated by applying a positive voltage to a control gate. Electrons. As described above, since substrate hot electrons are used as electrons to be injected into the tunnel insulating film, electrons can be injected into the entire surface of the tunnel insulating film. Therefore, when holes are present over almost the entire surface in the tunnel insulating film, these holes and electrons can be effectively combined and eliminated. For this reason, it is possible to more effectively prevent the deterioration of the film quality of the tunnel insulating film, thereby preventing the threshold voltage of the nonvolatile semiconductor memory device from fluctuating. As a result, a decrease in the reliability of the nonvolatile semiconductor memory device can be prevented.

According to a fourth aspect of the present invention, in the method of the second or third aspect, the step of injecting electrons into the floating gate comprises: applying a positive voltage to the control gate; The method includes a step of injecting electrons into the floating gate by an FN tunnel phenomenon caused by grounding the region. As described above, since the FN tunnel phenomenon is used for injecting electrons into the floating gate after injecting electrons into the tunnel insulating film, deterioration of the film quality of the tunnel insulating film is prevented, and at the same time, injection of electrons into the floating gate is performed. The required power can be reduced as compared with the case where hot electrons are used. Therefore, it is possible to prevent the threshold voltage of the nonvolatile semiconductor memory device from fluctuating. As a result, it is possible to prevent a decrease in the reliability of the nonvolatile semiconductor memory device and reduce power consumption.

According to a fifth aspect of the present invention, there is provided a method of controlling a nonvolatile semiconductor memory device according to the second aspect of the present invention, which utilizes an FN tunnel phenomenon generated by applying a positive voltage to the first source / drain region. The method further comprises the step of extracting the electrons accumulated in the floating gate to the first source / drain region. As described above, when electrons are extracted from the floating gate, electrons are extracted from the floating gate to the first source / drain region to which a positive voltage is applied. Accordingly, the first source / drain region of the tunnel insulating film is accordingly connected. Holes are formed in a region near to by the band-to-band tunnel phenomenon. Then, by applying a positive voltage for generating channel hot electrons again to the first source / drain region,
Channel hot electrons can be generated at a position near a region where holes are formed in the tunnel insulating film. Therefore, in the tunnel insulating film,
Holes and electrons can be effectively combined and annihilated.
Therefore, deterioration of the film quality of the tunnel insulating film can be more effectively prevented, and thus, fluctuation of the threshold voltage of the nonvolatile semiconductor memory device can be prevented. As a result,
It is possible to prevent a decrease in the reliability of the nonvolatile semiconductor memory device.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional structural view showing a DINOR type flash memory according to a first embodiment of the present invention. Referring to FIG. 1, a DINOR type flash memory according to a first embodiment of the present invention includes a source region 3, a drain region 2, a channel region 4, a tunnel insulating film 5, a floating gate 6, and an insulating film 7. When,
And a control gate 8. Source region 3 and drain region 2 are formed on the main surface of semiconductor substrate 1 so as to sandwich channel region 4. A tunnel insulating film 5 is formed on the channel region 4. On the tunnel insulating film 5, a floating gate 6 is formed. On the floating gate 6, an insulating film 7 is formed. A control gate 8 is formed on the insulating film 7. On the side surfaces of the tunnel insulating film 5, the floating gate 6, the insulating film 7, and the control gate 8,
Sidewall oxide films 9a and 9b are formed.

The voltage applied to the control gate 8 is V _cg , and the voltage applied to the source region 3 is V
_s, the voltage applied to the drain region 2 V _d, the voltage applied to the semiconductor substrate 1 and V _b.

FIGS. 2 to 5 and 7 are cross-sectional structural views for explaining an erasing / writing operation of the DINOR type flash memory according to the first embodiment of the present invention. Hereinafter, FIGS.
Referring to FIG. 7 and FIG.
The erasing / writing operation of the R-type flash memory will be described.

First, an erasing operation of the DINOR type flash memory will be described with reference to FIG. V _cg to 10V, V
_s The -8 V, -8 V and V _b, when the V _d and Floating, FN tunneling phenomenon occurs, the tunnel insulating film 5
Electrons 10 are injected from channel region 4 to floating gate 6 through the entire surface of. Thus, the electrons 10 are stored in the floating gate 6.

Next, the write operation of the DINOR type flash memory will be described with reference to FIG. V _cg -8V, V
The _d 6V, 0V to V _b, the the V _s and Floating, FN tunneling between the floating gate 6 and drain region 2 is generated, electrons 10 in the floating gate 6 is withdrawn into the drain region 2. At this time, as shown in FIG. 22, a high electric field generated between the floating gate 6 and the drain region 2 causes a band-to-band tunnel phenomenon. Thereby, the electrons 10 and the holes 11
And a part of the holes 11 are trapped in the tunnel insulating film 5 as shown in FIG.

Before performing the erase operation of injecting electrons 10 into the floating gate 6, channel hot electrons are generated as shown in FIG.
At this time, the condition of the voltage applied to each region is V
_cg is 5V or more and less than 12V, V _d is more than 3V and 8V
Below, using a condition that 0V and V _s and a V _b. Also,
V _cg is controlled to be equal to or more than the value of V _d . By applying a voltage to each region as described above, channel hot electrons 10 are generated near the boundary region between the drain region 2 and the channel region 4, and the channel hot electrons 10 are injected into the tunnel insulating film 5. . As a result, the holes 11 in the tunnel insulating film 5 can be coupled to and extinguished with the channel hot electrons 10, so that the film quality of the tunnel insulating film 5 can be prevented from being deteriorated.

FIGS. 6A to 6F are band diagrams for explaining a process in which the holes 11 in the tunnel insulating film 5 are combined with and disappear from the channel hot electrons 10. Hereinafter, with reference to FIGS. 6A to 6F, a description will be given of a process in which the holes 11 in the tunnel insulating film 5 are combined with and disappear from the channel hot electrons 10. FIG.

First, FIG. 6A is a band diagram corresponding to a state after a write operation in which electrons 10 are extracted from the floating gate 6 shown in FIG. Thus, since the holes 11 exist in the tunnel insulating film 5, the potential well 13 is formed.

FIG. 6B is a band diagram corresponding to a state where the channel hot electrons 10 shown in FIG. 5 are generated. Some of the channel hot electrons 10 having sufficient energy to overcome the barrier are injected into the tunnel insulating film 5. However, at this time, the channel hot electrons 1
0 is intended for coupling with the holes 11 in the tunnel insulating film 5, it is not necessary to have energy large enough to reach the floating gate 6.
Even if 0 arrives, a larger amount of electrons than the channel hot electrons 10 are injected into the floating gate 6 due to the FN tunnel phenomenon as will be described later, so that the energy of the channel hot electrons 10 is not strictly controlled. You may.

Next, since a positive voltage V _cg is applied to the control gate 8, the channel hot electrons 10 in the tunnel insulating film 5 move to the floating gate 6 side as shown in FIG. I do.

Next, as shown in FIG. 6D, while moving in the tunnel insulating film 5, the channel hot electrons 1
0 is trapped in the potential well 13.

Next, as shown in FIG. 6E, the channel hot electrons 10 trapped in the potential well 13 and the holes 11 are coupled.

As a result, as shown in FIG.
The holes 11 in the tunnel insulating film 5 disappear. Thus, the tunnel insulating film 5 recovers from the deteriorated state in which the holes 11 are formed. As described above, prior to the electron injection into the floating gate 6 by the FN tunnel phenomenon,
Since the channel hot electrons 10 are injected into the tunnel insulating film 5, the holes 11 in the tunnel insulating film 5 combine with and disappear from the channel hot electrons 10. Therefore, holes 11 are not accumulated in tunnel insulating film 5 even if erasing / writing of the flash memory is repeated.

After the injection of the hot electrons 10 into the tunnel insulating film 5 shown in FIG. 5, the electrons 10 are applied to the floating gate 6 from the entire surface of the tunnel insulating film 5 by the FN tunnel phenomenon as shown in FIG. inject. The conditions at this time are the same as the conditions shown in FIG.

FIG. 8 is a graph showing the results of a test for confirming the effect of the control method according to the first embodiment of the present invention. The vertical axis indicates the threshold voltage of the flash memory, and the horizontal axis indicates the number of erase / write operation cycles of the flash memory. In the graph, open circles and squares indicate changes in threshold voltage due to the conventional control method (erasing using only electron injection by FN tunneling), and solid circles and squares indicate the first embodiment. Control method (tunnel insulating film 5
The method of injecting electrons into the floating gate 6 by the FN tunnel phenomenon after injecting the channel hot electrons 10 into the floating gate 6 shows a change in threshold voltage. Also,
The circle in the graph indicates the threshold voltage in a state where the electrons 10 are accumulated in the floating gate 6 (erased state), and the square in the graph indicates the state in which the electrons 10 are extracted from the floating gate 6 (written state). At the threshold voltage. Conditions such as an applied voltage, an electron injection time, and an electron withdrawal time in this test are determined by the conventional control method and the first embodiment.
And the same control method. Referring to FIG.
In particular, there is a difference in the threshold voltage when electrons are stored in the floating gate 6. This is because, in the case of the conventional control method, as shown in FIG.
The holes 111 generated at the time of pulling out the tunnel insulating film 1
The electrons 110 are injected into the floating gate 106 by the FN tunnel phenomenon while being trapped in the region 05. Therefore, when injecting the electrons 110, the electric field intensity increases due to the holes 111 in the tunnel insulating film 105, thereby increasing the amount of the electrons 110 injected into the floating gate 106. Then, the erase / write operation is repeated, and as the number of holes 111 in the tunnel insulating film 105 increases and the film quality of the tunnel insulating film 105 deteriorates, the applied voltage is not changed, but is stored in the floating gate 106. Electrons 110 increase.
Therefore, as the number of erase / write operation cycles increases, the threshold voltage increases in the conventional control method, and the reliability of the flash memory decreases. On the other hand, in the control method according to the first embodiment, the channel hot electrons 10 are injected into the tunnel insulating film 5 as shown in FIG. Holes 11 are erased. Therefore, even if the number of erase / write cycles increases, the holes 11 do not accumulate inside the tunnel insulating film 5 and the quality of the tunnel insulating film 5 does not deteriorate. Then, the threshold voltage hardly changes and the reliability of the flash memory does not decrease.

(Second Embodiment) A DINOR type flash memory according to a second embodiment of the present invention has a structure similar to that of the DINOR type flash memory according to the first embodiment shown in FIG.

FIGS. 9 and 11 show a second embodiment of the present invention.
FIG. 3 is a cross-sectional structure diagram for describing an erasing operation of the DINOR type flash memory according to FIG. Hereinafter, an erasing operation of the DINOR type flash memory according to the second embodiment will be described with reference to FIGS.

First, according to the first embodiment shown in FIGS.
The erase / write operation is performed in the same manner as the operation. Do
4, holes 11 are formed in the tunnel insulating film 5 as shown in FIG.
It will be in an existing state. In the second embodiment,
As shown in FIG.
Before injection, holes 11 in tunnel insulating film 5 are eliminated.
Therefore, the substrate hot electrons 10 are generated. this
The condition of the voltage applied to each region at the time is V_cgTo
V_dOr V_sNot less than 12V, V_dOr V
_sIs V_POver and less than 4V, V_PExceeds 0V and 1.2
V or less, V_nIs 0V. V_bIs 0V
Or Floating. Where V_nIs a semiconductor
It surrounds the p-type well 14 formed on the main surface of the substrate 10.
The voltage applied to the n-type well 15 thus formed is shown.
You. And V_PIs formed on the main surface of the semiconductor substrate 10
Represents the voltage applied to the p-type well 14. Ma
V _dAnd V_sApply a voltage to either one of
The other side, which does not apply a voltage, can be used as a Floating
Good, V_dAnd V_sAnd apply the same voltage to both
Is also good. By applying a voltage to each area in this way,
Near the boundary region between the channel region 4 and the tunnel insulating film 5.
Near the substrate hot electrons 10 are generated. So
Then, the substrate hot electrons 10 are
Tunnel, because a positive voltage is applied to the
It is injected into the rim 5. As a result, in the tunnel insulating film 5
Holes 11 are combined with the substrate hot electrons 10 and disappear.
To prevent the quality of the tunnel insulating film 5 from deteriorating.
Can be stopped.

FIGS. 10A to 10F show that the holes 11 in the tunnel insulating film 5 correspond to the substrate hot electrons 1.
6 is a band diagram for explaining a process of combining and disappearing with 0. Hereinafter, a process in which the holes 11 in the tunnel insulating film 5 are combined with and disappear from the substrate hot electrons 10 will be described with reference to FIGS.

First, FIG. 10A is a band diagram corresponding to a state after the writing operation in which the electrons 10 are extracted from the floating gate 6 shown in FIG. Thus, since the holes 11 exist in the tunnel insulating film 5, the potential well 13 is formed. Next, FIG.
(B) is a band diagram corresponding to a state where the substrate hot electrons 10 shown in FIG. 9 are generated. Some of the substrate hot electrons 10 having sufficient energy to get over the barrier are injected into the tunnel insulating film 5. However, since the substrate hot electrons 10 at this time are intended to bond with the holes 11 in the tunnel insulating film 5, the floating gate 6
It is not necessary to have enough energy to reach
Further, even if the substrate hot electrons 10 reach the floating gate 6, a larger amount of electrons than the substrate hot electrons 10 are injected into the floating gate 6 due to the FN tunnel phenomenon as described later. The ten energies need not be strictly controlled.

Next, since a positive voltage V _cg is applied to the control gate 8, the substrate hot electrons 10 in the tunnel insulating film 5 are _removed as shown in FIG.
Moves to the floating gate 6 side.

Next, as shown in FIG. 10D, while moving through the tunnel insulating film 5, the substrate hot electrons 10
Is trapped in the potential well 13.

Next, as shown in FIG. 10E, the substrate hot electrons 10 trapped in the potential well 13 and the holes 11 are coupled.

As a result, as shown in FIG. 10F, the holes 11 in the tunnel insulating film 5 disappear. Thus, the tunnel insulating film 5 recovers from the deteriorated state in which the holes 11 are formed. As described above, since the substrate hot electrons 10 are injected into the tunnel insulating film 5 prior to the electron injection into the floating gate 6 by the FN tunnel phenomenon, the holes 11 in the tunnel insulating film 5 are combined with the substrate hot electrons 10. Disappear. Therefore, holes 11 are not accumulated in tunnel insulating film 5 even if the erasing / writing operation of the flash memory is repeated.

After the injection of the hot electrons 10 into the tunnel insulating film 5 shown in FIG. 9, the electrons 10 are applied to the floating gate 6 from the entire surface of the tunnel insulating film 5 to the floating gate 6 by the FN tunnel phenomenon as shown in FIG. inject.
At this time, the conditions for applying a voltage to each region are the same as the conditions according to the first embodiment shown in FIG.

FIG. 12 is a graph showing the results of a test for confirming the effect of the control method according to the second embodiment of the present invention. The vertical axis indicates the threshold voltage of the flash memory, and the horizontal axis indicates the number of erase / write operation cycles of the flash memory. In the graph, white circles and squares indicate changes in threshold voltage due to the conventional control method (erasing operation using only electron injection by FN tunneling), and solid circles and squares indicate the embodiment. 1 shows a change in threshold voltage according to the control method 1 (a method in which electrons are injected into the floating gate 6 by the FN tunnel phenomenon after the substrate hot electrons are injected into the tunnel insulating film 5). The circle in the graph indicates the threshold voltage in a state where the electrons 10 are accumulated in the floating gate 6 (erased state), and the square in the graph indicates the state in which the electrons 10 are extracted from the floating gate 6 (writing). (State). Conditions such as applied voltage, electron injection time, and electron withdrawal time in this test are the same between the conventional control method and the control method according to the second embodiment. Referring to FIG.
As in the case of the first embodiment shown in FIG. 8, the threshold voltage particularly when electrons are accumulated in the floating gate 6 is gradually increased in the case of the conventional control method. This is because, in the case of the conventional control method, the number of holes 11 in the tunnel insulating film 5 increases as the number of erase / write operation cycles increases, as in the test in the first embodiment. is there. On the other hand, in the control method according to the second embodiment, the hot holes 11 in the tunnel insulating film 5 are erased by injecting the substrate hot electrons into the tunnel insulating film 5 before the injection of the electrons 10 into the floating gate 6. doing. Therefore, even if the number of erase / write cycles increases, the holes 11 are not accumulated inside the tunnel insulating film 5, and the film quality of the tunnel insulating film 5 does not deteriorate. As a result, the threshold voltage hardly changes and the reliability of the flash memory does not decrease.

(Embodiment 3) The NOR flash memory according to Embodiment 3 of the present invention has the same structure as the DINOR flash memory according to Embodiment 1 shown in FIG. Here, as disclosed in IEDM Tech. Dig. Pp. 115-118 (1990), the NOR type flash memory has a state in which the electrons 10 are accumulated in the floating gate 6 and a state in which the electrons 10 are stored in the floating gate 6. The state where the electrons 10 are pulled out is the erased state.

FIGS. 13 to 16 and 18 are cross-sectional structural views for explaining an erasing / writing operation of the NOR flash memory according to the third embodiment of the present invention. Hereinafter, FIG.
The erase / write operation of the NOR flash memory according to the third embodiment will be described with reference to FIGS.

First, the write operation of the NOR type flash memory will be described with reference to FIG. V _cg to 12V, V _d
The 5V, Grounding V _s, channel hot electrons are generated, electrons 10 into the floating gate 6 is injected. As a result, electrons 10
Is accumulated, and the writing operation of the flash memory is performed.

Next, an erasing operation of the NOR type flash memory will be described with reference to FIG. V _cg -12V, V
_s The 5V, when the V _d and Floating, between the floating gate 6 and the source region 3, FN tunneling phenomenon occurs, electrons 10 in the floating gate 6 is withdrawn into the source region 3. At this time, a high electric field generated between the floating gate 6 and the source region 3 causes
A band-to-band tunnel phenomenon occurs. Thereby, the electron 1
A pair of 0 and a hole 11 is generated, and a part of the hole 11 is trapped in the tunnel insulating film 5 as shown in FIG. At this time, the floating gate 6 and the source region 3
A band-to-band tunnel phenomenon occurs between the holes and holes 11 are formed.
The density of 1 is higher in the region on the source region 3 side.

Then, before performing a write operation of injecting electrons 10 into floating gate 6, channel hot electrons 10 are generated as shown in FIG. At this time, the channel hot electron 1 near the region in the tunnel insulating film 5 where a large number of holes 11 are distributed.
In order to generate the 0, as a condition of the voltage applied to each region, V _cg is 5V or more and less than 12V, V _s or more 3V and 8V or less, using a condition that 0V and V _d and V _b. Further, V _cg is controlled to be equal to or more than the value of V _s .
By applying a voltage to each region in this manner, channel hot electrons 10 are generated near the boundary region between source region 3 and channel region 4, and channel hot electrons 10 are injected into tunnel insulating film 5. . As a result, the holes 11 in the tunnel insulating film 5 can be coupled to and extinguished with the channel hot electrons 10, so that the film quality of the tunnel insulating film 5 can be prevented from being deteriorated.

Here, FIGS. 17A to 17F are band diagrams for explaining a process in which the holes 11 in the tunnel insulating film 5 are combined with and disappear from the channel hot electrons 10, and FIGS. This is basically the same as the band diagrams shown in (a) to (f). In the third embodiment, as in the first embodiment, the channel hot electrons 10 are trapped in the potential well 13 in the tunnel insulating film 5 and then combined with the holes 11. The holes 11 disappear. Therefore, even when the erasing / writing operation of the flash memory is repeated, holes 11 are not accumulated in tunnel insulating film 5.

Then, the tunnel insulating film 5 shown in FIG.
After injection of channel hot electrons 10 into FIG.
As shown in FIG. 8, channel hot electrons 10 are injected into the floating gate 6. The condition of the voltage applied to each region at this time is the same as in the case of the write operation shown in FIG.

It should be understood that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims. For example, in Embodiments 1-3, DINO
R-type and NOR-type flash memories have been described. However, such a problem that the film quality of the tunnel insulating film is deteriorated is disclosed in IEDM Tech. Dig. P. 991 (1992).
The same problem can occur in the ND type flash memory, and the present invention is applicable to such an AND type flash memory.

[0052]

As described above, according to the first to fifth aspects of the present invention, in the control method of the nonvolatile semiconductor memory device capable of electrically writing and erasing information, electrons are injected into the floating gate. Since the step of injecting electrons into the tunnel insulating film is performed before the step, the accumulation of holes in the tunnel insulating film can be prevented. As a result, deterioration of the film quality of the tunnel insulating film is prevented,
Which can prevent a decrease in the reliability of the nonvolatile semiconductor memory device,
A method for controlling a nonvolatile semiconductor memory device can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional structural view showing a DINOR type flash memory according to a first embodiment of the present invention.

FIG. 2 shows a DINOR according to the first embodiment shown in FIG.
FIG. 4 is a cross-sectional structure diagram for explaining an erasing step of the flash memory.

FIG. 3 shows a DINOR according to the first embodiment shown in FIG.
FIG. 4 is a cross-sectional structure diagram for describing a writing step of the flash memory.

FIG. 4 shows a DINOR according to the first embodiment shown in FIG.
FIG. 4 is a cross-sectional structure diagram for describing a state after a writing step of the flash memory of the present invention.

5 is a DINOR according to the first embodiment shown in FIG.
FIG. 3 is a cross-sectional structure diagram for describing an operation of injecting channel hot electrons into a tunnel insulating film of a flash memory of the type.

FIG. 6 shows a DINOR according to the first embodiment shown in FIG.
4 is a band diagram for explaining a process in which holes in a tunnel insulating film of a flash memory are eliminated.

FIG. 7 shows a DINOR according to the first embodiment shown in FIG.
FIG. 4 is a cross-sectional structure diagram for explaining an erasing operation of the flash memory.

FIG. 8 shows a DINOR according to the first embodiment shown in FIG.
4 is a graph showing the results of a test for confirming the effect of the control method of the flash memory.

FIG. 9 is a sectional structural view for explaining an operation of injecting substrate hot electrons into a tunnel insulating film of the DINOR type flash memory according to the second embodiment of the present invention;

FIG. 10 is a band diagram for explaining a process in which holes in a tunnel insulating film of a DINOR type flash memory according to a second embodiment of the present invention disappear.

FIG. 11 is a sectional structural view for explaining an erasing operation of the DINOR type flash memory according to the second embodiment of the present invention;

FIG. 12 is a graph showing the results of a test for confirming the effect of the DINOR type flash memory control method according to the second embodiment.

FIG. 13 is a cross-sectional structure diagram for describing a write operation of the NOR flash memory according to the third embodiment;

FIG. 14 is a sectional structural view for illustrating an erasing operation of the NOR type flash memory according to the third embodiment;

FIG. 15 is a sectional structural view for illustrating a state after an erase operation of the NOR flash memory according to the third embodiment;

FIG. 16 is a sectional structural view for explaining an operation of injecting channel hot electrons into a tunnel insulating film of the NOR type flash memory according to the third embodiment.

FIG. 17 is a band diagram for explaining a process in which holes in the tunnel insulating film of the NOR flash memory according to the third embodiment disappear.

FIG. 18 is a cross-sectional structure diagram for describing a write operation of the NOR flash memory according to the third embodiment;

FIG. 19 is a sectional structural view showing a conventional DINOR type flash memory.

FIG. 20 is a cross-sectional structure diagram for describing an erasing operation of a conventional DINOR type flash memory.

FIG. 21 is a cross-sectional structure diagram for describing a write operation of a conventional DINOR type flash memory.

FIG. 22 is a cross-sectional structure diagram for describing a state in which a band-to-band tunnel phenomenon has occurred in a writing operation of a conventional DINOR type flash memory.

FIG. 23 is a cross-sectional structure diagram for explaining a state where an erasing operation is performed in a state where holes are accumulated in a tunnel insulating film in a conventional DINOR type flash memory.

[Explanation of symbols]

1 semiconductor substrate, 2 source region, 3 drain region,
4 channel region, 5 tunnel insulating film, 6 floating gate, 7 insulating film, 8 control gate, 9
a, 9b Sidewall oxide film, 10 electrons, 11
Holes, 12 depleted regions, 13 potential wells, 1
4,15 wells.

Claims (5)

[Claims] 1. A method for controlling a nonvolatile semiconductor memory device comprising a floating gate, a tunnel insulating film, first and second source / drain regions, and a control gate, wherein electrons are supplied to the tunnel insulating film. After the step of injecting, and the step of injecting electrons into the tunnel insulating film,
Injecting electrons into the floating gate. 2. A channel hot electron generated when electrons injected into the tunnel insulating film are applied by applying a positive voltage to the first source / drain region and grounding the second source / drain region. 2. The method for controlling a nonvolatile semiconductor memory device according to claim 1, wherein 3. The method according to claim 1, wherein the electrons injected into the tunnel insulating film are substrate hot electrons generated by applying a positive voltage to a control gate. 4. The step of injecting electrons into the floating gate comprises applying a positive voltage to the control gate and grounding the source region to generate electrons in the floating gate by a Fowler-Nordheim tunnel phenomenon. Injecting
A method for controlling a nonvolatile semiconductor memory device according to claim 2. 5. The method according to claim 1, wherein the electrons accumulated in the floating gate are applied to the first source / drain region by utilizing a Fowler-Nordheim tunnel phenomenon generated by applying a positive voltage to the first source / drain region. 3. The method for controlling a nonvolatile semiconductor memory device according to claim 2, further comprising the step of extracting to a drain region.