CN100442515C - Electronic device - Google Patents

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Publication number
CN100442515C
CN100442515C CNB038029170A CN03802917A CN100442515C CN 100442515 C CN100442515 C CN 100442515C CN B038029170 A CNB038029170 A CN B038029170A CN 03802917 A CN03802917 A CN 03802917A CN 100442515 C CN100442515 C CN 100442515C
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current source
electrode
wire
source lead
resistor
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CN1708851A (en
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M·K·克里
R·基维特
M·朱
J·张
C·J·塔泰勒
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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Abstract

The invention relates to an electronic device provided with an electronic component which comprises an integrated circuit arrangement including a 'semiconducting substrate, active components, and passive components such as capacitors and resistors. The resistors comprise materials of a high resistivity and can be manufactured with resistance values which lie within a narrow tolerance range. The resistor comprises a material chosen from the group comprising: (3-tantalum, TaxNy (0 <= x <= 1, . , 0 <= Y <= 1), TA1-x-ySiNy (0 <= x <= 1, 0 <= Y <= 1), TA1-x-yA1xNy (0 <= x <= 1, 0 <= Y <= 1), NIxCry (0 <= x <= 1, 0 <= Y <= 1), NIxCryA1z (0 <= x <= 1, 0 <= y <= 1, 0 <= Z <= 1), TIxWy(0 <= x <= 1, 0 <= Y <= 1), TIxWyNz(0 <= x <= 1, 0 <= y <= 1, 0 <= Z <= 1), TIxNy(0 <= x <= 1, 0 <= Y <= 1)AND CUxNiy(0 <= x <= 1, 0 <= y <= 1). The invention further relates to a transmitter, a receiver, an electronic component, a peripheral circuit, a current supply circuit, a filter module, and an integrated circuit arrangement.

Description

Integrated circuit
Technical field
The present invention relates to dispose the electronic equipment of the electronic component that comprises integrated circuit, this integrated circuit comprises having at least one active element and be electrically coupled at least one capacitor of this active element and the Semiconductor substrate of at least one resistor on described Semiconductor substrate.The invention further relates to transmitter, receiver, peripheral circuit, current source circuit, filter module, electronic component and integrated circuit.
Nowadays, capacitor-resistor network is used in many equipment of electronic data processing or mobile communication.Usually by thick film technology these networks are produced on the ceramic substrate.The shortcoming of this technology is that the electric capacity position of capacitor and/or the resistance value of resistor only can make with the wide margin of tolerance.In addition, do not have active element, can be integrated in these networks such as diode.
For example, EP0192989 discloses the integrated circuit that comprises transistor, capacitor and resistor.Two electrodes of capacitor and resistor have been formed by polysilicon layer.
Because polysilicon is compatible mutually with semi-conductive standard manufacture craft, so polysilicon is widely used as electrode or resistor material in semiconductor element.Use polysilicon to be the particle size of restive polysilicon in the manufacturing process of polysilicon layer as the shortcoming of electrode or resistor material.Further shortcoming is restive doping level in the manufacture process of doped polycrystalline silicon layer.
These two kinds of influences cause the resistance value of the capacitance of capacitor and/or resistor only can be provided with to have the wide margin of tolerance.
In addition, polysilicon has low-resistivity, makes to have only by the resistance bending to produce high resistance position in circuit, and it occupies more space.
Therefore one object of the present invention is to provide the electronic equipment that comprises electronic component, this electronic component is joined to be and is had improved integrated circuit, and this integrated circuit comprises Semiconductor substrate, at least one active element, at least one capacitor and at least one resistor.
Realized this purpose by the electronic equipment that disposes the electronic component that comprises integrated circuit, integrated circuit has input and output, and comprise: Semiconductor substrate, described Semiconductor substrate comprise the dopant of first doping type with first doping content (n1) and have at least one active element; At least one capacitor that comprises first electrode, second electrode and first dielectric layer; With at least one resistor, described resistor comprises the material that is selected from following: β-tantalum, Ta xN Y(0＜x≤1,0＜y≤1), Ta 1-x-ySi xN y(0＜x≤1,0＜y≤1), Ta 1-x-yAl xN y(0＜x≤1,0＜y≤1), Ni xCr y(0＜x≤1,0＜y≤1), Ni xCr xAl z(0＜x≤1,0＜y≤1,0＜z≤1), Si xCr xO z(0＜x≤1,0＜y≤1,0＜z≤≤ 1), Si xCr xN z(0＜x≤1,0＜y≤1,0＜z≤1), Ti xW y(0＜x≤1,0＜y≤1), Ti xW yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ti xN y(0＜x≤1,0＜y≤1) and Cu xNi y(0＜x≤1,0＜y≤1), described resistor and mos capacitance device are electrically coupled to the wherein said active element of active element and are the diode as overvoltage protective device, described diode is formed by first semiconductor regions of the dopant of first doping type with second doping content (n2) and second semiconductor regions of dopant with second doping type of the 3rd doping content, wherein said diode is electrically connected to input by first current source lead-in wire, and described second doping content (n2) is lower than first doping content (n1) of substrate (1); Be provided at the insulating barrier on the Semiconductor substrate, described insulating barrier interrupts in some zone, wherein said capacitor is restricted to the mos capacitance device, the Semiconductor substrate of described mos capacitance device is as first electrode, described Semiconductor substrate is by the 4th current source lead-in wire ground connection, between the described Semiconductor substrate and first dielectric layer first oxide skin(coating) is set, second electrode of described capacitor is coupled to described first current source lead-in wire; Be positioned at the 3rd dielectric layer on the insulating barrier, in some zones on described the 3rd dielectric layer, be provided with the second layer with resistance value to form described resistor, described resistor is electrically coupled to second electrode of described capacitor and is connected to output by the 3rd current source lead-in wire; And be arranged on protective layer on the entire circuit.
The layer of these materials can provide high homogeneity, so that can make the resistor that its resistance value is positioned at the narrow margin of tolerance.
Further advantage is that these materials have high resistivity value.Owing to these higher resistivity values, can reduce the external dimensions of resistor.Valuable semi-conducting material can be saved like this, and lower technology cost can be guaranteed.Further advantage is that these materials have 0 to 100ppm/K low TCR value (temperature coefficient of resistance).Make the resistance value of resistor in the electronic device works process, have only slight variation like this.
If capacitor advantageously is configured to MOS (metal-oxide semiconductor (MOS)) capacitor, then its capacitance of the capacitor that is obtained is for example compared the electric capacity position of the capacitor of two electrodes of polysilicon with having semi-conducting material, is within the narrower margin of tolerance.
The feasible range of application that might widen electronic component and electronic equipment therefore of the advantageous embodiment of integrated circuit configuration of the present invention.
The invention further relates to transmitter, receiver, each comprises the electronic component with integrated circuit, the invention still further relates to electricity in element, peripheral circuit, current source circuit and filter module, and wherein each comprises integrated circuit recited above.
By five accompanying drawings of reference, the present invention now obtains more detailed explanation, in the accompanying drawing:
Each is the schematic cross-sectional view with Semiconductor substrate of diode, mos capacitance device and resistor for Fig. 1 and Fig. 2,
Fig. 3 is the schematic cross-sectional view with Semiconductor substrate of diode, mos capacitance device and resistor and other capacitor,
Fig. 4 and Fig. 5 show possible circuit arrangement.
Embodiment
Electronic equipment can be for example to be used for the equipment of electronic data processing, such as computer, kneetop computer or PDA (personal digital assistant).Replacedly, electronic equipment can be the mobile data transmission equipment such as mobile phone.
Mobile telephone equipment comprises: for example power subsystem, display device, loud speaker, microphone, input equipment, memory devices, antenna, transmitter, receiver, peripheral circuit, filter module and current source circuit.Each can comprise the electronic component with integrated circuit transmitter, receiver, peripheral circuit, filter module and current source circuit, this integrated circuit comprises having at least one active element, be provided on this Semiconductor substrate and be electrically coupled at least one capacitor of this active element and the Semiconductor substrate of at least one resistor, and wherein this resistor comprises the material that is selected from following: β-tantalum, Ta xN y(0＜x≤1,0＜y≤1), Ta 1-x-ySi xN y(0＜x≤1,0＜y≤1), Ta 1-x-yAl xN y(0＜x≤1,0＜y≤1), Ni xCr y(0＜x≤1,0＜y≤1), Ni xCr yAl z(0＜x≤1,0＜y≤1,0＜z≤1), Si xCr yO z(0＜x≤1,0＜y≤1,0＜z≤1), Si xCr yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ti xW y(0＜x≤1,0＜y≤1), Ti xW yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ti xN y(0＜x≤1,0＜y≤1) and Cu xNi y(0＜x≤1,0＜y≤1).
This active element can be, for example diode or transistor.Diode is as for example overvoltage protective device in circuit arrangement.Diode can be for example pn diode, Zener diode, diode (diode that differential concatenation connects), front and back diode (diode that is connected in series) or floating boom diode back-to-back.
Transistor can be, for example bipolar transistor or field-effect transistor (FET) are such as junction field effect transistor (JFET), P-channel metal-oxide-semiconductor field-effect transistor (PMOS-FET), n channel metal oxide semiconductor field effect transistor (NMOS-FET) or complementary metal oxide semiconductor field effect transistor (CMOS-FET).
Fig. 1 is the schematic cross-sectional view with Semiconductor substrate 1 of pn diode, mos capacitance device and resistor.This Semiconductor substrate 1 comprises, for example, Si with first doping type dopant of the first doping content n1, perhaps III/IV family semiconductor, GaAs such as the first doping type dopant with first doping content n1, the SiC semiconductor that perhaps has the first doping type dopant of the first doping content n1 perhaps has the SiGe semiconductor of the first doping type dopant of the first doping content n1.In this Semiconductor substrate 1, there is first semiconductor regions 2, it comprises the Si or the III/IV family semiconductor of the first doping type dopant with second doping content n2, such as the GaAs of the first doping type dopant with second doping content n2 or have the SiC semiconductor of the first doping type dopant of the second doping content n2.Doping content n2 in first semiconductor regions 2 is lower than the doping content n1 in Semiconductor substrate 1.The second less semiconductor regions 3 appears in the first semiconductor region city 2, second semiconductor regions 3 comprises the Si or the III/IV family semiconductor of the second doping type dopant with the 3rd doping content n3, such as the GaAs of the second doping type dopant with the 3rd doping content n3 or have the SiC of the second doping type dopant of the 3rd doping content n3.The dopant of employed first doping type can be, for example B, Al or Ga, and the dopant of employed second doping type can be, for example P, As or Sb.The first semiconductor region city 2 and second semiconductor regions 3 form the pn diode.
Insulating barrier 4 is provided on Semiconductor substrate 1, and this layer comprises, for example SiO 2, be doped with SiO such as the doping oxide of boron oxide or phosphorous oxide 2, or SiN (H).Insulating barrier 4 interrupts in some zone.In these zones, preferably include SiO 2First oxide skin(coating) 5 be positioned on the Semiconductor substrate 1.Have first dielectric layer 6 on oxide skin(coating) 5, this first dielectric layer 6 for example comprises Si 3N 4, Si xO yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ta 2O 5, (Ta 2O 5) x-(Al 2O 3) 1-x(0＜x≤1), (Ta 2O 5) x-(TiO 2) 1-x(0＜x≤1), (Ta 2O 5) x-(Nb 2O 5) 1-x(0＜x≤1), (Ta 2O 5) x-(SiO 2) 1-x(0＜x≤1), TiO 2, ZrO 2, HfO 2Perhaps Nb 2O 5First conductive layer 7 that can comprise for example poly-Si, Ta or Al is positioned on first dielectric layer 6.Second oxide skin(coating) 8 is provided on first conductive layer 7, has preferably included SiO 2Have second dielectric layer 9 on second oxide skin(coating) 8, this second dielectric layer 9 comprises for example Si 3N 4, Si xO yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ta 2O 5, (Ta 2O 5) x-(Al 2O 3) 1-x(0＜x≤1), (Ta 2O 5) x-(TiO 2) 1-x(0＜x≤1), (Ta 2O 5) x-(Nb 2O 5) 1-x(0＜x≤1), (Ta 2O 5) x-(SiO 2) 1-x(0＜x≤1), TiO 2, ZrO 2, HfO 2Perhaps Nb 2O 5
Ground floor 10 with resistance value is provided on second dielectric layer 9, and this layer 10 comprises, for example β-tantalum, Ta xN y(0＜x≤1,0＜y≤1), Ta 1-x-ySi xN y(0＜x≤1,0＜y≤1), Ta 1- X-yAl xN y(0＜x≤1,0＜y≤1), Ni xCr y(0＜x≤1,0＜y≤1), Ni xCr yAl z(0＜x≤1,0＜y≤1,0＜z≤1), Si xCr yO z(0＜x≤1,0＜y≤1,0＜z≤1), Si xCr yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ti xW y(0＜x≤1,0＜y≤1), Ti xW yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ti xN y(0＜x≤1,0＜y≤1) or Cu xNi y(0＜x≤1,0＜y≤1).
The 3rd dielectric layer 11 is positioned on the insulating barrier 4, and this layer 11 comprises, for example Si 3N 4, Si xO yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ta 2O 5, (Ta 2O 5) x-(Al 2O 3) 1-x(0＜x≤1), (Ta 2O 5) x-(TiO 2) 1-x(0＜x≤1), (Ta 2O 5) x-(Nb 2O 5) 1-x(0＜x≤1), (Ta 2O 5) x-(SiO 2) 1-x(0＜x≤1), TiO 2, ZrO 2, HfO 2Person Nb 2O 5On described the 3rd dielectric layer 11, we have found to have the second layer 12 of resistance value in some zones, and this layer 12 comprises, for example β-tantalum, Ta xN y(0＜x≤1,0＜y≤1), Ta 1-x-ySi xN y(0＜x≤1,0＜y≤1), Ta 1- X-yAl xN y(0＜x≤1,0＜y≤1), Ni xCr y(0＜x≤1,0＜y≤1), Ni xCr yAl z(0＜x≤1,0＜y≤1,0＜z≤1), Si xCr yO z(0＜x≤1,0＜y≤1,0＜z≤1), Si xCr yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ti xW y(0＜x≤1,0＜y≤1), Ti xW yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ti xN y(0＜x≤1,0＜y≤1) or Cu xNi y(0＜x≤1,0＜y≤1).Preferably, the second layer 12 with resistance value comprises β-tantalum, Ta xN y(0＜x≤1,0＜y≤1), Ti xW yN z(0＜x≤1,0＜y≤1,0＜z≤1) or Ti xN y(0＜x≤1,0＜y≤1).Protective layer 13 is provided above whole assembly, has for example comprised the combination of organic or inorganic material or inorganic material or the combination of organic and inorganic material.Employed organic material can be, for example polyphenyl and cyclobutane or polyimides, and employed inorganic material can be, for example SiN (H), SiO 2Perhaps Si xO yN z(0＜x≤1,0＜y≤1,0＜z≤1).
Second semiconductor regions 3 of pn diode is electrically connected to the input 15 of circuit arrangement, and is electrically connected to first conductive layer 7 by first current source lead-in wire 14, and the ground floor 10 with resistance value is by second current source lead-in wire ground connection.Make up first conductive layer 7, make its with the second layer 12 with resistance value physically and electrically contact.For this purpose, the second layer 12 that can make up first conductive layer 7 and have resistance value makes it be set to overlap or adjacent to each other.The second layer 12 with resistance value is electrically connected to the output 18 of circuit arrangement by the 3rd current source lead-in wire 17.Semiconductor substrate 1 is by the 4th current source 19 ground connection that go between.Form current source lead-in wire 14,16,17,19 by the contact hole that is filled with electric conducting material.Current source lead-in wire can comprise one or several electric conducting materials, for example with the form of sequence of layer.Like this, for example, the material with resistance value that provides with the 3rd layer 20 form with resistance value can be provided first current source lead-in wire 14, and the material 21 with good electrical conductivity, such as Al, be doped with the Al of Cu or be doped with the Al of Si.The 4th current source lead-in wire 19 can be by the material with resistance value that for example provides with the 4th layer 22 form with resistance value, and the material 23 with good electrical conductivity, such as Al, be doped with the Al of Cu or be doped with the Al structure of Si.
In this embodiment of the present invention, formed the mos capacitance device by following layer: Semiconductor substrate 1.Oxide skin(coating) 5, first electric Jie's shield layer 6, first conductive layer 7, second oxide skin(coating) 8, second dielectric layer 9 and first resistive layer 10.Mos capacitance utensil in this embodiment has double stack construction.Semiconductor substrate 1 is here as first electrode, and first resistive layer 10 is as second electrode, and first conductive layer 7 is as the target of mos capacitance device.
Replacedly, can omit first resistive layer 10 in this structure, in this case, current source lead-in wire 16 will be as second electrode of mos capacitance device.
Depend on the material that is used for first conductive layer 7, for example, can omit second oxide skin(coating) 8.For example, if Ta or Al then can omit second oxide skin(coating) 8 as the material of first conductive layer 7.In addition, can also omit first oxide skin(coating) 5.
Replacedly, the mos capacitance device can have single laminated construction.In this embodiment, for example form the mos capacitance device by Semiconductor substrate 1, first oxide skin(coating) 5, first dielectric layer 6 and first resistive layer 10.Replacedly, in this embodiment of mos capacitance device, can also omit first resistive layer 10 once more, and form second electrode of mos capacitance device then by second current source lead-in wire 16.
Replacedly, the mos capacitance device can have many laminated construction.Depend on the mos capacitance device the quantity of the lamination that will have, the oxide skin(coating) of corresponding number, dielectric layer and conductive layer are deposited between first electrode and second electrode of this mos capacitance device.Replacedly, in many laminated construction, can omit oxide skin(coating), and the dielectric layer of corresponding number and conductive layer are deposited between first electrode and second electrode of this mos capacitance device.
Fig. 2 is the schematic cross-sectional view with Semiconductor substrate 1 of pn diode, mos capacitance device and resistor, and wherein the mos capacitance utensil has single laminated construction.In this embodiment, second current source lead-in wire 16 does not have ground connection.
The pn diode that forms by first semiconductor regions 2 and second semiconductor regions 3 appears in the Semiconductor substrate 1.Insulating barrier 4 is provided on the Semiconductor substrate 1 and in several zones and breaks.In these zones, first dielectric layer 6 is positioned on the Semiconductor substrate 1.The 3rd dielectric layer 11 is positioned on the insulating barrier 4.In several zones, second resistive layer 12 is positioned on the 3rd dielectric layer 11.Protective layer 13 appears on the dielectric layer 11 and second resistive layer 12.Second semiconductor regions 3 is electrically connected to the input 15 of circuit arrangement by first current source lead-in wire 14.Second electrode that second current source lead-in wire 16 forms the mos capacitance device.In addition, second current source lead-in wire 16 is connected to second resistive layer 12 with the mos capacitance device.This mos capacitance device is electrically connected to second semiconductor regions 3, and is electrically connected to the input 15 of circuit arrangement by first current source lead-in wire, 14 and second current source lead-in wire 16 that electrically contacts.Second resistive layer 12 is connected to the output 18 of circuit arrangement by the 3rd current source lead-in wire 17.Semiconductor substrate 1 is by the 4th current source 23 ground connection that go between.
Fig. 3 has pn diode, a mos capacitance device, the schematic cross-sectional view of the Semiconductor substrate 1 of resistor and other capacitor.In this embodiment of configuration in a circuit according to the invention, second current source lead-in wire 16 is not to be directly electrically connected to second resistive layer 12, but is configured to make it to be used as second electrode of other capacitor extraly it.Construct second resistive layer 12 and make it, and be used as first electrode of other capacitor on the other hand on the one hand as resistor.Appear at second resistive layer 12 and formed the dielectric of other capacitor as the 4th dielectric layer 24 between those zones of second current source lead-in wire 16 of second electrode of other capacitor, the 4th dielectric layer 24 can comprise, for example Si 3N 4, Si xO yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ta 2O 5, (Ta 2O 5) x-(Al 2O 3) 1-x(0＜x≤1), (Ta 2O 5) x-(TiO 2) 1-x(0＜x≤1), (Ta 2O 5) x-(Nb 2O 5) 1-x(0＜x≤1), (Ta 2O 5) x-(SiO 2) 1-x(0＜x≤1), TiO 2, ZrO 2, HfO 2Perhaps Nb 2O 5 Protective layer 13 is provided on the whole assembly.Second current source lead-in wire does not have ground connection in this embodiment.
Replacedly; can construct one or several current source lead-in wires 14,16; 17 or 19 make them can be used as inductance element; so that circuit arrangement comprises inductance and diode, mos capacitance device and resistor; replacedly; have for example spiral two dimension or for example have that the MEMS of the three-dimensional of helicoidal structure (" MEMS (micro electro mechanical system) ") inductance can be provided on the protective layer 13, and can be integrated with circuit arrangement by first and/or second current source lead-in wire 14,16.
The electronic component of finishing can be equipped with, for example standard semiconductor shell, flip-chip shell, plastic casing, wafer-level package or ceramic package.The electrically contacting of electronic component to be subjected to the going between influence of bonding or projection.These are protruding certainly can to comprise, for example NiV/Cu/ (Pb 0.35Sn 0.65), NiV/Cu (Pb 0.4Sn 0.6), NiCr/Cu/Ni/Au or other materials or lead-free combination of materials.
Fig. 4 show have at least one diode D, resistor R and mos capacitance device C MOSThe possible circuit arrangement of network.Resistor R appears at input 15 and exports between 18.Diode D is between input 15 and ground.Mos capacitance device C MOSFirst splicing ear the input 15 and resistor R between.Mos capacitance device C MOSThe second splicing ear ground connection.For n, that correct is n=1,2,3,4 ... ∞.For m, depend on the structure of mos capacitance device, that correct is m=1,2,3,4 ... ∞.For mos capacitance device with single laminated construction, all as shown in FIG. 2, that correct is m=1.For the mos capacitance device with double stack construction, for example shown in Figure 1, that correct is m=2.For mos capacitance device with many laminated construction, m=3,4 ... ∞.
Diode D, resistor R and mos capacitance device C MOSCan present different, interchangeable configuration.
Fig. 5 show have at least one diode D, resistor R and mos capacitance device C MOSWith other capacitor C AThe possible circuit arrangement of network.Resistor R is in input 15 and export between 18.Other capacitor C AAppear between input 15 and the resistor R.Diode D is connected between input 15 and the ground.Capacitor C MOSFirst splicing ear be positioned at input 15 and other capacitor C ABetween.Capacitor C MOSThe second splicing ear ground connection.For n, that correct is n=1,2,3,4 ... ∞.For m, depend on the structure of mos capacitance device, m=1,2,3,4 ... ∞.
Diode D, resistor R, mos capacitance device C MOSAnd other capacitor C ACan have different, interchangeable configuration equally.
Embodiment
As shown in Figure 1 have a Semiconductor substrate 1 that the electronic component of circuit arrangement as shown in Figure 4 comprises Si, use B as the dopant with first doping type of the first doping content n1, wherein circuit arrangement comprises the input 15 that is configured in circuit arrangement and exports resistor R between 18, is configured in the mos capacitance device C between input 15 and the ground as shown in Figure 4 MOS, and be configured in the input 15 and ground between pn diode D.This Semiconductor substrate 1 has first semiconductor regions 2, and it comprises the Si of use B as the dopant of first doping type with second doping content n2.Doping content n1 is greater than doping content n2.The second less semiconductor regions 3 appears in each first semiconductor regions 2, comprises using the Si of P as the dopant of second doping type with the 3rd doping content n3.Provide SiO on the Semiconductor substrate 1 2 Insulating barrier 4.
Insulating barrier 4 breaks in some zones.In these zones, SiO 2First oxide skin(coating) 5 appear on the Semiconductor substrate 1.Si 3N 4First dielectric layer 6 be positioned on the oxide skin(coating) 5.First conductive layer 7 of polysilicon is positioned on first dielectric layer 6, and SiO 2Second oxide skin(coating) 8 be provided on first conductive layer 7.Si 3N 4Second dielectric layer 9 be provided on second oxide skin(coating) 8.Have resistance value and be provided on second dielectric layer 9 by the ground floor 10 that β-tantalum is made.
Si 3N 4The 3rd dielectric layer 11 appear on the insulating barrier 4, and in some zones, have resistance value and appear on the 3rd dielectric layer 11 by the second layer 12 that β-tantalum is made.Si 3N 4 Protective layer 13 be provided on the whole assembly.
Second semiconductor regions 3 of pn diode is electrically connected to the input 15 of circuit arrangement, and is electrically connected to first conductive layer 7 by first current source lead-in wire 14.First current source lead-in wire 14 comprises the sequence of layer by the layer of the good conductive material 21 of Al conduct of the 3rd resistive layer 20 of β-tantalum and doping Si.Ground floor 10 with resistance value is by second current source, 16 ground connection that go between.Constructing first conductive layer 7 overlaps itself and the second layer 12 with resistance value.The 3rd current source lead-in wire 17 of the Al of the second layer 12 with resistance value by being doped with Si is electrically connected to the output 18 of circuit arrangement.Semiconductor substrate 1 is by the 4th current source 19 ground connection that go between, and the 4th current source lead-in wire 19 comprises having resistance value and the 4th layer 22 of being made as good conductive material 23 by β-tantalum and the Al that is doped with Si.
Such circuit arrangement is used as low pass filter in the mobile phone application apparatus.

Claims (7)

1. one kind has input (15) and exports the integrated circuit of (18), comprising:
Semiconductor substrate (1), described Semiconductor substrate comprise the dopant of first doping type with first doping content (n1) and have at least one active element;
At least one capacitor that comprises first electrode, second electrode and first dielectric layer (6); With
At least one resistor, described resistor comprise the material that is selected from following: β-tantalum, Ta xN Y(0＜x≤1,0＜y≤1), Ta 1-x-ySi xN y(0＜x≤1,0＜y≤1), Ta 1-x-yAl xN y(0＜x≤1,0＜y≤1), Ni xCr y(0＜x≤1,0＜y≤1), Ni xCr xAl z(0＜x≤1,0＜y≤1,0＜z≤1), Si xCr xO z(0＜x≤1,0＜y≤1,0＜z≤1), Si xCr xN z(0＜x≤1,0＜y≤1,0＜z≤1), Ti xW y(0＜x≤1,0＜y≤1), Ti xW yN z(0＜x≤1,0＜y≤1,0＜z≤1), Ti xN y(0＜x≤1,0＜y≤1) and Cu xNi y(0＜x≤1,0＜y≤1), described resistor and mos capacitance device are electrically coupled to active element, it is characterized in that:
Described active element is the diode as overvoltage protective device, described diode is formed by first semiconductor regions (2) of the dopant of first doping type with second doping content (n2) and second semiconductor regions (3) of dopant with second doping type of the 3rd doping content, wherein said diode by first current source go between (14) be electrically connected to input (15), and described second doping content (n2) is lower than first doping content (n1) of substrate (1);
Be provided at the insulating barrier (4) on the Semiconductor substrate (1), described insulating barrier interrupts in some zone, wherein said capacitor is restricted to the mos capacitance device, the Semiconductor substrate of described mos capacitance device (1) is as first electrode, described Semiconductor substrate (1) is by the 4th current source lead-in wire (19) ground connection, between described Semiconductor substrate (1) and first dielectric layer (6) first oxide skin(coating) (5) is set, second electrode of described capacitor is coupled to described first current source lead-in wire (14);
Be positioned at the 3rd dielectric layer (11) on the insulating barrier (4), in some zones on described the 3rd dielectric layer, be provided with the second layer (12) forming described resistor with resistance value, described resistor be electrically coupled to described capacitor second electrode and by the 3rd current source go between (17) be connected to output (18); And
Be arranged on the protective layer (13) on the entire circuit.
2. integrated circuit according to claim 1, wherein said mos capacitance device is a kind of single laminated construction with second current source lead-in wire, this second current source lead-in wire forms and is connected to first current source lead-in wire and resistor.
3. integrated circuit according to claim 1, wherein said mos capacitance device is a kind of double stack construction with first conductive layer, this first conductive layer is as second electrode and be arranged to connect first current source lead-in wire and resistor.
4. integrated circuit according to claim 1, wherein:
Setting has the other capacitor of first electrode and second electrode, is provided with between this first electrode and second electrode as dielectric the 4th dielectric layer (24);
Described mos capacitance device is a kind of single laminated construction with second current source lead-in wire, and this second current source lead-in wire forms and is connected to first current source lead-in wire;
Described second current source lead-in wire is constructed to make it to be used as second electrode of other capacitor extraly;
Described second resistive layer (12) is constructed to make it on the one hand as resistor, is used as first electrode of other capacitor on the other hand.
5. integrated circuit according to claim 1 further comprises first resistive layer (10) that is positioned at described first dielectric layer (6) top, and described first resistive layer (10) is with second electrode of described mos capacitance device.
6. integrated circuit according to claim 1, one of them or several current source lead-in wire (14,16,17,19) are constructed to make them to be used as inductance element, to limit inductance.
7. integrated circuit according to claim 1 further comprises the MENS inductance, and described MENS inductance is positioned on the protective layer and has two dimension or three-dimensional structure, and integrated by first and/or second current source lead-in wire (14,16) and circuit arrangement.
CNB038029170A 2002-01-31 2003-01-27 Electronic device Expired - Fee Related CN100442515C (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54100277A (en) * 1978-01-24 1979-08-07 Mitsubishi Electric Corp Semiconductor element for hybrid integrated circuit
US6208009B1 (en) * 1999-04-30 2001-03-27 Digital Devices, Inc. RC-networks in semiconductor devices and method therefor
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
CN1330406A (en) * 2000-06-20 2002-01-09 光颉科技股份有限公司 RC integrated semiconductor circut with MIS over-voltage protector and its preparing process

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54100277A (en) * 1978-01-24 1979-08-07 Mitsubishi Electric Corp Semiconductor element for hybrid integrated circuit
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6208009B1 (en) * 1999-04-30 2001-03-27 Digital Devices, Inc. RC-networks in semiconductor devices and method therefor
CN1330406A (en) * 2000-06-20 2002-01-09 光颉科技股份有限公司 RC integrated semiconductor circut with MIS over-voltage protector and its preparing process

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