CN1330406A - RC integrated semiconductor circut with MIS over-voltage protector and its preparing process - Google Patents
RC integrated semiconductor circut with MIS over-voltage protector and its preparing process Download PDFInfo
- Publication number
- CN1330406A CN1330406A CN 00118663 CN00118663A CN1330406A CN 1330406 A CN1330406 A CN 1330406A CN 00118663 CN00118663 CN 00118663 CN 00118663 A CN00118663 A CN 00118663A CN 1330406 A CN1330406 A CN 1330406A
- Authority
- CN
- China
- Prior art keywords
- layer
- resistance
- mis
- electric capacity
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
An integrated RC circuit with over-voltage protection of metal insulator semiconductor (MIS) features that there are resistor area, capacitor area, MIS structure, I/O connection area and the connection lines between said areas on a semiconductor substrate. Its advantages are simple preparing process and high protection power.
Description
The present invention relates to a kind of integrated semiconductor circuit and manufacture method thereof, particularly a kind of resistance, electric capacity and MIS (metal-insulator semiconductor's device) overvoltage protector integrated semiconductor circuit and manufacture method thereof.
Traditional RC circuit with protection component is made of resolution element (discrete element) usually, and its shortcoming is: production cost height, circuit layout area are big, need other line during test.And owing to interelement space influences its service speed greatly.Along with the development of semiconductor integrated circuit, present trend is with having the RC circuit integration of protection component, to overcome above-mentioned shortcoming.
Disclose a relevant known technology in the United States Patent (USP) 5355014, have denomination of invention to be: " Semiconductor Device with Integrated RC Network and Schottky Diode ".Fig. 1 represents its circuit, wherein 31,32,33 is respectively Schottky diode (Schottky diode), resistance and electric capacity, and resistance and capacitances in series, and then in parallel with Schottky diode.The negative electrode of Schottky diode 31 is connected in first end of input and resistance 32, its plus earth; First end of electric capacity 33 is connected second end of resistance 32, its second end ground connection.This circuit adopts Schottky diode to protect electric capacity and resistance, discharges big path of current to provide, thus the damage that inhibition overvoltage or Electrostatic Discharge are caused for the RC circuit.
Fig. 2 is the profile of the pairing semiconductor device of circuit of Fig. 1, and it adopts semiconductor technology, is forming respectively on the semi-conductive substrate: the distribution between schottky diode area 31, resistance region 32, capacitor regions 33 and the three.
The RC integrated circuit that this kind has a Schottky diode has overcome the problems referred to above of separating element circuit.Yet with reference to Fig. 2, owing to the complex structure of Schottky diode, corresponding manufacture process is too numerous and diverse, must adopt technologies such as deposit, ion injection even multiple interior connection, so production cost is very high.
In view of this; main purpose of the present invention is to provide integrated RC circuit and the manufacture method thereof of a kind of MIS of employing overvoltage protector as protection component; its biggest advantage is to make simple, and by the parallel connection of a plurality of MIS elements, can provide bigger overvoltage or electrostatic discharge protective power.
According to the semiconductor element theory, if during the insulating barrier very thin (less than 10A) of MIS element, its similar is in Schottky diode.So if adopt appropriate material also suitably to control the thickness of insulating layer of MIS element, the MIS element of then making can be used as protection component equally.Compare with Schottky diode, the semiconductor manufacturing of MIS overvoltage protector is simpler, and four road photoetching are saved in the semiconductor manufacturing of comparable at least Schottky diode; And the current range that can optionally will absorb increases the quantity of MIS element.So adopt the MIS overvoltage protector can absorb bigger electric current, so more effective protection is provided.
According to purpose of the present invention, a kind of RC integrated semiconductor circuit of the MIS of having overvoltage protector is provided, this circuit is respectively by resistance region on semi-conductive substrate; Capacitor regions comprises dielectric layer, upper/lower electrode zone; The MIS structure comprises separator, semiconductor layer and metallic conduction zone; Distribution between one I/O electrode bonding pad and above-mentioned resistance, electric capacity and the MIS structure constitutes.In parallel by the one or more MIS overvoltage protector that forms in parallel with electric capacity, and then connect with above-mentioned resistance, the other end of resistance is connected input.
According to another object of the present invention, the method for the RC integrated semiconductor circuit that a kind of manufacturing has the MIS overvoltage protector is provided, may further comprise the steps: form a substrate; Be covered an insulation film on the whole surface of this substrate, by photoetching and selective etch, form the corresponding resistance of an insulating barrier on this substrate surface and the zone of I/O electrode, in order to avoid this resistance and this I/O electrode join domain and above-mentioned substrate conducting; Form a dielectric layer on whole surface and cover above-mentioned insulating barrier, in order to dielectric material as this electric capacity; By photoetching and selective etch, form this MIS structure; The thin separator of lining one is on the whole surface and be covered on the described dielectric layer, in order to the isolated film as this MIS structure; Be covered a resistive layer on the whole surface and be covered on the described separator, in order to form this resistance; Be covered a barrier layer on the whole surface and cover on the described resistive layer, in case resistive layer and other thin layers interact here; Be covered first conductive layer on the whole surface and cover on the described barrier layer, and in this conductive layer, form two electrodes of this resistance, the metal level of this MIS structure, the battery lead plate and the I/O electrode bonding pad of this electric capacity by photoetching and selective etch, and form required distribution between this resistance, this electric capacity and this MIS structure; By photoetching and selective etch,, remove the barrier layer and first conductive layer above described resistive layer, to form this resistance in the zone of desire formation resistance; Form the whole lower surface of second conductive layer, as the lower electrode layer of this electric capacity at described substrate.
Above-mentioned and other purpose of the present invention, advantage and characteristic are by in the detailed description of following preferred embodiment and with reference to the accompanying drawings then can be clearer, wherein:
Fig. 1 represents known RC circuit with Schottky diode;
Fig. 2 is the sectional arrangement drawing of the pairing semiconductor device of Fig. 1 circuit;
Fig. 3 is this bright manufacturing flow chart;
Fig. 4 (a) expression is according to the preferred embodiment of protecting the RC circuit of electric capacity with the MIS overvoltage protector of the present invention;
Fig. 4 (b) is a side circuit of the circuit of application drawing 4 (a);
Fig. 5 is the transverse cross-sectional view of the pairing semiconductor device of circuit of Fig. 4 (b);
Fig. 6 is the longitudinal sectional drawing along the AA line of Fig. 5.
With reference to the accompanying drawings, preferred embodiment of the present invention will describe in detail below.
Fig. 4 (a) expression is wherein protected electric capacity 13 by MIS overvoltage protector 11 according to the preferred embodiment of RC circuit of the present invention, and this MIS overvoltage protector 11 is in parallel with electric capacity 13, connects with resistance 12 again.Fig. 4 (b) is a side circuit of the circuit of application drawing 4 (a), and this RC circuit comprises 8 branch circuits, can optionally select corresponding I/O end.
Fig. 5 is the transverse cross-sectional view of the pairing semiconductor device of circuit of Fig. 4 (b).Fig. 6 is the longitudinal sectional drawing along the AA line of Fig. 5.As shown in Figure 6, mainly comprise on the Semiconductor substrate 10: MIS overvoltage protector 51, resistance 52 and electric capacity 53 etc.Make process, material of this chip or the like below with reference to Fig. 3 explanation.
Adopt the material of N type silicon as substrate 10, on whole surface, be about the insulation film of 1～2 μ m with sputter, evaporation or the CVD mode layer thickness that is covered, this insulation film is mainly used in avoids resistance region and I/O electrode bonding pad and base material conducting.Then, via photoetching (photolithography) technology, the zone beyond etching resistance area and the I/O electrode bonding pad is to form the insulating barrier 110 of resistance area and I/O electrode bonding pad.
Then, on whole surface, be covered one deck by Ta by sputter or evaporation or CVD mode
2O
5Or SiO
2In the medium 120 that metal oxide constituted, thickness is about 300～2000A.Then, by photoetching and this dielectric layer 120 of etching, obtain being used to form the required zone of MIS overvoltage protector.
On whole surface, by the be covered separator 130 of MIS overvoltage protector of sputter, evaporation or CVD mode, this separator 130 is very thin, about 50～300A, and it can be by Ta
2O
5, ZnO or SiO
2Constitute Deng metal oxide.
Then, on whole surface, form the resistive layer 140 that one deck is made of TaN by sputter, evaporation or CVD mode, its thickness is about 500～2500A.Then, in order to stop the interaction between resistive layer 140 and the position upper strata metal conducting layer thereon, on resistive layer 140, be about the diffusion impervious layer (diffusionbarrier layer) 150 of 3000～5000A by sputter, evaporation or the CVD mode thickness that is covered, this barrier layer 150 can be made of Ti or W.
Further, on the whole surface and on this barrier layer 150, form a layer thickness by sputter, evaporation or CVD mode and be about layer metal conducting layer 160 on 1～2 μ m, this upper strata metal conducting layer 160 can be made of metals such as Al, Cu, Au or Ag.Then; by photoetching and selective etch upper strata metal conducting layer 160; form two electrodes of resistance, the metal level of MIS overvoltage protector, the electric pole plate and the I/O electrode bonding pad of electric capacity, and form required distribution between resistance, electric capacity and the MIS overvoltage protector.
Then, in the zone that is used to form resistance,, remove barrier layer 150 and upper strata metal conducting layer 160 on resistive layer 140, to form resistance by photoetching and selective etch.
At last, at the whole lower surface of silicon substrate 10, by sputter, evaporation or CVD mode, the thickness that formation one deck is made of metals such as Al, Au or Ag is about the metal level of 2000～5000A, as lower electrode layer 170.
In the above-described embodiments, the example that has a MIS overvoltage protector with each RC branch circuit explains.Yet the number of the number of RC branch circuit, MIS overvoltage protector is not limited to this, can optionally change the number of RC branch circuit; Or the scope of the electric capacity of optionally protecting, the number of increase MIS overvoltage protector in circuit in parallel.
The specific embodiment that is proposed in the detailed description of preferred embodiment is only in order to be easy to illustrate technology contents of the present invention, and be not with narrow sense of the present invention be limited to this embodiment, in the situation that does not exceed spirit of the present invention and claim scope, can make many variations and implement.
Claims (6)
1. RC integrated semiconductor circuit with MIS overvoltage protector comprises:
One resistance, its first end is connected in input;
One electric capacity, its first end are connected in second end of this resistance as output, its second end ground connection; And
One or more MIS formed overvoltage protector in parallel, this overvoltage protector is parallel to this electric capacity, is used to protect this electric capacity,
It is characterized in that:
Described circuit be on Semiconductor substrate respectively by:
One resistance region;
One capacitor regions comprises dielectric layer and upper/lower electrode zone;
One MIS structure comprises separator, semiconductor layer and metallic conduction zone, and overvoltage protection is provided;
One I/O electrode bonding pad; And
Distribution between this resistance region, this capacitor regions and this MIS structure constitutes.
2. a manufacturing has the method for the RC integrated semiconductor circuit of MIS overvoltage protector, may further comprise the steps:
Form a substrate;
Be covered an insulation film on the whole surface of this substrate, by photoetching and selective etch, form the corresponding resistance of an insulating barrier on this substrate surface and the zone of I/O electrode, in order to avoid this resistance and this I/O electrode join domain and above-mentioned substrate conducting;
Form a dielectric layer on whole surface and cover above-mentioned insulating barrier, in order to dielectric material as this electric capacity;
By photoetching and selective etch, form this MIS structure;
The thin separator of lining one is on the whole surface and be covered on the described dielectric layer, in order to the isolated film as this MIS structure;
Be covered a resistive layer on the whole surface and be covered on the described separator, in order to form this resistance;
Be covered a barrier layer on the whole surface and cover on the described resistive layer, in case resistive layer and other thin layers interact here;
Be covered first conductive layer on the whole surface and cover on the described barrier layer, and in this conductive layer, form two electrodes of this resistance, the metal level of this MIS structure, the battery lead plate and the I/O electrode bonding pad of this electric capacity by photoetching and selective etch, and form required distribution between this resistance, this electric capacity and this MIS structure;
By photoetching and selective etch,, remove the barrier layer and first conductive layer above described resistive layer, to form this resistance in the zone of desire formation resistance;
Form the whole lower surface of second conductive layer, as the lower electrode layer of this electric capacity at described substrate.
3. method as claimed in claim 2 wherein is to adopt one of sputter, evaporation or CVD method, forms described insulating barrier, dielectric layer, separator, resistive layer, barrier layer, first metal conducting layer and the second electrode lay in order.
4. method as claimed in claim 3, wherein the material that separator adopted in this MIS structure is Ta
2O
5, ZnO or SiO
2
5. method as claimed in claim 3, wherein said resistive layer is made of TaN.
6. method as claimed in claim 3, wherein said substrate are the N type silicon with high-dopant concentration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00118663 CN1330406A (en) | 2000-06-20 | 2000-06-20 | RC integrated semiconductor circut with MIS over-voltage protector and its preparing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00118663 CN1330406A (en) | 2000-06-20 | 2000-06-20 | RC integrated semiconductor circut with MIS over-voltage protector and its preparing process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1330406A true CN1330406A (en) | 2002-01-09 |
Family
ID=4587312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 00118663 Pending CN1330406A (en) | 2000-06-20 | 2000-06-20 | RC integrated semiconductor circut with MIS over-voltage protector and its preparing process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1330406A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442515C (en) * | 2002-01-31 | 2008-12-10 | Nxp股份有限公司 | Electronic device |
| CN102074553A (en) * | 2009-08-25 | 2011-05-25 | 英飞凌科技奥地利有限公司 | Semiconductor component with dielectric layer stack |
-
2000
- 2000-06-20 CN CN 00118663 patent/CN1330406A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442515C (en) * | 2002-01-31 | 2008-12-10 | Nxp股份有限公司 | Electronic device |
| CN102074553A (en) * | 2009-08-25 | 2011-05-25 | 英飞凌科技奥地利有限公司 | Semiconductor component with dielectric layer stack |
| US9786659B2 (en) | 2009-08-25 | 2017-10-10 | Infineon Technologies Austria Ag | Semiconductor component with dielectric layer stack and voltage divider |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3987847B2 (en) | Semiconductor device equipped with MIM structure resistor | |
| US9299655B2 (en) | Single-chip integrated circuit with capacitive isolation and method for making the same | |
| CN1280874C (en) | Self-aligned double-sided vertical MIMcap | |
| CN1194418C (en) | Integrated component comprising metal-insulator-metal capacitor | |
| US4914055A (en) | Semiconductor antifuse structure and method | |
| US5468984A (en) | ESD protection structure using LDMOS diodes with thick copper interconnect | |
| CN101414606B (en) | Stack capacitor in semiconductor device and method for fabricating the same | |
| KR100442407B1 (en) | Integrated circuit which uses an etch stop for producing staggered interconnect lines | |
| EP0790649A2 (en) | Integrated ciruit having integral decoupling capacitor | |
| KR101172783B1 (en) | Capacitance element and semiconductor device | |
| TWI334630B (en) | Semiconductor device and method for fabricating the same | |
| US20140159202A1 (en) | Method for forming a three-dimensional structure of metal-insulator-metal type | |
| CN1832139A (en) | Method of integrated circuit device and forming device using the same | |
| CN1289451A (en) | Improved high quality factor capacitor | |
| JP3677346B2 (en) | Semiconductor devices that can be controlled by field effects | |
| US10748847B2 (en) | Metallisation for semiconductor device | |
| CN1330406A (en) | RC integrated semiconductor circut with MIS over-voltage protector and its preparing process | |
| EP0968529B1 (en) | Semiconductor device and method of manufacturing such a device | |
| CN1266286A (en) | RC semiconductor integrated circuit with MIS pulse protector | |
| US20220310910A1 (en) | Semiconductor memory device and fabrication method thereof | |
| US20220216350A1 (en) | 3d capacitors | |
| US20230125974A1 (en) | Semiconductor structure with selective bottom terminal contacting | |
| KR100442144B1 (en) | Method for manufacturing muti-layered capacitor of semiconductor device | |
| KR100613282B1 (en) | Capacitor in semiconductor device and manufacturing method thereof | |
| KR20020037340A (en) | Electronic device, and method of patterning a first layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |