CN100428473C - Semiconductor structure of high voltage side drive and its manufacturing method - Google Patents
Semiconductor structure of high voltage side drive and its manufacturing method Download PDFInfo
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- CN100428473C CN100428473C CNB2006101433871A CN200610143387A CN100428473C CN 100428473 C CN100428473 C CN 100428473C CN B2006101433871 A CNB2006101433871 A CN B2006101433871A CN 200610143387 A CN200610143387 A CN 200610143387A CN 100428473 C CN100428473 C CN 100428473C
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Abstract
The invention relates to a semi-conductor of high-voltage driver with ion doping connecting face, wherein said ion doping connecting face comprises one base board, the first well, the second well, the first heavy ion doping area, the second heavy doping area; the first and second wells have same ion doping type; the first well has the first heavy ion doping area connected ton the first high voltage; the first doping area has same ion doping type as first well; the second well has the second doping area connected to the second high voltage; the first and second doping areas have same ion doping type.
Description
Technical field
The relevant a kind of semiconductor of the present invention, and particularly relevant a kind of semiconductor structure of high-pressure side driver and manufacture method thereof.
Background technology
For high-pressure side driver with two hot ends, when two hot ends very near the time, the breakdown voltage that the p-n under potential end connects face may increase, and the leakage current that causes p-n to connect on the face zone between two hot ends increases.Basically reduce the notion of leakage current, increase by two distances between the hot end exactly.Yet this will cause chip size and manufacturing cost to increase.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of semiconductor structure of high-pressure side driver.Form the deep trap that two parts connect by the substrate regions under two hot ends, the impedance between the deep trap of two hot ends can be increased to reduce the leakage current between two hot ends.Therefore, the cost of chip size and high-pressure side driver is lowered.
According to purpose of the present invention, a kind of semiconductor structure of high-pressure side driver that comprises the ion doping ground face is proposed.The ion doping ground face comprises a substrate, one first deep trap and one second deep trap, one first heavy ion doped regions and one second heavy ion doped regions.First deep trap and second deep trap are formed in the substrate, and two deep traps connect and first deep trap and second deep trap have identical ion doping kenel in the surface part of closing on the ion doping ground face each other.In first deep trap, form in order to connecting first high-tension first heavy ion doped regions, and first heavy ion doped regions has the ion doping kenel identical with first deep trap.In second deep trap, form in order to connecting second high-tension second heavy ion doped regions, and second heavy ion doped regions has the ion doping kenel identical with first deep trap.
According to purpose of the present invention, a kind of manufacture method of semiconductor structure of high-pressure side driver is proposed.This method comprises formation one substrate; Form one first deep trap and one second deep trap in substrate, wherein first deep trap and second deep trap have the same ion dopant profile and connect in the surface part of closing on the ion doping ground face each other; And, respectively at forming one in first deep trap and second deep trap in order to connect first high-tension first heavy ion doped regions and in order to connect second high-tension second heavy ion doped regions, wherein first heavy ion doped regions and second heavy ion doped regions have the ion doping kenel identical with first deep trap.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is elaborated as follows:
Description of drawings
Figure 1A illustrates the part sectioned view according to the semiconductor structure of high-pressure side driver in the power supply supply IC of a preferred embodiment of the present invention;
Figure 1B is illustrated in the depletion region that ion doping ground face place that tradition has the high-pressure side driver of two hot ends produces;
Fig. 1 C is illustrated in the depletion region that the ion doping ground face place of the high-pressure side driver with two hot ends of the preferred embodiment according to the present invention produces;
Fig. 2 illustrates the manufacture method flow chart of the semiconductor structure of high-pressure side driver of Figure 1A;
Fig. 3 illustrates the schematic diagram of the ion doping operation of the ion doping deep trap that connects with the part with the photomask formation Figure 1A that separates pattern; And
Fig. 4 illustrates the simulate electric field curve chart of the semiconductor structure of high-pressure side driver of the preferred embodiment according to the present invention.
Embodiment
Please refer to Figure 1A, it illustrates the part sectioned view according to the semiconductor structure of high-pressure side driver in the power supply supply IC of a preferred embodiment of the present invention.Semiconductor structure of high-pressure side driver comprises ion doping ground face 100, oxide layer 110, first dielectric layer 120 and conduction capacitance structure 130.Ion doping ground face 100 comprises substrate 102, first deep trap 104, second deep trap 106, first heavy ion doped regions 105 and second heavy ion doped regions 107.First deep trap 104 and second deep trap 106 are formed in the substrate 102 and in the part connection each other of the surface of contiguous ion doping ground face 100, wherein first deep trap 104 and second deep trap 106 have identical ion doping kenel.
Be formed in first deep trap 104 in order to first heavy ion doped regions 105 that connects the first high voltage V1 (for example 500V), wherein first heavy ion doped regions 105 has the ion doping kenel identical with first deep trap 104.Be formed in second deep trap 106 in order to second heavy ion doped regions 107 that connects the second high voltage V2 (for example 530V), wherein second heavy ion doped regions 107 has the ion doping kenel identical with first deep trap 104.
For example, ion doping ground face 100 is that p-n connects face, and substrate 102 is P type substrates, and first deep trap 104 and second deep trap 106 are the N moldeed depth traps that are formed in the P type substrate.First heavy ion doped regions 105 and the second ion doping zone 107 are n+ diffusion regions.
Ion doping ground face 100 also is included in the 3rd deep trap 108 in the substrate 102.The 3rd deep trap 108 has the ion doping kenel identical with first deep trap 104, and partly is connected each other with first deep trap 104 conduction capacitance structure 130 times.The 3rd deep trap 108 for example also is a N moldeed depth trap.In addition, first deep trap 104 comprises that one first trap 104a and the 3rd deep trap 108 comprise one second trap 108a, and wherein the first trap 104a and the second trap 108a have the ion doping kenel with 104 complementations of first deep trap.For example, the first trap 104a and the second trap 108a are P type trap (PW) or P type main body.The breakdown voltage of ion doping ground face 100 depend on the first trap 104a in first deep trap 104 and the second trap 108a shape and the relative position in the 3rd deep trap 108.
Preferably, the distance D 2 of 106 of first deep trap 104 and second deep traps is greater than 0 μ m and less than 20 μ m.The depth D of first deep trap 104, second deep trap 106 and the 3rd deep trap 108 is between the 10 μ m at 2 μ m.The doping content of first deep trap 104 and second deep trap 106 is to be positioned at 1.7E17cm
-3To 8.3E18cm
-3Between.The doping content of the first trap 104a and the second trap 108a is to be positioned at 3.3E17cm
-3To 1E19cm
-3Between.
In addition, oxide layer 110 is formed on the ion doping ground face 100, and a part is between double ion doping zone 105 and 107 and another is partly between first deep trap 104 and the 3rd deep trap 108.First dielectric layer 120 is formed on the oxide layer 110, and conduction capacitance structure 130 is formed on first dielectric layer 120 and connects the first high voltage V1.Conduction capacitance structure 130 comprises the first metal layer 132, second dielectric layer 134 and two second metal levels 136 and 138 that separate.The first metal layer 132 be formed on first dielectric layer 120 and be positioned at the first trap 104a and the second trap 108a on, and second dielectric layer 134 is formed on the first metal layer 132.Second metal level 136,138 that separates is formed on second dielectric layer 134 and is positioned on the first metal layer 132, and one second metal level 136 wherein connects the first high voltage V1 and another second metal level 138 connects a low-voltage, for example 0V.
The invention is not restricted to have two second metal levels 136,138 and conduction capacitance structure 130 and can have plural second metal level (plural electric capacity polyphone is just arranged), one second metal level wherein connects the first high voltage V1 and another second metal level connects low pressure 0V.
Figure 1B is illustrated in the depletion region that ion doping ground face place that tradition has the high-pressure side driver of two hot ends produces.Fig. 1 C is illustrated in the depletion region that the ion doping ground face place of the high-pressure side driver with two hot ends of the preferred embodiment according to the present invention produces.Shown in Figure 1B, in traditional high-pressure side driver, be formed at two N moldeed depth traps 146 and 148 respectively in order to the N+ zone 142 and 144 that connects two high voltage V and V '.Be formed at p-n and connect depletion region 150 in the face 140, the G1 zone between two N moldeed depth traps 146 and 148 has a noncoherent boundary, and a corresponding concave edge circle CB is in substrate.Because concave edge circle CB is positioned at the electric field distorting of the depletion region 150 under the G1 zone and causes that internal field strengthens.Charge carrier is to be accelerated with lattice collisions to produce more carrier up to depletion region 150 generation collapses, thereby lowers the leakage current that p-n connects the breakdown voltage of face 140 and increases by 142 and 144 in two N+ zone.
Yet shown in Fig. 1 C, in high-pressure side driver of the present invention, deep trap 104 and 106 is that 105 and 107 area part is connected to each other in double ion doping zone.Therefore, the depletion region 160 that produces at ion doping ground face 100 places, depletion region 150 dissmilarities with Figure 1B have the border in the part junction of deep trap 104 and 106, and have corresponding smooth boundary SB in the substrate 102.In this example, the electric field of depletion region 160 can not twist, so the breakdown voltage of ion doping ground face 100 can not lower, and the leakage current that produces between two hot ends (V1 and V2) can significantly lower.
Please refer to Fig. 2, it illustrates the manufacture method flow chart of the semiconductor structure of high-pressure side driver of Figure 1A.At first, as step 200, form substrate 102, for example a P type substrate.Then, as step 210, the heat of carrying out 6～12 hours 1000 ℃ to 1200 ℃ of temperature ranges with the photomask 300 that separates pattern 302～304 as having of Fig. 3 drives in the operation, and first deep trap 104, second deep trap 106 and the 3rd deep trap 108 (for example N moldeed depth trap) that form part connection each other are in substrate 102. Separate pattern 302 and 304 apart from being directly proportional of 106 of d1 and first deep trap 104 and second deep traps apart from d2, and determine leakage current between first heavy ion doped regions 105 and second heavy ion doped regions 107 (not being illustrated among the figure).Preferably, 106 of first deep trap 104 and second deep traps apart from d2 greater than 0 μ m and less than 20 μ m, and the depth D of first deep trap 104, second deep trap 106 and the 3rd deep trap 108 is between the 10 μ m at 2 μ m.In addition, the doping content of first deep trap 104, second deep trap 106 and the 3rd deep trap 108 is to be positioned at 1.7E17cm
-3To 8.3E18cm
-3Between.
Then, as step 220, drive in the heat that 900 ℃ to 1100 ℃ of temperature ranges were carried out 2～6 hours and to form the first trap 104a and the second trap 108a (for example P type trap) in the operation respectively in first deep trap 104 and the 3rd deep trap 108.The doping content of the first trap 104a and the second trap 108a is preferably and is positioned at 3.3E17cm
-3To 1E19cm
-3Between.
Then, as step 230, formation in order to first heavy ion doped regions 105 (for example n+ zone) that connects the first high voltage V1 in first deep trap 104, and in order to second heavy ion doped regions 107 (for example n+ zone) that connects the second high voltage V2 in second deep trap 106.
As step 240, form oxide layer 110 on substrate 102 with deep trap 104,106 and 108, wherein oxide layer 110 somes are between double ion doping zone 105 and 107, and another partly is positioned on deep trap 104 and 108.As step 250, form first dielectric layer 120 on oxide layer 110.At last, as step 260, by forming the first metal layer 132 in reaching on the first trap 104a and the second trap 108a on first dielectric layer 120, forming second dielectric layer 134 on the first metal layer 132, and form two second metal levels 136 and 138 that separate on second dielectric layer 134, to form conduction capacitance structure 130 on first dielectric layer 120 and be positioned on first deep trap 104 and second deep trap 108.Wherein second metal level 136 and 138 connects the first high voltage V1 and low pressure 0V respectively.
Please refer to Fig. 4, it illustrates the simulate electric field curve chart of the semiconductor structure of high-pressure side driver of the preferred embodiment according to the present invention.Can know that from Fig. 4 the electric field E that finds out in the ion doping ground face 100 is very even, displaying has the ion doping ground face 100 of the ion doping deep trap (not illustrating among the figure) that part separates by use, and the high-pressure side driver with two hot ends still can be reached good effect.
Semiconductor structure of high-pressure side driver that the above embodiment of the present invention disclosed and manufacture method thereof, by forming the deep trap that part connects in order to the substrate regions between the double ion doping zone that connects two high voltages, the impedance of these deep traps is increased between two hot ends, can not reduce the breakdown voltage of high crimping face to reduce the leakage current between two hot ends.Therefore, the cost of chip size and high-pressure side driver is lowered.
In sum, though the present invention with preferred embodiment announcement as above, yet it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when doing various change that is equal to and retouching.Therefore, protection scope of the present invention is when looking accompanying being as the criterion that the application's claim scope defined.
Claims (26)
1. semiconductor structure of high-pressure side driver comprises:
One ion doping ground face comprises:
One substrate;
One first deep trap and one second deep trap are formed in this substrate, wherein this first deep trap and this second deep trap in the surface of closing on the ion doping ground face each other part connect and have an identical ion doping kenel;
One first heavy ion doped regions is formed in this first deep trap to be connected to one first high voltage, and wherein this first heavy ion doped regions has the ion doping kenel identical with this first deep trap; And
One second heavy ion doped regions is formed in this second deep trap to be connected to one second high voltage, and wherein this second heavy ion doped regions has the ion doping kenel identical with this first deep trap.
2. semiconductor structure as claimed in claim 1 is characterized in that the distance between this first deep trap and this second deep trap is greater than 0 μ m and less than 20 μ m.
3. semiconductor structure as claimed in claim 1 is characterized in that also comprising:
One oxide layer is formed on this ion doping ground face; And
One conduction capacitance structure is formed on this oxide layer and is connected to this first high voltage.
4. semiconductor structure as claimed in claim 3 is characterized in that this ion doping ground face comprises that also one has with the 3rd deep trap of this first deep trap same ion dopant profile and with this first deep trap under this conduction capacitance structure and partly is connected.
5. semiconductor structure as claimed in claim 4, it is characterized in that this ion doping ground face also comprise one first trap in this first deep trap and one second trap in the 3rd deep trap, and this first trap and this second trap have the ion doping kenel with this first deep trap complementation.
6. semiconductor structure as claimed in claim 5, the breakdown voltage that it is characterized in that this ion doping ground face are to be decided by that this first trap reaches shape and the relative position of this second trap in the 3rd deep trap in this first deep trap.
7. semiconductor structure as claimed in claim 5 is characterized in that the doping content of this first trap and this second trap is to be positioned at 3.3E17cm
-3To 1E19cm
-3Between.
8. semiconductor structure as claimed in claim 4, the degree of depth that it is characterized in that this first deep trap, this second deep trap and the 3rd deep trap are between the 10 μ m at 2 μ m.
9. semiconductor structure as claimed in claim 3 is characterized in that also comprising that one first dielectric layer is formed between this conduction capacitance structure and this oxide layer.
10. semiconductor structure as claimed in claim 9 is characterized in that this conduction capacitance structure comprises:
One the first metal layer is formed on this first dielectric layer;
One second dielectric layer is formed on this first metal layer;
Second metal level of a plurality of separation is formed on this second dielectric layer, wherein these second metal levels one of them be connected to this first high voltage, and another of these second metal levels is to be connected to a low-voltage.
11. semiconductor structure as claimed in claim 1 is characterized in that this substrate is a P type substrate, and this first deep trap and this second deep trap are the N moldeed depth traps that is formed in this P type substrate.
12. semiconductor structure as claimed in claim 1 is characterized in that the doping content of this first deep trap and this second deep trap is to be positioned at 1.7E17cm
-3To 8.3E18cm
-3Between.
13. semiconductor structure as claimed in claim 1 is characterized in that this first high voltage and this second high-tension voltage difference are about 30V.
14. the manufacture method of a semiconductor structure of high-pressure side driver comprises:
Form a substrate;
Form one first deep trap and one second deep trap in this substrate, wherein this first deep trap and this second deep trap have identical ion doping kenel and interconnect in the surface part of closing on the ion doping ground face each other; And
Respectively at forming one in this first deep trap and this second deep trap in order to connect one first high-tension first heavy ion doped regions and in order to connect one second high-tension second heavy ion doped regions, wherein this first heavy ion doped regions and this second heavy ion doped regions have the ion doping kenel identical with this first deep trap.
15. method as claimed in claim 14 is characterized in that the distance between this first deep trap and this second deep trap is greater than 0 μ m and less than 20 μ m.
16. method as claimed in claim 14, it is characterized in that forming this first deep trap and the step of this second deep trap in this substrate also is included in the substrate and forms one and have identical ion doping kenel, and the 3rd deep trap that partly is connected with this first deep trap, and form this in order to be connected to this first high-tension first heavy ion doped regions and this is in order to be connected to the step of this second high-tension second heavy ion doped regions, comprise also that respectively at forming one first trap and one second trap in this first deep trap and the 3rd deep trap wherein this first trap and this second trap have the ion doping kenel with this first deep trap complementation.
17. method as claimed in claim 16 is characterized in that also comprising:
Form an oxide layer on this substrate with this first trap and this second trap;
Form a conduction capacitance structure on this oxide layer, and be positioned on this first deep trap and the 3rd deep trap.
18. method as claimed in claim 17 is characterized in that also comprising forming one first dielectric layer on this oxide layer, the step that wherein forms this conduction capacitance structure comprises:
Form a first metal layer on this first dielectric layer;
Form one second dielectric layer on this first metal layer; And
Form a plurality of second metal levels on this second dielectric layer, wherein one of these second metal levels be connected to this first high voltage and this second metal level another be connected to a low-voltage.
19. method as claimed in claim 16 is characterized in that being included in 900 ℃ to 1100 ℃ of temperature ranges respectively at the step that forms this first trap and this second trap in this first deep trap and the 3rd deep trap carries out forming this first trap and this second trap in 2～6 hours the heat driving operation.
20. method as claimed in claim 16 is characterized in that the doping content of this first trap and this second trap is to be positioned at 3.3E17cm
-3To 1E19cm
-3Between.
21. method as claimed in claim 14 is characterized in that this substrate is that a P type substrate and this first deep trap and this second deep trap are N moldeed depth traps.
22. method as claimed in claim 14 is characterized in that forming this first deep trap and the step of this second deep trap in this substrate and comprises that having two light shields that separate pattern with one forms this first deep trap and this second deep trap.
23. method as claimed in claim 22, it is characterized in that these distances of separating between patterns be with this first deep trap and this second deep trap between distance be directly proportional and determine leakage current between this first heavy ion doped regions and this second heavy ion doped regions.
24. method as claimed in claim 14 is characterized in that the doping content of this first deep trap and this second deep trap is to be positioned at 1.7E17cm
-3To 8.3E18cm
-3Between.
25. method as claimed in claim 14, the degree of depth that it is characterized in that this first deep trap and this second deep trap are between the 10 μ m at 2 μ m.
26. method as claimed in claim 14 is characterized in that forming this first deep trap and the step of this second deep trap in this substrate and is included in a heat that 1000 ℃ to 1200 ℃ of temperature ranges carried out 6～12 hours and drives and form this first deep trap and this second deep trap in the operation.
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| CNB2006101433871A CN100428473C (en) | 2006-11-02 | 2006-11-02 | Semiconductor structure of high voltage side drive and its manufacturing method |
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|---|---|---|---|
| CNB2006101433871A CN100428473C (en) | 2006-11-02 | 2006-11-02 | Semiconductor structure of high voltage side drive and its manufacturing method |
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| CN100428473C true CN100428473C (en) | 2008-10-22 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6262459B1 (en) * | 2000-01-18 | 2001-07-17 | United Microelectronics Corp. | High-voltage device and method for manufacturing high-voltage device |
| CN1366349A (en) * | 2001-01-16 | 2002-08-28 | 三洋电机株式会社 | Semiconductor apparatus and its making method |
| US20050048707A1 (en) * | 2003-09-01 | 2005-03-03 | Jung-Cheng Kao | Processing method for improving structure of a high voltage device |
| US20060141714A1 (en) * | 2004-12-29 | 2006-06-29 | Dongbuanam Semiconductor Inc. | Method for manufacturing a semiconductor device |
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2006
- 2006-11-02 CN CNB2006101433871A patent/CN100428473C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6262459B1 (en) * | 2000-01-18 | 2001-07-17 | United Microelectronics Corp. | High-voltage device and method for manufacturing high-voltage device |
| CN1366349A (en) * | 2001-01-16 | 2002-08-28 | 三洋电机株式会社 | Semiconductor apparatus and its making method |
| US20050048707A1 (en) * | 2003-09-01 | 2005-03-03 | Jung-Cheng Kao | Processing method for improving structure of a high voltage device |
| US20060141714A1 (en) * | 2004-12-29 | 2006-06-29 | Dongbuanam Semiconductor Inc. | Method for manufacturing a semiconductor device |
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| CN1967844A (en) | 2007-05-23 |
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