CN102903752B - High-voltage element and manufacturing method thereof - Google Patents
High-voltage element and manufacturing method thereof Download PDFInfo
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- CN102903752B CN102903752B CN201110219850.7A CN201110219850A CN102903752B CN 102903752 B CN102903752 B CN 102903752B CN 201110219850 A CN201110219850 A CN 201110219850A CN 102903752 B CN102903752 B CN 102903752B
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Abstract
The invention provides a high-voltage element and a manufacturing method thereof. The high-voltage element is formed in a first conducting substrate. The high-voltage element comprises a second conducting buried layer, a first conducting well region and a second conducting well region, wherein the second conducting buried layer is formed in the first conducting substrate; when viewed by a cutaway view, the first conducting well region is positioned between the upper surface of the substrate and the second conducting buried layer; the second conducting well region is in a different position from the first conducting well region in the horizontal direction and is adjacent to the first conducting well region; the second conducting well region comprises a well region lower surface; the well region lower surface is provided with a first part and a second part; the first part is positioned above the second conducting buried layer and electrically coupled with the second conducting buried layer; and the second part is not positioned above the second conducting buried layer and forms a PN junction with the first conducting substrate.
Description
Technical field
The present invention relates to a kind of high voltage device and manufacture method thereof, refer to a kind of high voltage device and the manufacture method thereof that strengthen crash guard voltage especially.
Background technology
Fig. 1 shows lateral double diffusion metal oxide semiconductor (lateral doublediffused metal oxide semiconductor, LDMOS) the element cutaway view of prior art.As shown in Figure 1, in P type substrate 11, there is multiple insulation layer 12, to define element region 100, insulation layer 12 is such as shallow trench isolation (shallow trench isolation, STI) structure or zone oxidation as shown in the figure (local oxidation of silicon, LOCOS) structure; P type substrate 11 also comprises n type buried layer 14.LDMOS element is formed in element region 100, except n type buried layer 14, also comprises grid 13, drain electrode 15, source electrode 16, p type wells district 17 and N-type wellblock 18.Wherein, n type buried layer 14, drain electrode 15, source electrode 16 and N-type wellblock 18 are shielding by micro-shadow technology or with part or all of grid 13, insulation layer 12, to define each region, and respectively with ion embedding technology, by N-type impurity, with the form of speeding-up ion, formed in the region of implantation definition; P type wells district 17 is then by micro-shadow technology, defines this region, and with ion embedding technology, by p type impurity, with the form of speeding-up ion, formed in the region of implantation definition.Wherein, drain electrode 15 and source electrode 16 lay respectively at grid 13 down either side.And in LDMOS element, grid 13 some be positioned on field oxide region 22.
Fig. 2 shows double-diffused drain electrode metal-oxide semiconductor (MOS) (doublediffused drain metal oxide semiconductor, DDDMOS) the element cutaway view of prior art.With aforementioned LDMOS element unlike, the grid 13a of DDDMOS element is not that some is positioned on field oxide region 22, but is positioned at P type substrate 11 completely on the surface.
LDMOS and DDDMOS element is high voltage device, that is it is that design is for being applied to higher operating voltage, but when high voltage device needs with when being generally integrated on same substrate compared with the element of low operating voltage, for coordinating the element processing procedure compared with low operating voltage, need to make high voltage device and low voltage component with identical implanted ions parameter, the implanted ions parameter of high voltage device is restricted, thus reduces high voltage device crash guard voltage, limit the range of application of element.If do not sacrifice high voltage device crash guard voltage, then must increase fabrication steps, make high voltage device with the step of different ions implantation parameter separately, but will manufacturing cost be improved thus, just can reach desired crash guard voltage.
In view of this, the present invention, namely for above-mentioned the deficiencies in the prior art, proposes a kind of high voltage device and manufacture method thereof, when not increasing fabrication steps, improve the crash guard voltage of element operation, increase the range of application of element, and the processing procedure of low voltage component can be integrated in.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art and defect, propose a kind of high voltage device and manufacture method thereof.
For reaching above-mentioned purpose, the invention provides a kind of high voltage device, be formed in one first conduction type substrate, this first conduction type substrate has a upper surface of base plate, and this high voltage device comprises: one second conductive type buried layer, is formed in this first conduction type substrate; One first conductivity type wellblock, is formed at below this upper surface of base plate, and looks it by cutaway view, and this first conductivity type wellblock is between this upper surface of base plate and this second conductive type buried layer; And one second conductivity type wellblock, be formed at below this upper surface of base plate, and this second conductivity type wellblock and this first conductivity type wellblock are positioned at diverse location and adjacent in the horizontal direction, wherein, this the second conductivity type wellblock comprises a wellblock lower surface, and this wellblock lower surface has Part I and Part II, this Part I is positioned at above this second conductive type buried layer, and with this second conductive type buried layer electric property coupling, and this Part II is not above this second conductive type buried layer, and form PN junction with this first conduction type substrate.
With regard to another viewpoint, present invention provides a kind of high voltage device manufacture method, comprise: provide one first conduction type substrate, it has a upper surface of base plate; Form one second conductive type buried layer in this first conduction type substrate; Form one first conductivity type wellblock below this upper surface of base plate, and look it by cutaway view, this first conductivity type wellblock is between this upper surface of base plate and this second conductive type buried layer; And form one second conductivity type wellblock below this upper surface of base plate, and this second conductivity type wellblock and this first conductivity type wellblock are positioned at diverse location and adjacent in the horizontal direction, wherein, this the second conductivity type wellblock comprises a wellblock lower surface, and this wellblock lower surface has Part I and Part II, this Part I is positioned at above this second conductive type buried layer, and with this second conductive type buried layer electric property coupling, and this Part II is not above this second conductive type buried layer, and form PN junction with this first conduction type substrate.
Wherein in a kind of preferred embodiment, when this second conductivity type wellblock is suitable for this high voltage device to operate in a not on-state, roughly vague and general.
In another kind of preferred embodiment, this high voltage device more should comprise one second conductivity type drift region, be arranged in this second conductivity type wellblock, and be defined between this first conductivity type wellblock and drains in the horizontal direction, wherein when this high voltage device operates in a not on-state, this second conductivity type drift region is completely vague and general.
In another preferred embodiment, this high voltage device is a lateral double diffusion metal oxide semiconductor (lateral double diffused metal oxide semiconductor, LDMOS) element or double-diffused drain electrode metal-oxide semiconductor (MOS) (double diffused drain metal oxidesemiconductor, DDDMOS) element.
Again in another preferred embodiment, this first conduction type substrate should comprise the naked substrate of one first conductivity type, one first conductive type buried layer or one first conductivity type epitaxial layer; Wherein this first conductive type buried layer is implanted the first conductive-type impurity by ion implantation manufacture process step and formed, and this first conductivity type epitaxial layer formed by building crystal technique.
Illustrate in detail below by specific embodiment, when the effect being easier to understand object of the present invention, technology contents, feature and reach.
Accompanying drawing explanation
Fig. 1 shows the LDMOS element cutaway view of prior art;
Fig. 2 shows the DDDMOS element cutaway view of prior art;
Fig. 3 shows first embodiment of the present invention;
Fig. 4 shows second embodiment of the present invention;
Fig. 5 A and Fig. 5 B show comparing of prior art and the electric field simulation figure in first embodiment of the invention during LDMOS element not conducting (OFF) state;
Fig. 6 A-6D illustrates the manufacture method utilizing high voltage device of the present invention.
Symbol description in figure
11 substrates
12 insulation layers
13,13a grid
14 n type buried layers
14a photoresistance
15 drain electrodes
16 source electrodes
17 p type wells districts
18 N-type wellblocks
18a Part I
18b Part II
18c drift region
22 field oxide regions
100 element regions
Embodiment
Graphic in the present invention all belongs to signal, is mainly intended to represent the orbution up and down between fabrication steps and each layer, as shape, thickness and width then not according to scale.
Refer to Fig. 3, show first embodiment of the present invention, the present embodiment shows the cross-sectional schematic that the present invention is applied to LDMOS element.In substrate 11, form insulation layer 12 to define element region 100, wherein substrate 11 is such as P type but is not limited to P type (implementing can also be N-type in kenel at other); Insulation layer 12 is such as sti structure or zone oxidation LOCOS structure as shown in the figure, and, in substrate 11, comprise the conductivity type N-type not identical with substrate 11 (implementing can also be P type in kenel at other) buried regions 14.In addition, as shown in Figure 3, in substrate 11, P type (implementing in kenel at other can also be N-type) wellblock 17 and N-type (implementing can also be P type in kenel at other) wellblock 18 is formed.Wherein, p type wells district 17 is between substrate 11 upper surface and n type buried layer 14; N-type wellblock 18 is formed at below substrate 11 upper surface, and N-type wellblock and p type wells district are positioned at diverse location and adjacent in the horizontal direction.In substrate 11 surface, in element region 100, form field oxide region 22 with oxidation technology on the surface in this substrate 11, it is such as sti structure or zone oxidation LOCOS structure; Further, field oxide region 22 can utilize but be not limited to be formed with insulation layer 12 same process step.Then in element region 100, formed grid 13, drain electrode 15, with source electrode 16; Wherein, drain electrode 15 and source electrode 16 are such as N-type but are not limited to N-type (implementing can also be P type in kenel at other), lay respectively at grid 13 both sides in element region 100, and look it by vertical view (not shown), drain electrode 15 is separated by grid 13 and field oxide region 22 with source electrode 16.
Unlike the prior art, in the present embodiment, the lower surface of N-type wellblock 18 has Part I 18a and Part II 18b, illustrated by oval dotted line, wherein Part I 18a is positioned at above n type buried layer 14, and with n type buried layer electric property coupling, and Part II 18b is not above n type buried layer 14, and forms PN junction with P type substrate 11.
The advantage of this kind of arrangement comprises: in component specification, can improve the crash guard voltage of high voltage device, after its reason will be specified in; On processing procedure, can be, but not limited to the processing procedure and the light shield that utilize formation n type buried layer 14, when ion implantation manufacture process step, cover below Part II 18b with photoresistance or other shielding, stop that speeding-up ion is implanted below Part II 18b, and do not need new intensifying hood or fabrication steps in addition, therefore manufacturing cost can be reduced.
Fig. 4 shows second embodiment of the present invention.With first embodiment unlike, the present embodiment application the present invention in DDDMOS element but not LDMOS element.The grid 13a of DDDMOS element is not that some is positioned on field oxide region 22, but is positioned at P type substrate 11 completely on the surface.
Fig. 5 A and Fig. 5 B show comparing of prior art and the electric field simulation figure in first embodiment of the invention during LDMOS element not conducting (OFF) state.And and then illustrate how to utilize the present invention to strengthen the crash guard voltage of high voltage device.Refer to electric field simulation figure Fig. 5 A, show the electric field simulation figure during LDMOS element not on-state of prior art.For N-type LDMOS element, when operating in not on-state, grid 13 voltage is such as zero potential, and the PN junction between p type wells district 17 and n type buried layer 14, between p type wells district 17 and N-type wellblock 18 and between N-type wellblock 18 and P type substrate 11 is all reverse bias, thus there is the exhaustion region that width is different, as the electric field line in Fig. 5 A illustrated, and without the region of electric field line distribution, then represent it for zero potential.
Please continue to refer to Fig. 5 B, the electric field simulation figure in display first embodiment of the invention during LDMOS element not conducting (OFF) state.With the prior art shown in Fig. 5 A unlike, due to N-type wellblock 18 lower surface, there is Part I 18a and n type buried layer 14 couples, and Part II 18b and P type substrate 11 couple, between this Part II 18b and P type substrate 11, when the not conducting of LDMOS element, form the PN junction of reverse bias state.Can be known by inference by the distribution situation of electric field line in figure, N-type wellblock 18 is completely vague and general because of the reverse bias state of three PN junctions (the Part II 18b between p type wells district 17 and N-type wellblock 18 and in the side surface of N-type wellblock 18 and lower surface and between P type substrate 11) haply.
Comparison diagram 5A and 5B, can find out and utilize Fig. 5 B of the present invention compared to prior art Fig. 5 A, when high voltage device not conducting, its N-type wellblock 18 is completely vague and general haply.Therefore, its operating voltage that can bear is higher, and namely its crash guard voltage is higher.This illustrate the advantage that the present invention can improve the crash guard voltage of high voltage device.Wherein, in Fig. 5 B, rectangular broken line indicates N-type drift region 18c, it is arranged in N-type wellblock 18, the fabrication steps that can be, but not limited to by forming N-type wellblock 18 identical completes, and is defined between P wellblock 17 and drain electrode 15 in the horizontal direction, wherein when high voltage device operates in not on-state, N-type drift region 18c is completely vague and general, to strengthen the crash guard voltage of high voltage device.It should be noted that, N-type drift region 18c by high voltage device when conducting (ON) state electric current the region of process, therefore the and 15 high-tension operating voltages coupled that immediately drain, are the regions the most easily occurring to collapse.
Fig. 6 A-6D illustrates the manufacture method utilizing high voltage device of the present invention.As shown in Figure 6A, first provide such as but not limited to P type substrate 11 (implementing can also be N-type in kenel at other), it has upper surface of base plate; Then in P type substrate 11, utilize photoresistance 14a or other shielding to cover as shown in the figure, stop that the N-type impurity speeding-up ion of anticipating as the dotted line arrows is implanted in P type substrate 11, to form n type buried layer 14.
Next, as shown in Figure 6B, utilize photoresistance or other shielding definition p type wells district 17 and N-type wellblock 18 respectively, and respectively with the speeding-up ion of P type with N-type impurity, form p type wells district 17 and N-type wellblock 18.Wherein, look it by cutaway view Fig. 6 B, p type wells district 17 is between substrate 11 upper surface and n type buried layer 14, and N-type wellblock 18 is below substrate 11 upper surface, and N-type wellblock 18 and p type wells district 17 are positioned at diverse location and adjacent in the horizontal direction.
Following again, as shown in Figure 6 C, in substrate 11, form insulation layer 12 to define element region 100, and such as but not limited to utilizing same fabrication steps, form field oxide region 22.Wherein, N wellblock 18 comprises wellblock lower surface, and this wellblock lower surface has Part I 18a and Part II 18b, Part I 18a is positioned at above n type buried layer 14, and with n type buried layer 14 electric property coupling, and Part II 18b is not above n type buried layer 14, and forms PN junction with P type substrate 11.
Finally refer to Fig. 6 D, in element region 100, formed grid 13, drain electrode 15, with source electrode 16; Wherein, drain electrode 15 and source electrode 16 are such as N-type but are not limited to N-type (implementing can also be P type in kenel at other), lay respectively at grid 13 both sides in element region 100, and look it by vertical view (not shown), drain electrode 15 is separated by grid 13 and field oxide region 22 with source electrode 16.
It should be noted that, P type substrate 11 such as can be the naked substrate of P type, namely directly utilizes P type wafer as P type substrate 11; P type substrate 11 can also be p type buried layer, is formed such as but not limited to ion embedding technology; Or P type substrate 11 can also be P type epitaxial layer, formed by crystal technique of heap of stone.
Below for preferred embodiment, the present invention is described, just the above, be only and make those skilled in the art be easy to understand content of the present invention, be not used for limiting interest field of the present invention.Under same spirit of the present invention, those skilled in the art can think and various equivalence change.Such as, not affecting under the main characteristic of element, other fabrication steps or structure can be added, as deep-well district etc.; And for example, micro-shadow technology is not limited to masking techniques, also can comprise e-beam lithography; For another example, shown electric field simulation figure is the analog result of wherein a kind of embodiment, can not also need N-type wellblock is completely vague and general and only have partially depleted, as long as compared to prior art, having the crash guard voltage of enhancing.Scope of the present invention should contain above-mentioned and other all equivalence change.
Claims (10)
1. a high voltage device, be formed in one first conduction type substrate, this first conduction type substrate has a upper surface of base plate, it is characterized in that, this high voltage device comprises:
One second conductive type buried layer, is formed in this first conduction type substrate;
One first conductivity type wellblock, is formed at below this upper surface of base plate, and looks it by cutaway view, and this first conductivity type wellblock is between this upper surface of base plate and this second conductive type buried layer; And
One second conductivity type wellblock, be formed at below this upper surface of base plate, and this second conductivity type wellblock has side extends to below a grid of this high voltage device, opposite side extends beyond a drain electrode of this high voltage device, and this second conductivity type wellblock and this first conductivity type wellblock are positioned at diverse location and adjacent in the horizontal direction, wherein, this the second conductivity type wellblock comprises a wellblock lower surface, and this wellblock lower surface has Part I and Part II, this Part I is positioned at above this second conductive type buried layer, and with this second conductive type buried layer electric property coupling, and this Part II is not above this second conductive type buried layer, and form PN junction with this first conduction type substrate,
Wherein this second conductivity type wellblock has a region and is positioned at below this drain electrode, and when this high voltage device operates in a not on-state, this region is vague and general in fact.
2. high voltage device as claimed in claim 1, wherein, when this region of this second conductivity type wellblock is vague and general, it is darker than the upper surface of this second conductive type buried layer that this region has an exhaustion region.
3. high voltage device as claimed in claim 1, wherein, also comprise one second conductivity type drift region, be arranged in this second conductivity type wellblock, and be defined between this first conductivity type wellblock and drains in the horizontal direction, wherein when this high voltage device operates in a not on-state, this second conductivity type drift region is completely vague and general.
4. high voltage device as claimed in claim 1, wherein, this high voltage device is a lateral double diffusion metal oxide semiconductor element or double-diffused drain electrode metal oxide semiconductor device.
5. high voltage device as claimed in claim 1, wherein, this first conduction type substrate comprises the naked substrate of one first conductivity type, one first conductive type buried layer or one first conductivity type epitaxial layer; Wherein this first conductive type buried layer is implanted the first conductive-type impurity by ion implantation manufacture process step and formed, and this first conductivity type epitaxial layer formed by building crystal technique.
6. a high voltage device manufacture method, is characterized in that, comprises:
There is provided one first conduction type substrate, it has a upper surface of base plate;
Form one second conductive type buried layer in this first conduction type substrate;
Form one first conductivity type wellblock below this upper surface of base plate, and look it by cutaway view, this first conductivity type wellblock is between this upper surface of base plate and this second conductive type buried layer; And
Form one second conductivity type wellblock below this upper surface of base plate, and this second conductivity type wellblock has side extends to below a grid of this high voltage device, opposite side extends beyond a drain electrode of this high voltage device, and this second conductivity type wellblock and this first conductivity type wellblock are positioned at diverse location and adjacent in the horizontal direction, wherein, this the second conductivity type wellblock comprises a wellblock lower surface, and this wellblock lower surface has Part I and Part II, this Part I is positioned at above this second conductive type buried layer, and with this second conductive type buried layer electric property coupling, and this Part II is not above this second conductive type buried layer, and form PN junction with this first conduction type substrate,
Wherein this second conductivity type wellblock has a region and is positioned at below this drain electrode, and when this high voltage device operates in a not on-state, this region is vague and general in fact.
7. high voltage device manufacture method as claimed in claim 6, wherein, when this region of this second conductivity type wellblock is vague and general, it is darker than the upper surface of this second conductive type buried layer that this region has an exhaustion region.
8. high voltage device manufacture method as claimed in claim 6, wherein, also comprise formation one second conductivity type drift region in this second conductivity type wellblock, and be defined between this first conductivity type wellblock and drains in the horizontal direction, wherein when this high voltage device operates in a not on-state, this second conductivity type drift region is completely vague and general.
9. high voltage device manufacture method as claimed in claim 6, wherein, this high voltage device is a lateral double diffusion metal oxide semiconductor element or double-diffused drain electrode metal oxide semiconductor device.
10. high voltage device manufacture method as claimed in claim 6, wherein, this first conduction type substrate comprises the naked substrate of one first conductivity type, one first conductive type buried layer or one first conductivity type epitaxial layer; Wherein this first conductive type buried layer is implanted the first conductive-type impurity by ion implantation manufacture process step and formed, and this first conductivity type epitaxial layer formed by building crystal technique.
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| TWI613712B (en) * | 2016-12-23 | 2018-02-01 | 新唐科技股份有限公司 | Semiconductor device and method of fabricating the same |
| CN109473427B (en) * | 2017-09-08 | 2020-06-30 | 立锜科技股份有限公司 | High voltage device and method for manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6879003B1 (en) * | 2004-06-18 | 2005-04-12 | United Microelectronics Corp. | Electrostatic discharge (ESD) protection MOS device and ESD circuitry thereof |
| TW201003912A (en) * | 2008-07-09 | 2010-01-16 | Taiwan Semiconductor Mfg | Semiconductor structure |
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| US6593621B2 (en) * | 2001-08-23 | 2003-07-15 | Micrel, Inc. | LDMOS field effect transistor with improved ruggedness in narrow curved areas |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6879003B1 (en) * | 2004-06-18 | 2005-04-12 | United Microelectronics Corp. | Electrostatic discharge (ESD) protection MOS device and ESD circuitry thereof |
| TW201003912A (en) * | 2008-07-09 | 2010-01-16 | Taiwan Semiconductor Mfg | Semiconductor structure |
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