CN100499167C - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN100499167C CN100499167C CNB2007100862978A CN200710086297A CN100499167C CN 100499167 C CN100499167 C CN 100499167C CN B2007100862978 A CNB2007100862978 A CN B2007100862978A CN 200710086297 A CN200710086297 A CN 200710086297A CN 100499167 C CN100499167 C CN 100499167C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000009413 insulation Methods 0.000 claims abstract description 27
- 239000012535 impurity Substances 0.000 claims description 44
- XEBWQGVWTUSTLN-UHFFFAOYSA-M phenylmercury acetate Chemical compound CC(=O)O[Hg]C1=CC=CC=C1 XEBWQGVWTUSTLN-UHFFFAOYSA-M 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 36
- 150000004706 metal oxides Chemical class 0.000 description 36
- 230000015572 biosynthetic process Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 101150064138 MAP1 gene Proteins 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
A semiconductor structure includes a first high-voltage well (HVW) region of a first conductivity type overlying a substrate, a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region, and a third HVW region of the second conductivity type underlying the second HVW region. A region underlying the first HVW region is substantially free from the third HVW region, wherein the third HVW region has a bottom lower than a bottom of the first HVW region. The semiconductor structure further includes an insulation region in a portion and extending from a top surface of the first HVW region into the first HVW region, a gate dielectric extending from over the first HVW region to over the second HVW region wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
Description
Technical field
The present invention relates to semiconductor element, particularly (metal oxidesemiconductor, MOS) element relate more specifically to the structure and the manufacture method of high pressure (high voltage) metal oxide semiconductor device to metal-oxide semiconductor (MOS).
Background technology
High-voltage metal oxide semiconductor element is widely used in many electronic installations, for example: input/output circuitry, CPU (central process unit, CPU) power supply supply, power-supply management system and AC/DC converter or the like.
High-voltage metal oxide semiconductor element has many different types.The high-voltage metal oxide semiconductor element of symmetry has symmetrical structure in source terminal and drain electrode end, and high pressure can be applicable to source terminal and drain electrode end.Asymmetric high-voltage metal oxide semiconductor element has asymmetric structure in source terminal and drain electrode end.For example, have only one of source terminal and drain electrode end person, tradition is a drain electrode end, is designed to bear high pressure.
Fig. 1 shows traditional asymmetric high-pressure N-type metal oxide semiconductor element 2, and it comprises gate oxide 10, be positioned at gate electrode 12 on the gate oxide 10, be positioned at the drain region 4 on the high-pressure N-shaped well region HVNW1 and be positioned at source area 6 on the high-voltage P-type well region HVPW1.Shallow trench isolation is from (shallow trench isolation, STI) district 8 separates drain region 4 and gate electrode 12, is high-tension situation so that be applied in drain electrode to grid voltage.
High-pressure N-type metal oxide semiconductor element 2 is formed at the anti-break-through of high pressure (anti-punch-through, APT) top in district 14.The anti-reach through region 14 of high pressure is the anti-reach through region of P type high pressure, and be called as high-pressure N-shaped anti-reach through region (HVNAPT), wherein the character N of HVNAPT is illustrated in the operating period of high-pressure N-type metal oxide semiconductor element 2, forms N type zones of inversions (inversion region) at high-pressure N-shaped anti-reach through region 14.When high-voltage applications during in drain region 4, high pressure also is used on the high-pressure N-shaped well region HVNW1, and wherein voltage can be up to 20 volts.Suppose that high-pressure N-shaped anti-reach through region 14 does not have the words that form, it is the top that high-pressure N-shaped well region HVNW1 and high-voltage P-type well region HVPW1 directly are formed at P type substrate (substrate) 16, when high-voltage applications during, will cause the interface between high-pressure N-shaped well region HVNW1 and P type substrate 16 to produce the zones of inversions (not shown) in drain region 4.At high-pressure N-shaped well region HVNW1 end, zones of inversions belongs to the P type; And at P type substrate 16 ends, zones of inversions belongs to the N type.Because P type substrate 16 is light dope traditionally, the zones of inversions in the P type substrate 16 is extended toward big relatively distance.Zones of inversions can be coupled to another zones of inversions in the high-pressure N-shaped well region HVNW2, and it belongs to contiguous high-pressure N-type metal oxide semiconductor element 18, therefore causes break-through to take place.For solving the break-through problem, below the high-pressure N-type metal oxide semiconductor element, form high-pressure N-shaped anti-reach through region 14.Because high-pressure N-shaped anti-reach through region has mixed and had than the also high p type impurity of P type substrate 16 concentration, the thickness of each zones of inversions is relatively little, therefore can avoid the generation of break-through.
But, still there is shortcoming in the shown conventional high-tension N type metal oxide semiconductor element of Fig. 1.The electric current of Fig. 2 displayed map 1 mesohigh N type metal oxide semiconductor element is to the curve chart of voltage, and wherein X-axis represents to be applied in the voltage of drain region 4, and Y-axis is represented drive current (drive current).When being applied in high voltage Vg, for example during the Vg=20 volt, can notice that drive current is unsaturated along with the increase of drain voltage, or in other words, folder ends (pinch).Its expression will cause the output resistance problem of element reliability issues.Therefore, need a kind of solution for the problems referred to above.
Summary of the invention
For addressing the above problem, according to the embodiment of the invention, a kind of semiconductor structure comprises: substrate; First high-pressure trap area has first conduction type, is positioned at the top of above-mentioned substrate; Second high-pressure trap area has second conduction type with above-mentioned first conductivity type opposite, is positioned at the top of above-mentioned substrate and side direction adjacent to above-mentioned first high-pressure trap area; The 3rd high-pressure trap area, has above-mentioned second conduction type, be positioned at the below of above-mentioned second high-pressure trap area, the zone that wherein is positioned at above-mentioned first high-pressure trap area below is substantially away from above-mentioned the 3rd high-pressure trap area, and the bottom of above-mentioned the 3rd high-pressure trap area is lower than the bottom of above-mentioned first high-pressure trap area substantially; Insulation layer is positioned at the part of above-mentioned first high-pressure trap area, and extends in above-mentioned first high-pressure trap area from the top layer of above-mentioned first high-pressure trap area; Gate dielectric extends to the top of above-mentioned second high-pressure trap area from the top of above-mentioned first high-pressure trap area, wherein Yi Bufen above-mentioned gate dielectric is positioned at the top of above-mentioned insulation layer; And gate electrode, be positioned at the top of above-mentioned gate dielectric.
In the above-mentioned semiconductor structure, the edge of above-mentioned second high-pressure trap area substantially can align at the edge of above-mentioned the 3rd high-pressure trap area.
In the above-mentioned semiconductor structure, the bottom of above-mentioned the 3rd high-pressure trap area can be lower than the bottom of above-mentioned first high-pressure trap area, and approximately differ more than the 10nm, and above-mentioned the 3rd high-pressure trap area partially overlaps above-mentioned first high-pressure trap area, and the width of overlapping region approximately is less than 1 μ m.
In the above-mentioned semiconductor structure, the impurity concentration of above-mentioned the 3rd high-pressure trap area can be same as the impurity concentration of above-mentioned second high-pressure trap area substantially, and the impurity concentration of above-mentioned the 3rd high-pressure trap area is higher than the impurity concentration of above-mentioned substrate, and approximately differs more than 10 the first power.
Above-mentioned semiconductor structure also can comprise the 4th high-pressure trap area with above-mentioned first conduction form, be arranged in the opposite side of above-mentioned first high-pressure trap area with respect to above-mentioned second high-pressure trap area, wherein above-mentioned the 4th high-pressure trap area has identical thickness with above-mentioned first high-pressure trap area, and the zone that is positioned at above-mentioned the 4th high-pressure trap area below is substantially away from above-mentioned the 3rd high-pressure trap area, and above-mentioned gate dielectric extends across above-mentioned the 4th high-pressure trap area.
In the above-mentioned semiconductor structure, above-mentioned first high-pressure trap area and above-mentioned the 3rd high-pressure trap area can contact with above-mentioned substrate physical property.
In the above-mentioned semiconductor structure, also can comprise: the 4th high-pressure trap area, has the above-mentioned second conduction form, be positioned at the top of above-mentioned substrate and side direction adjacent to above-mentioned first high-pressure trap area, wherein above-mentioned the 4th high-pressure trap area is arranged in the opposite side of above-mentioned first high-pressure trap area with respect to above-mentioned second high-pressure trap area, and the zone that is positioned at above-mentioned the 4th high-pressure trap area top is substantially away from above-mentioned gate dielectric; And the 5th high-pressure trap area, has the above-mentioned second conduction form, be positioned at the below of above-mentioned the 4th high-pressure trap area, the zone that wherein is positioned at above-mentioned first high-pressure trap area below is substantially away from above-mentioned the 5th high-pressure trap area, and the bottom of above-mentioned the 5th high-pressure trap area is lower than the bottom of above-mentioned first high-pressure trap area substantially.
In the above-mentioned semiconductor structure, also can comprise: first source/drain region is positioned at above-mentioned first high-pressure trap area and adjacent to above-mentioned insulation layer; And second source/drain region, be positioned at above-mentioned second high-pressure trap area and adjacent to above-mentioned gate dielectric.
According to another embodiment of the present invention, a kind of semiconductor structure comprises: Semiconductor substrate; First high-pressure trap area has first conduction type, is located immediately at the top of above-mentioned Semiconductor substrate; Second high-pressure trap area, has second conduction type with above-mentioned first conductivity type opposite, be located immediately at the top of above-mentioned Semiconductor substrate and side direction adjacent to above-mentioned first high-pressure trap area, first thickness of wherein above-mentioned first high-pressure trap area is less than second thickness of above-mentioned second high-pressure trap area substantially; Insulation layer, separating at above-mentioned first high-pressure trap area and between above-mentioned first high-pressure trap area and above-mentioned second high-pressure trap area becomes the interface; Gate dielectric extends to the top of above-mentioned second high-pressure trap area from the top of above-mentioned insulation layer; And gate electrode, be positioned at the top of above-mentioned gate dielectric.
In the above-mentioned semiconductor structure, above-mentioned second thickness can be greater than above-mentioned first thickness, and approximately differ ten more than the percentage.
In the above-mentioned semiconductor structure, also can comprise the 3rd high-pressure trap area, has the second conduction form, in abutting connection with and be arranged in the opposite side of above-mentioned first high-pressure trap area with respect to above-mentioned second high-pressure trap area, wherein above-mentioned the 3rd high-pressure trap area has above-mentioned second thickness, and above-mentioned second high-pressure trap area and above-mentioned the 3rd high-pressure trap area are the part of the continuous high-pressure trap area that surrounds above-mentioned first high-pressure trap area.
According to further embodiment of this invention, a kind of semiconductor structure comprises: Semiconductor substrate; High-pressure N-shaped well region is positioned at the top of above-mentioned Semiconductor substrate; The high-voltage P-type well region is positioned at the top of above-mentioned Semiconductor substrate and surrounds above-mentioned high-pressure N-shaped well region; The anti-reach through region of P type high pressure, only between above-mentioned high-voltage P-type well region and above-mentioned Semiconductor substrate, the anti-reach through region of wherein above-mentioned P type high pressure is overlapped in above-mentioned high-voltage P-type well region substantially, and the bottom of the anti-reach through region of above-mentioned P type high pressure is lower than the bottom of above-mentioned high-pressure N-shaped well region substantially; Insulation layer is positioned at above-mentioned high-pressure N-shaped well region; Gate dielectric extends to the top of above-mentioned high-voltage P-type well region from the top of above-mentioned insulation layer; Gate electrode is positioned at the top of above-mentioned gate dielectric; First source/drain region is positioned at above-mentioned high-pressure N-shaped well region and adjacent to above-mentioned insulation layer; And second source/drain region, be positioned at above-mentioned high-voltage P-type well region and adjacent to above-mentioned gate dielectric.
In the above-mentioned semiconductor structure, the bottom of the above-mentioned high-voltage P-type well region bottom level with above-mentioned high-pressure N-shaped well region substantially is identical.
In the above-mentioned semiconductor structure, the bottom of the anti-reach through region of above-mentioned P type high pressure can be lower than the bottom of above-mentioned high-pressure N-shaped well region, and approximately differs more than the 10nm.
In the above-mentioned semiconductor structure, the p type impurity concentration of the anti-reach through region of above-mentioned P type high pressure can be between the p type impurity concentration of the p type impurity concentration of above-mentioned Semiconductor substrate and above-mentioned high-voltage P-type well region.
The present invention can improve the reliability of high-pressure N-type metal oxide semiconductor element, and obviously reduces the p type impurity atom that diffuses to high-pressure N-shaped well region.
Description of drawings
Fig. 1 shows conventional high-tension N type metal oxide semiconductor element;
The electric current of Fig. 2 displayed map 1 mesohigh N type metal oxide semiconductor element is to the curve chart of voltage;
Fig. 3 to Fig. 8 A shows the profile in the interstage of making the high-pressure N-type metal oxide semiconductor element;
The vertical view of Fig. 8 B displayed map 8A mesohigh N type metal oxide semiconductor element 68;
Fig. 9 shows that electric current according to the described high-pressure N-type metal oxide semiconductor element of the embodiment of the invention is to voltage curve;
Figure 10 shows the embodiment of the high-pressure N-type metal oxide semiconductor element of symmetry;
Figure 11 shows the embodiment of high voltage p-type metal oxide semiconductor (HVPMOS) element.
Wherein, description of reference numerals is as follows:
2,18,68～high-pressure N-type metal oxide semiconductor element
4～drain region
6～source area
8～shallow channel isolation area
10～gate oxide
12,62～gate electrode
14,24, HVNAPT～high-pressure N-shaped anti-reach through region
16～P type substrate
20～substrate
22,27,40,50～photoresistance
25～overlay region
26,30, HVPW, HVPW1, HVPW2～high-voltage P-type well region
28, HVNW, HVNW1, HVNW2～high-pressure N-shaped well region
32～mask layer
36～insulation layer
42～raceway groove
44,46, P
+～P
+The district
54,56, N
+～N
+The district
60～gate dielectric
64～grid gap wall
The anti-reach through region of HVPAPT～high-voltage P-type
Embodiment
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below:
Embodiment:
Fig. 3 to Fig. 8 A shows preferred embodiment of the present invention, and the variation of preferred embodiment will then be discussed.
With reference to figure 3, provide substrate 20 among Fig. 3.Substrate 20 preferably comprises for example semi-conducting material of silicon, yet substrate 20 also can use other semi-conducting materials.Preferably, substrate 20 carries out light dope with p type impurity, yet substrate 20 also can carry out light dope by N type impurity.
Fig. 3 also shows the high-voltage P- type well region 26,30 that is formed at high-pressure N-shaped anti-reach through region 24 tops.High-voltage P- type well region 26,30 also preferably mix p type impurity, for example boron and/or indium.Preferably, the concentration of the p type impurity of high-voltage P- type well region 26,30 can be higher than the concentration of the p type impurity of high-pressure N-shaped anti-reach through region 24, yet the concentration of the p type impurity of high-voltage P- type well region 26,30 also can equal or less than the concentration of the p type impurity of high-pressure N-shaped anti-reach through region 24.In one embodiment, the concentration of the p type impurity of high-voltage P- type well region 26,30 is approximately between 10
14Cm
-3With 10
17Cm
-3Between.Please note, though high-voltage P- type well region 26,30 is two different zones, high-voltage P- type well region 26,30 also can be the part that continuous high-voltage P-type well region surrounds high-pressure N-shaped well region 28, and as shown in Fig. 8 B, it is the vertical view of high-pressure N-type metal oxide semiconductor element.After forming high-pressure N-shaped anti-reach through region 24 and high-voltage P- type well region 26,30, remove photoresistance 22.Similarly, can determine that high-pressure N-shaped anti-reach through region 24 is parts of distinct area or closed loop (closed loop) according to the shape of high-voltage P-type well region 26,30.Those skilled in the art will recognize the selection that the order that forms high-pressure N-shaped anti-reach through region 24 and high-voltage P- type well region 26,30 just designs.
High-pressure N-shaped anti-reach through region 24 can use the mask identical with high-voltage P- type well region 26,30, as shown in Fig. 3.Yet high-pressure N-shaped anti-reach through region 24 also can use the mask different with high-voltage P-type well region 26,30.The mask that is formed high-pressure N-shaped anti-reach through region 24 by the logical operation (logic operation) of traditional masks is one of characteristic of the present invention, wherein can get rid of traditional high-pressure N-shaped anti-reach through region, thereby obtain new mask (with reference to figure 4) as high-pressure N-shaped anti-reach through region 24 via high-pressure N-shaped well region 28.In addition, via logical operation, but high-pressure N-shaped anti-reach through region 24 fractions are overlapped in high-pressure N-shaped well region 28, and wherein the width TE of overlay region 25 is approximately less than 1 μ rn.
Fig. 4 shows the formation of high-pressure N-shaped well region 28.Form photoresistance 27 with the previous formed high-voltage P- type well region 26,30 of shade, and inject N type impurity, for example: phosphorus, antimony and/or arsenic.In one embodiment, the impurity concentration of high-pressure N-shaped well region 28 is approximately between 10
14Cm
-3With 10
17Cm
-3Between.
Preferably, the thickness T 1 of high-pressure N-shaped well region 28 equals the thickness T 2 of high-voltage P- type well region 26,30 substantially.Therefore, dispose high-pressure N-shaped anti-reach through region 24 in the place that is lower than high-voltage P- type well region 26,30 and high-pressure N-shaped well region 28 bottoms.The preferred thickness T3 of high-pressure N-shaped anti-reach through region 24 partly determines according to the concentration of p type impurity in the high-pressure N-shaped anti-reach through region 24, and along with the increase of the concentration of p type impurity, thickness T 3 can and then reduce.Can recognize high-pressure N-shaped anti-reach through region 24 thickness T 3 can with the formation technology of integrated circuit and to be applied in the drain region voltage of each high-pressure N-type metal oxide semiconductor element proportional.In one embodiment, thickness T 3 is approximately between 10nm and 800nm.
Notice,, can in a processing step, high-pressure N-shaped anti-reach through region 24 and high-voltage P-type well region 26 be formed a zone by not only a kind of injection with different-energy.Therefore, to the bottom surface of high-pressure N-shaped anti-reach through region 24, the impurity that is injected has how identical impurity concentration from the surface of high-voltage P-type well region 26.In the same manner, high-pressure N-shaped anti-reach through region 24 and high-voltage P-type well region 30 also can form land (combined region).In this embodiment, the thickness of land preferably substantially greater than the thickness T 1 of high-pressure N-shaped well region 28, for example differs approximately between 10nm and 800nm.Perhaps, the thickness T 3 of high-pressure N-shaped anti-reach through region 24 is greater than 1/10th of the thickness T 2 of the thickness T 1 of high-pressure N-shaped well region 28 and high-voltage P- type well region 26,30.
In other embodiments, by forming high-pressure N-shaped well region 28, high-pressure N-shaped anti-reach through region 24 and high-voltage P- type well region 26,30, show that as Fig. 4 doping semiconductor layer has thickness T 1 at substrate 20 epitaxial growth doping semiconductor layers.Preferably the mix N type impurity of the concentration that is same as high-pressure N-shaped well region 28 in fact of doping semiconductor layer.Then, form the photoresistance that is same as photoresistance 22 among Fig. 3 in fact, and form high-pressure N-shaped anti-reach through region 24 and high-voltage P- type well region 26,30 via injecting p type impurity.The p type impurity that N type impurity is injected in the doping semiconductor layer offsets, and the net concentration of high-pressure N-shaped anti-reach through region 24 and high-voltage P- type well region 26,30 is same as aforementioned in fact.Therefore, the not injection region of doping semiconductor layer has formed high-pressure N-shaped well region 28.
Fig. 5 A, Fig. 5 B show the formation of insulation layer 36.In the preferred embodiment, shown in Fig. 5 A, in high-pressure N-shaped well region 28 and high-voltage P-type well region 26,30, form groove, and fill dielectric material to groove, for example: silicon dioxide (SiO2) or high-density plasma (high-density plasma, HDP) oxide, and carry out surface flattening that cmp will fill dielectric material to the surface of high-pressure N-shaped well region 28 and high-voltage P-type well region 26,30 to form insulation layer 36.Insulation layer 36 be the shallow trench isolation that produced from.In other embodiments, shown in Fig. 5 B, mask layer 32 is formed at (preferably being made up of silicon nitride) top of high-pressure N-shaped well region 28 and high-voltage P-type well region 26,30.Then, mask layer 32 is patterned to form raceway groove.Then, carry out oxidation processes, in raceway groove, form insulation layer 36 (being also referred to as field oxide (field oxide)) then.In general, for 0.25 μ m and be lower than the technology of 0.25 μ m, place (field region) preferably is shallow channel isolation area.With regard to the technology of large-size, the place preferably is a field oxide.
With reference to figure 6, placement and patterning photoresistance 40 are to form raceway groove 42.Carry out the injection of P type alloy to form P at high-voltage P- type well region 26,30 respectively
+ District 44,46.Preferably, P
+District 44,46 comprises boron and/or other P type alloys, and to be approximately higher than 10 greatly
20Cm
-3Concentration mix deeply.P
+District 44,46 is as the contact of picking up (pick-up) district.Then, remove photoresistance 40.
Fig. 7 shows the structure of gate dielectric 60, gate electrode 62 and grid gap wall 64.As is known to the person skilled in the art, gate dielectric 60 preferably comprises silica, yet also can use other dielectric material, for example: silicon nitride, carborundum, silicon oxynitride, its combination and multilayer dielectric material.Gate electrode 62 preferably comprises doped polycrystalline silicon, perhaps can use metal, metal nitride, metal silicide and other electric conducting materials.Preferably, cover (blanket) mode via blanket and form dielectric material, and get rid of part not and form grid gap wall 64 from horizontal plane.The detailed formation step of gate dielectric 60, gate electrode 62 and grid gap wall 64 is well known to those skilled in the art, and therefore no longer repeats at this.Preferably, the side of gate electrode 62 is positioned at the top of high-pressure N-shaped well region 28 insulation layers 36.
With reference to figure 8A, patterning and formation photoresistance 50.Carry out the injection of N type impurity to form N at high-voltage P-type well region 26 and high-pressure N-shaped well region 28 respectively
+ District 54 and N
+District 56.Therefore form high-pressure N-type metal oxide semiconductor element 68.N type alloy can comprise phosphorus and/or arsenic.Preferably, N type alloy is to be approximately higher than 10 greatly
20Cm
-3Concentration mix deeply.In described embodiment, the dark doping is to represent that the concentration of impurity is greatly about 10
20Cm
-3More than.Yet those skilled in the art will understand and be doped to technical term deeply, and it depends on specific element pattern, technical merit, minimum feature size or the like.Therefore, this term that mixes deeply is according to technology evaluation, but not in order to limit described embodiment.Source area is by N in the high-pressure N-type metal oxide semiconductor element 68
+ District 54 forms, and the drain region is by N
+District 56 forms.After injecting, remove photoresistance 50.Because gate electrode 62 and N
+Separate in district 56, so can under high pressure use.
Perhaps, N
+District 54 and N
+District 56 can form before gate dielectric 60, gate electrode 62 and grid gap wall 64.Those skilled in the art will understand the processing step that has separately aspect formation.
Fig. 8 B shows the layout vertical view of high-pressure N-type metal oxide semiconductor element 68.In Fig. 8 B, comprise that the high-voltage P-type well region of high-voltage P- type well region 26,30 surrounds high-pressure N-shaped well region 28, wherein the high-voltage P-type well region occupies the Zone Full except high-pressure N-shaped well region 28.Part high-voltage P- type well region 26,30 can have the insulation layer 36 that is positioned at the top.So high-pressure N-shaped anti-reach through region 24 preferably is overlapped in high-voltage P- type well region 26,30, also surrounds high-pressure N-shaped well region 28.The zone that is fenced up by two dashed rectangle is P
+The district comprises P
+District 44,46.It should be noted that embodiments of the invention can use different layout type to inject, and layout shown in Fig. 8 B is an example.
Fig. 9 shows that electric current according to the described high-pressure N-type metal oxide semiconductor element of one embodiment of the invention is to voltage (Id-Vds) curve chart.It should be noted that when high pressure for example during 20 volts of grids that are applied in the high-pressure N-type metal oxide semiconductor element, when drain electrode when the voltage (being Vds) of source electrode is near 12 volts, electric current I d is pressed from both sides the curve of voltage Vds to be ended.Its demonstration can improve the reliability according to the formed high-pressure N-type metal oxide semiconductor element of the embodiment of the invention.
When high-pressure N-shaped anti-reach through region is formed at the below of high-pressure N-shaped well region 28, the p type impurity atom of high-pressure N-shaped anti-reach through region will diffuse in the high-pressure N-shaped well region 28 and offset N type impurity in the high-pressure N-shaped well region 28.It will cause the increase of high-pressure N-shaped well region 28 internal resistance values and the minimizing of element drain current.One of feature of the present invention is the high-pressure N-shaped anti-reach through region that is positioned at high-pressure N-shaped well region 28 belows and has p type impurity by getting rid of can obviously reduce the p type impurity atom that diffuses to high-pressure N-shaped well region 28.
Previous described embodiment has asymmetric structure, and wherein source area and drain region are positioned at dissimilar high-pressure trap areas.Figure 10 shows the embodiment of the high-pressure N-type metal oxide semiconductor element with symmetrical structure, and wherein the high-pressure N-type metal oxide semiconductor element comprises two high-pressure N-shaped well region HVNW and a high-voltage P-type well region HVPW.Similar in appearance to Fig. 8 A illustrated embodiment, high-pressure N-shaped anti-reach through region HVNAPT is formed at the below of high-voltage P-type well region HVPW, and the below of high-pressure N-shaped well region HVNW does not have high-pressure N-shaped anti-reach through region HVNAPT to exist substantially.
Though, preferred embodiment shows the formation of high-pressure N-type metal oxide semiconductor element, those skilled in the art will recognize in order to forming the formation step separately of high voltage p-type metal oxide semiconductor (HVPMOS) element, with and be opposite with the conduction type of high-pressure N-shaped well region 28, high-voltage P- type well region 26,30 and (with reference to figure 8A) such as source area 54 and drain regions 56.Figure 11 shows an embodiment.Those skilled in the art can recognize that also high-voltage metal oxide semiconductor element has many different layouts.In any case spirit of the present invention still can be employed.Similarly, anti-phase by making among Figure 10 the conduction type of doped region, can form the high voltage p-type metal oxide semiconductor (HVPMOS) element of symmetry.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limiting scope of the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; can change and revise, so protection scope of the present invention should be as the criterion with claims.
Claims (15)
1. semiconductor structure comprises:
Substrate;
First high-pressure trap area has first conduction type, is positioned at the top of above-mentioned substrate;
Second high-pressure trap area has second conduction type with above-mentioned first conductivity type opposite, is positioned at the top of above-mentioned substrate and side direction adjacent to above-mentioned first high-pressure trap area;
The 3rd high-pressure trap area, has above-mentioned first conduction type, be positioned at the below of above-mentioned second high-pressure trap area, the zone that wherein is positioned at above-mentioned first high-pressure trap area below is away from above-mentioned the 3rd high-pressure trap area, and the bottom of above-mentioned the 3rd high-pressure trap area is lower than the bottom of above-mentioned first high-pressure trap area;
Insulation layer is positioned at the part of above-mentioned first high-pressure trap area, and extends in above-mentioned first high-pressure trap area from the top layer of above-mentioned first high-pressure trap area;
Gate dielectric extends to the top of above-mentioned second high-pressure trap area from the top of above-mentioned first high-pressure trap area, wherein Yi Bufen above-mentioned gate dielectric is positioned at the top of above-mentioned insulation layer; And
Gate electrode is positioned at the top of above-mentioned gate dielectric.
2. semiconductor structure as claimed in claim 1, the edge of above-mentioned second high-pressure trap area of the justified margin of wherein above-mentioned the 3rd high-pressure trap area.
3. semiconductor structure as claimed in claim 1, the bottom of wherein above-mentioned the 3rd high-pressure trap area is lower than the bottom of above-mentioned first high-pressure trap area, and differ more than the 10nm, and above-mentioned the 3rd high-pressure trap area partially overlaps above-mentioned first high-pressure trap area, and the width of overlapping region is less than 1 μ m.
4. semiconductor structure as claimed in claim 1, the impurity concentration of wherein above-mentioned the 3rd high-pressure trap area is same as the impurity concentration of above-mentioned second high-pressure trap area, and the impurity concentration of above-mentioned the 3rd high-pressure trap area is higher than the impurity concentration of above-mentioned substrate, and differs more than 10 the first power.
5. semiconductor structure as claimed in claim 1, also comprise the 4th high-pressure trap area with above-mentioned first conduction type, be arranged in the opposite side of above-mentioned first high-pressure trap area with respect to above-mentioned second high-pressure trap area, wherein above-mentioned the 4th high-pressure trap area has identical thickness with above-mentioned first high-pressure trap area, and the zone that is positioned at above-mentioned the 4th high-pressure trap area below is away from above-mentioned the 3rd high-pressure trap area, and above-mentioned gate dielectric extends across above-mentioned the 4th high-pressure trap area.
6. semiconductor structure as claimed in claim 1, wherein above-mentioned first high-pressure trap area and above-mentioned the 3rd high-pressure trap area are located immediately on the above-mentioned substrate.
7. semiconductor structure as claimed in claim 1 also comprises:
The 4th high-pressure trap area, has above-mentioned second conduction type, be positioned at the top of above-mentioned substrate and side direction adjacent to above-mentioned first high-pressure trap area, wherein above-mentioned the 4th high-pressure trap area is arranged in the opposite side of above-mentioned first high-pressure trap area with respect to above-mentioned second high-pressure trap area, and the zone that is positioned at above-mentioned the 4th high-pressure trap area top is away from above-mentioned gate dielectric; And
The 5th high-pressure trap area, has above-mentioned second conduction type, be positioned at the below of above-mentioned the 4th high-pressure trap area, the zone that wherein is positioned at above-mentioned first high-pressure trap area below is away from above-mentioned the 5th high-pressure trap area, and the bottom of above-mentioned the 5th high-pressure trap area is lower than the bottom of above-mentioned first high-pressure trap area.
8. semiconductor structure as claimed in claim 1 also comprises:
First source/drain region is positioned at above-mentioned first high-pressure trap area and adjacent to above-mentioned insulation layer; And
Second source/drain region is positioned at above-mentioned second high-pressure trap area and adjacent to above-mentioned gate dielectric.
9. semiconductor structure comprises:
Semiconductor substrate;
First high-pressure trap area has first conduction type, is located immediately at the top of above-mentioned Semiconductor substrate;
Second high-pressure trap area has second conduction type with above-mentioned first conductivity type opposite, is located immediately at the top of above-mentioned Semiconductor substrate and side direction adjacent to above-mentioned first high-pressure trap area;
The 3rd high-pressure trap area has above-mentioned first conduction type, is located immediately at the top of above-mentioned Semiconductor substrate and side direction adjacent to above-mentioned second high-pressure trap area, and wherein above-mentioned second high-pressure trap area is between above-mentioned first high-pressure trap area and above-mentioned the 3rd high-pressure trap area;
The 4th high-pressure trap area, has above-mentioned first conduction type, be positioned at the below of above-mentioned second high-pressure trap area, the zone that wherein is positioned at above-mentioned first high-pressure trap area and above-mentioned the 3rd high-pressure trap area below is away from above-mentioned the 4th high-pressure trap area, and the bottom of above-mentioned the 4th high-pressure trap area is lower than the bottom of above-mentioned first high-pressure trap area and above-mentioned the 3rd high-pressure trap area;
First insulation layer is at above-mentioned first high-pressure trap area and away from the interface between above-mentioned first high-pressure trap area and above-mentioned second high-pressure trap area;
Second insulation layer is at above-mentioned the 3rd high-pressure trap area and away from the interface between above-mentioned the 3rd high-pressure trap area and above-mentioned second high-pressure trap area;
Gate dielectric extends to the top of above-mentioned second insulation layer from the top of above-mentioned first insulation layer; And
Gate electrode is positioned at the top of above-mentioned gate dielectric.
10. semiconductor structure as claimed in claim 9, the edge of above-mentioned second high-pressure trap area of the justified margin of wherein above-mentioned the 4th high-pressure trap area.
11. semiconductor structure as claimed in claim 9, the bottom of wherein above-mentioned the 4th high-pressure trap area is lower than the bottom of above-mentioned first high-pressure trap area and above-mentioned the 3rd high-pressure trap area, and differ more than the 10nm, and above-mentioned first high-pressure trap area has identical thickness with above-mentioned the 3rd high-pressure trap area.
12. a semiconductor structure comprises:
Semiconductor substrate;
High-pressure N-shaped well region is positioned at the top of above-mentioned Semiconductor substrate;
The high-voltage P-type well region is positioned at the top of above-mentioned Semiconductor substrate and surrounds above-mentioned high-pressure N-shaped well region;
The anti-reach through region of N type high pressure, only between above-mentioned high-voltage P-type well region and above-mentioned Semiconductor substrate, the anti-reach through region of wherein above-mentioned N type high pressure is overlapped in above-mentioned high-voltage P-type well region, and the bottom of the anti-reach through region of above-mentioned N type high pressure is lower than the bottom of above-mentioned high-pressure N-shaped well region;
Insulation layer is positioned at above-mentioned high-pressure N-shaped well region;
Gate dielectric extends to the top of above-mentioned high-voltage P-type well region from the top of above-mentioned insulation layer;
Gate electrode is positioned at the top of above-mentioned gate dielectric;
First source/drain region is positioned at above-mentioned high-pressure N-shaped well region and adjacent to above-mentioned insulation layer; And
Second source/drain region is positioned at above-mentioned high-voltage P-type well region and adjacent to above-mentioned gate dielectric.
13. semiconductor structure as claimed in claim 12, the bottom of wherein above-mentioned high-voltage P-type well region is identical with the bottom level of above-mentioned high-pressure N-shaped well region.
14. semiconductor structure as claimed in claim 12, the bottom of the anti-reach through region of wherein above-mentioned N type high pressure is lower than the bottom of above-mentioned high-pressure N-shaped well region, and differs more than the 10nm.
15. semiconductor structure as claimed in claim 12, the p type impurity concentration of the anti-reach through region of wherein above-mentioned N type high pressure is between the p type impurity concentration of the p type impurity concentration of above-mentioned Semiconductor substrate and above-mentioned high-voltage P-type well region.
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