CN100428452C - 封装结构 - Google Patents

封装结构 Download PDF

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CN100428452C
CN100428452C CNB2004101011048A CN200410101104A CN100428452C CN 100428452 C CN100428452 C CN 100428452C CN B2004101011048 A CNB2004101011048 A CN B2004101011048A CN 200410101104 A CN200410101104 A CN 200410101104A CN 100428452 C CN100428452 C CN 100428452C
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partly
encapsulating structure
protection
connection pad
described encapsulating
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CN1738033A (zh
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杨文焜
陈世立
孙文彬
林明辉
周昭男
林志伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Yupei Science & Technology Co Ltd
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Abstract

本发明涉及一种封装结构，其中包含一元件；一接垫与该元件连接；至少一内连接部份，该内连接部份包含一第一端与一第二端，其中该第一端与该接垫连接；一连接部分与该内连接部份的该第二端连接；及一保护部份覆盖该接垫与该内连接部份的该第一端，该保护部份避免温度变化产生张力集中而造成该内连接部份与该接垫间的连接破裂。

Description

封装结构
技术领域
本发明涉及一种封装结构，特别是使用一种具有保护部份的封装结构。
背景技术
高密度封装的急速成长为电子装配与制造带来极大的冲击。于先进制程中，球门阵列(Ball Grid Array)与芯片级封装(Chip Scale Package，CSP)居于领导的地位。目前许多主要制造大厂与电子公司皆加速致力于封装技术的研究与发展。
参照图1A，封装技术的一产品，以间距1.27mm(相邻两锡球113的中心间的距离)的球门阵列封装11说明之，其为接脚(输出/入)数目多于300的一种选择，取代了现存低接脚的导线架式引脚封装(Quad FlatPackage，QFP)。
于最近几年，芯片级封装于市场上快速成长，其主要优点在于尺寸的缩小。参照图1B，以一芯片级封装13说明之，其比球门阵列封装11的尺寸更小，具有小于间距1.27mm的无导脚或有导脚的架构。芯片级封装13具有更轻巧的尺寸，一般用于内存的接脚(输出/入)数目小于100，亦可用于较高的接脚(输出/入)数目(小于300)。相较于诸如薄型小尺寸封装(Thin Small Outline Package，TSOP)的传统表面接脚结构，芯片级封装13亦提供较佳的电性与热效能、制造效率高且容易控管。然而，对于高信赖度应用的崭新封装领域而言，仍有若干因素需考量(主要是检验与信赖度)。
参照图1C，芯片级封装主要由元件131、黏着树脂135与锡球139所组成。锡球139通过若干内连接部分137与接垫141连接至元件131。一隔离层143与黏着树脂135隔离元件131及内连接部分137。另一隔离层145覆盖内连接部分137以保护内连接部分137避免破裂。整个封装结构亦可通过黏着层1331固定于一基板133上。
芯片级封装对于减少底座区域但有锡球连接，特别是介于内连接部分137及接垫141之间的锡球连接的信赖度问题需考量的情形是有效的。芯片级封装不易吸收由温度变化与导脚变形产生的冲击两者所产生的张力。因此，对于芯片级封装，张力集中于内连接部分137及接垫141之间的连接使得连接破裂且接着降低信赖度。因此需要发展避免信赖度降低的封装结构。
发明内容
本发明的目的之一在于避免锡球连接破裂。
本发明的另一目的在于提供一种封装结构，其吸收由温度变化所产生的张力。
本发明的再一目的在于提供一种封装结构，其吸收由导脚变形产生的冲击两者所产生的张力。
本发明的又一目的在于提供一种封装结构，其用以增加操作封装时的信赖度。
为达上述目的，本发明提供一种封装结构，其中包含一元件；一接垫与该元件连接；至少一内连接部份，该内连接部份包含一第一端与一第二端，其中该第一端与该接垫连接；一连接部分与该内连接部份的该第二端连接；及一保护部份覆盖该接垫与该内连接部份的该第一端，该保护部份避免温度变化产生张力集中而造成该内连接部份与该接垫间的连接破裂。
附图说明
图1A为一现有球门阵列封装的示意图。
图1B为一现有芯片级封装的示意图。
图1C为一现有芯片级封装的剖面示意图；
图2为本发明的一第一实施例的封装结构的剖面示意图；
图3为本发明的一第二实施例的封装结构的剖面示意图；
图4为本发明的一第三实施例的封装结构的剖面示意图；
图5为本发明的一第四实施例的封装结构的剖面示意图。
图中符号说明
11球门阵列封装
113锡球
13芯片级封装
131元件
133基板
135黏着树脂
137内连接部分
139锡球
141接垫
143隔离层
145隔离层
1331黏着层
21元件
23接垫
25内连接部份
251第一端
253第二端
291连接部分
293连接部分
27保护部份
29连接部分
31基板
33充填层
313黏着层
351绝缘层
353绝缘层
具体实施方式
本发明的实施例用示意图详细描述如下，在详述本发明的实施例时，表示封装结构的部份会放大显示并说明，然不应以此作为有限定的认知。此外，在实际的封装结构与方法中，应包含此结构中其它必要的部分。
参照图2所示，本发明的第一实施例所提供的一封装结构，包含一元件21、若干接垫23与元件21连接、若干内连接部份25与保护部份27。每一内连接部份25包含一第一端251与一第二端253，其中第一端251与接垫23连接。保护部份27覆盖接垫23与内连接部份25的第一端251。此外，若干连接部分29通过内连接部份25的第二端253连接。
保护部份27覆盖接垫23与内连接部份25的第一端251以避免介于接垫23与内连接部份25的第一端251之间的锡球连接破裂。当操作元件21，由于保护部份27的存在，使得接垫23与第一端251连接良好。封装结构中的保护部份27可吸收因温度变化或导脚变形冲击所产生的介于接垫23与内连接部份25之间的大部分张力。如此连接部分29可与元件21保持电性连接。因为保护部份27覆盖接垫23与内连接部份25的第一端251，故可增加操作元件21时的可靠度。
此外，于此所提供的封装结构更包含其它部分。一基板31通过一黏着层313黏着至元件21的背面。元件21的周围填充一充填层33以保护元件21，一绝缘层351则形成于元件21与内连接部份25之间。再者，绝缘层351亦形成于充填层33的表面上。
可以理解地，根据上述教示可形成许多变化的封装结构。举例来说，本发明的第一实施例所提供的元件21可以为一有源元件，例如一硅芯片或一半导体芯片。此外，本发明的其它实施例所提供的元件21可以为一无源元件，例如电阻、电容、电导、传感器或其它与接垫23及内连接部份25连接的结构。本发明的第一实施例中的保护部份27由塑料材料形成，例如聚丙烯或环氧塑封化合物等等。本发明的其它实施例中的保护部份27可由不同的材料形成，例如陶瓷或橡胶材料等等，视封装的设计而定。本发明的第一实施例中的接垫23由金属材料形成，例如铝材料。本发明的其它实施例中的接垫23可由不同的材料形成，例如铜或镍等等，视封装的设计而定。本发明的第一实施例中填充于元件21周围的充填层33由陶瓷材料形成。然而，充填层33亦由不同的材料形成，例如塑料、树脂、橡胶、合金等等。第一实施例中黏着于元件21上的基板31可由一刚性的材料形成，例如玻璃、陶瓷、合金、金属等等，或是挠性材料，例如聚丙烯、聚硫化亚氨、环氧物质等等，视封装的设计而定。本发明的第一实施例中的绝缘层351与353由硅橡胶(silicon rubber，SINR)的材料形成。然而，绝缘层351与353亦可由不同的材料形成，例如聚硫化亚氨、苯环丁烯(benzocyclobutene，BCB)、环氧锡球屏蔽、硅玻璃等等。
本发明的第一实施例中的连接部分29为一锡球。然而，一第二实施例中的一连接部分291为一针脚，如图3所示。第二实施例中的元件21并不黏着在基板31。第一实施例中的保护部份27较绝缘层353厚，但第二实施例中的保护部份27较绝缘层353薄。因此绝缘层353形成于保护部份27、内连接部份25与元件21上。无基板的封装结构的厚度较黏着在基板上的封装结构薄，故第二实施例的封装结构尺寸会缩小。
参照图4所示，一第三实施例中的一连接部分291亦为一针脚，另一连接部分293为一锡球接垫，并无任何绝缘层覆盖内连接部份25。再者，封装结构包含若干保护部份27。
参照图5所示，一第四实施例中的一连接部分291亦为一针脚，另一连接部分293为一锡球接垫，并无任何绝缘层覆盖内连接部份25。根据封装的设计，元件21并不黏着在基板且并无充填层填充于元件21周围。无黏着于基板且无充填层填充的的封装结构厚度会更缩小。
虽然本实施例的封装结构包含仅一元件21，但根据封装的不同设计，封装结构可包含更多的元件21。但假使其它部分，也就是接垫23、内连接部份25与保护部份27配置于上述本实施例的元件21的相同表面上，但根据封装的不同设计，其它部分亦可形成于不同的表面上。
本实施例提供一封装结构包含保护部份可保护介于接垫与内连接部份之间的锡球连接。由于保护部份、本实施例的封装结构提供操作元件时所需的信赖度。
以上所述的实施例仅为说明本发明的技术思想及特点，其目的在使本领域的技术人员能够了解本发明的内容并据以实施，当不能以之限定本发明的专利范围，即大凡依本发明所揭示的精神所作的均等变化或修饰，仍应涵盖在本发明的权利要求书内。

Claims (10)

1.一种封装结构，其特征在于，包含：
一元件；
一接垫与该元件连接；
至少一内连接部份，该内连接部份包含一第一端与一第二端，其中该第一端与该接垫连接；
一连接部分与该内连接部份的该第二端连接；及
一保护部份覆盖该接垫与该内连接部份的该第一端，该保护部份避免温度变化产生张力集中而造成该内连接部份与该接垫间的连接破裂。
2.如权利要求1所述的封装结构，其中，该元件为一有源元件。
3.如权利要求第1所述的封装结构，其中，该元件包含一无源元件。
4.如权利要求第1所述的封装结构，其中，该保护部份由塑料材料形成。
5.如权利要求第1所述的封装结构，其中，该保护部份由陶瓷材料形成。
6.如权利要求第1所述的封装结构，其中，该保护部份由橡胶材料形成。
7.如权利要求第1所述的封装结构，其中，更包含一基板黏着于该元件上。
8.如权利要求第1所述的封装结构，其中，更包含一绝缘层，该绝缘层位于该元件与该内连接部份之间并紧临该接垫。
9.如权利要求第8所述的封装结构，其中，该保护部份较该元件与该内连接部份上的该绝缘层厚。
10.如权利要求第8所述的封装结构，其中，该保护部份较该元件与该内连接部份上的该绝缘层薄。
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KR100905719B1 (ko) 2007-06-20 2009-07-01 삼성전자주식회사 열응력 흡수 부재를 구비한 반도체 패키지
US7691682B2 (en) * 2007-06-26 2010-04-06 Micron Technology, Inc. Build-up-package for integrated circuit devices, and methods of making same
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
US8435837B2 (en) 2009-12-15 2013-05-07 Silicon Storage Technology, Inc. Panel based lead frame packaging method and device
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465745B1 (en) * 2000-06-28 2002-10-15 Advanced Micro Devices, Inc. Micro-BGA beam lead connection
WO2003021664A1 (fr) * 2001-08-31 2003-03-13 Hitachi, Ltd. Dispositif semiconducteur, corps structurel et dispositif electronique

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2833996B2 (ja) * 1994-05-25 1998-12-09 日本電気株式会社 フレキシブルフィルム及びこれを有する半導体装置
JPH08167630A (ja) * 1994-12-15 1996-06-25 Hitachi Ltd チップ接続構造
JPH08236586A (ja) * 1994-12-29 1996-09-13 Nitto Denko Corp 半導体装置及びその製造方法
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6433427B1 (en) * 2001-01-16 2002-08-13 Industrial Technology Research Institute Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465745B1 (en) * 2000-06-28 2002-10-15 Advanced Micro Devices, Inc. Micro-BGA beam lead connection
WO2003021664A1 (fr) * 2001-08-31 2003-03-13 Hitachi, Ltd. Dispositif semiconducteur, corps structurel et dispositif electronique

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