CN100428448C - 电路装置及其制造方法 - Google Patents

电路装置及其制造方法 Download PDF

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Publication number
CN100428448C
CN100428448C CNB2005100821343A CN200510082134A CN100428448C CN 100428448 C CN100428448 C CN 100428448C CN B2005100821343 A CNB2005100821343 A CN B2005100821343A CN 200510082134 A CN200510082134 A CN 200510082134A CN 100428448 C CN100428448 C CN 100428448C
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China
Prior art keywords
insulating resin
resin film
matrix part
film
circuit arrangement
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Expired - Fee Related
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CNB2005100821343A
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English (en)
Chinese (zh)
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CN1725474A (zh
Inventor
臼井良辅
水原秀树
井上恭典
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of CN1725474A publication Critical patent/CN1725474A/zh
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Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/2413—Connecting within a semiconductor or solid-state body
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Laminated Bodies (AREA)
CNB2005100821343A 2004-06-29 2005-06-29 电路装置及其制造方法 Expired - Fee Related CN100428448C (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2004191881A JP2006013367A (ja) 2004-06-29 2004-06-29 回路装置およびその製造方法
JP191881/04 2004-06-29
JP191882/04 2004-06-29
JP191884/04 2004-06-29
JP191883/04 2004-06-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN2008102128216A Division CN101419949B (zh) 2004-06-29 2005-06-29 电路装置及其制造方法

Publications (2)

Publication Number Publication Date
CN1725474A CN1725474A (zh) 2006-01-25
CN100428448C true CN100428448C (zh) 2008-10-22

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CNB2005100821343A Expired - Fee Related CN100428448C (zh) 2004-06-29 2005-06-29 电路装置及其制造方法
CN2008102128216A Expired - Fee Related CN101419949B (zh) 2004-06-29 2005-06-29 电路装置及其制造方法

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CN (2) CN100428448C (ja)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4728980B2 (ja) * 2007-02-21 2011-07-20 古河電気工業株式会社 プリント配線板及びその製造方法
WO2009133969A2 (en) * 2008-04-30 2009-11-05 Panasonic Electric Works Co., Ltd. Method of producing circuit board by additive method, and circuit board and multilayer circuit board obtained by the method
US8240036B2 (en) 2008-04-30 2012-08-14 Panasonic Corporation Method of producing a circuit board
KR101195674B1 (ko) * 2009-01-29 2012-10-30 야마하 가부시키가이샤 열교환 유닛
EP2496061A4 (en) 2009-10-30 2014-01-08 Panasonic Corp PRINTED CIRCUIT BOARD AND SEMICONDUCTOR DEVICE COMPRISING A COMPONENT MOUNTED ON A PRINTED CIRCUIT BOARD
US9332642B2 (en) 2009-10-30 2016-05-03 Panasonic Corporation Circuit board
JP2012028744A (ja) * 2010-06-22 2012-02-09 Panasonic Corp 半導体装置用パッケージおよびその製造方法ならびに半導体装置
US9907181B2 (en) * 2013-07-30 2018-02-27 Harman Becker Automotive Systems Gmbh Electronic module

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1395460A (zh) * 2001-07-04 2003-02-05 日矿金属株式会社 叠层板用铜合金箔
JP2003053879A (ja) * 2001-06-04 2003-02-26 Nippon Zeon Co Ltd 回路基板及びその製造方法
CN1476632A (zh) * 2001-10-10 2004-02-18 德山株式会社 基板和制造该基板的方法
JP2004140268A (ja) * 2002-10-18 2004-05-13 Matsushita Electric Works Ltd 高周波用多層プリント配線板の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4830704A (en) * 1988-01-29 1989-05-16 Rockwell International Corporation Method of manufacture of a wiring board
JP4045781B2 (ja) * 2001-08-28 2008-02-13 松下電工株式会社 発光装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003053879A (ja) * 2001-06-04 2003-02-26 Nippon Zeon Co Ltd 回路基板及びその製造方法
CN1395460A (zh) * 2001-07-04 2003-02-05 日矿金属株式会社 叠层板用铜合金箔
CN1476632A (zh) * 2001-10-10 2004-02-18 德山株式会社 基板和制造该基板的方法
JP2004140268A (ja) * 2002-10-18 2004-05-13 Matsushita Electric Works Ltd 高周波用多層プリント配線板の製造方法

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Publication number Publication date
CN1725474A (zh) 2006-01-25
CN101419949B (zh) 2011-10-12
CN101419949A (zh) 2009-04-29
JP2006013367A (ja) 2006-01-12

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