CN100383797C - 集成电路版图的层次网表提取方法 - Google Patents
集成电路版图的层次网表提取方法 Download PDFInfo
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- CN100383797C CN100383797C CNB2005100538532A CN200510053853A CN100383797C CN 100383797 C CN100383797 C CN 100383797C CN B2005100538532 A CNB2005100538532 A CN B2005100538532A CN 200510053853 A CN200510053853 A CN 200510053853A CN 100383797 C CN100383797 C CN 100383797C
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CNB2005100538532A CN100383797C (zh) | 2005-03-14 | 2005-03-14 | 集成电路版图的层次网表提取方法 |
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CNB2005100538532A CN100383797C (zh) | 2005-03-14 | 2005-03-14 | 集成电路版图的层次网表提取方法 |
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CN1834967A CN1834967A (zh) | 2006-09-20 |
CN100383797C true CN100383797C (zh) | 2008-04-23 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102402630A (zh) * | 2010-09-10 | 2012-04-04 | 北京华大九天软件有限公司 | 一种层次版图验证中单元间图形连接关系的识别方法 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
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US7640520B2 (en) * | 2007-03-13 | 2009-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Design flow for shrinking circuits having non-shrinkable IP layout |
CN101464916B (zh) * | 2007-12-21 | 2010-09-08 | 北京华大九天软件有限公司 | 集成电路版图的器件属性计算方法 |
CN102314531B (zh) * | 2010-07-02 | 2013-04-17 | 北京华大九天软件有限公司 | 集成电路版图自动构造层次方法 |
US20130019219A1 (en) * | 2011-07-13 | 2013-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for hierarchy reconstruction from flattened graphic database system layout |
CN102323964B (zh) * | 2011-08-16 | 2014-06-25 | 北京芯愿景软件技术有限公司 | 一种数字电路网表数据的处理方法 |
CN104615795B (zh) * | 2013-11-05 | 2017-12-12 | 中国空间技术研究院 | 图纸内容提取验证方法 |
CN105224708B (zh) * | 2014-07-03 | 2019-01-18 | 台湾积体电路制造股份有限公司 | 集成电路中网路的确定方法和装置 |
US10031989B2 (en) * | 2014-11-18 | 2018-07-24 | Globalfoundries Inc. | Integrated circuit performance modeling using a connectivity-based condensed resistance model for a conductive structure in an integrated circuit |
CN106650140B (zh) * | 2016-12-29 | 2019-10-25 | 北京华大九天软件有限公司 | 一种基于全面板的电路自动展开方法 |
CN109858166A (zh) * | 2019-02-13 | 2019-06-07 | 北京芯愿景软件技术有限公司 | 一种动态复合图形 |
CN110619168B (zh) * | 2019-09-11 | 2023-08-11 | 上海高性能集成电路设计中心 | 一种基于网表的超大规模芯片信息分析方法 |
CN112199918B (zh) * | 2020-10-20 | 2021-09-21 | 芯和半导体科技(上海)有限公司 | 一种通用eda模型版图物理连接关系的重建方法 |
WO2022110114A1 (zh) * | 2020-11-30 | 2022-06-02 | 华为技术有限公司 | 电路版图的识别方法及识别设备 |
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US5956257A (en) * | 1993-03-31 | 1999-09-21 | Vlsi Technology, Inc. | Automated optimization of hierarchical netlists |
US6574779B2 (en) * | 2001-04-12 | 2003-06-03 | International Business Machines Corporation | Hierarchical layout method for integrated circuits |
US6651236B2 (en) * | 2000-09-13 | 2003-11-18 | Ricoh Company, Ltd. | Semiconductor integrated circuit device, and method of placement and routing for such device |
CN1523663A (zh) * | 2003-02-19 | 2004-08-25 | 上海芯华微电子有限公司 | 双极型集成电路设计中的版图/电路提取方法 |
US20040221255A1 (en) * | 2000-09-29 | 2004-11-04 | Numerical Technologies, Inc. | Dissection of edges with projection points in a fabrication layout for correcting proximity effects |
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2005
- 2005-03-14 CN CNB2005100538532A patent/CN100383797C/zh active Active
Patent Citations (5)
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US5956257A (en) * | 1993-03-31 | 1999-09-21 | Vlsi Technology, Inc. | Automated optimization of hierarchical netlists |
US6651236B2 (en) * | 2000-09-13 | 2003-11-18 | Ricoh Company, Ltd. | Semiconductor integrated circuit device, and method of placement and routing for such device |
US20040221255A1 (en) * | 2000-09-29 | 2004-11-04 | Numerical Technologies, Inc. | Dissection of edges with projection points in a fabrication layout for correcting proximity effects |
US6574779B2 (en) * | 2001-04-12 | 2003-06-03 | International Business Machines Corporation | Hierarchical layout method for integrated circuits |
CN1523663A (zh) * | 2003-02-19 | 2004-08-25 | 上海芯华微电子有限公司 | 双极型集成电路设计中的版图/电路提取方法 |
Non-Patent Citations (1)
Title |
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基于ILT的版图自动层次构造算法. 李宁,侯劲松.微电子学与计算机,第21卷第9期. 2004 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102402630A (zh) * | 2010-09-10 | 2012-04-04 | 北京华大九天软件有限公司 | 一种层次版图验证中单元间图形连接关系的识别方法 |
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