CN100377308C - Particle-removing process before semiconductor etching - Google Patents
Particle-removing process before semiconductor etching Download PDFInfo
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- CN100377308C CN100377308C CNB2005101262854A CN200510126285A CN100377308C CN 100377308 C CN100377308 C CN 100377308C CN B2005101262854 A CNB2005101262854 A CN B2005101262854A CN 200510126285 A CN200510126285 A CN 200510126285A CN 100377308 C CN100377308 C CN 100377308C
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Abstract
The present invention provides a particle-removing process before semiconductor etching, particularly a process for preprocessing a silicon chip. The process comprises two steps that the step one is particle activation and the step two is particle removal. The process of the present invention can make the cleaning treatment on the silicon chip before the etching process step to achieve the optimum efficiency of particle control.
Description
Technical field
The present invention relates to a kind of pre-treatment process of semiconductor etching process, specifically, relate to the preceding technology of removing particle of a kind of semiconductor etching.
Background technology
At present in semiconductor technology is made, the characteristic size of components and parts is more and more littler, so, also more and more higher to semi-conductive technological requirement accordingly, wherein, the control of the particle in the technical process (particle) is a very crucial factor of control period rate of finished products, is the very big challenge that the semiconductor technology manufacturing faces.
In polycrystalline silicon gate grid etching process, generally comprise following three steps: (1) BT (Breakthrough), it mainly acts on is the oxide layer of removing the nature on surface; (2) ME (Main etch), i.e. main etching, its effect is an etch polysilicon, forms lines; (3) OE (Over etch), i.e. over etching, its effect is that the surface after the etching is purged.These three steps are carried out continuously, and wherein that the pressure maximum is OE, but also only less than 100mT, process gas also is very pure, so the control of particle is to be determined by the situation before the technology to a great extent.
Prior art generally is before etching technics silicon chip to be carried out wet-cleaned.Its shortcoming can not be carried out clean to silicon chip exactly before next-door neighbour's processing step begins, so also just be difficult to guarantee the control effect of particle in the technical process.
Summary of the invention
(1) technical problem that will solve
Purpose of the present invention is exactly silicon chip to be carried out once promptly before next-door neighbour's processing step silicon chip being carried out clean at the processing of particle before these three processing steps, reaches the optimum efficiency of particle control.
(2) technical scheme
For achieving the above object, the present inventor provides the preceding technology of removing particle of a kind of semiconductor etching promptly silicon chip to be carried out pretreated technology, and this technology comprises following two steps:
(1) particle activates step.This process condition is: chamber pressure 5-20mT, and upper electrode power 50-800w, carrier gas is selected from N
2, Cl
2, SF
6, O
2In one or more, total gas flow rate 5-600sccm, wherein N
2Flow is 5-100sccm, Cl
2Flow is 5-100sccm, SF
6Flow is that 10-300sccm, O2 flow are 5-50sccm.
The preferred process conditions of this step are: chamber pressure 5-15mT, and upper electrode power 300-500w, carrier gas is N
2, Cl
2, SF
6, O
2Mist, total gas flow rate is 90-170sccm, wherein N
2Flow is 50-80sccm, Cl
2Flow is 10-30sccm, SF
6Flow is 20-40sccm, O
2Flow is 10-20sccm.
(2) particle removal step.This process condition is: chamber pressure 0.01-20mT, and upper electrode power 50-800w, carrier gas is selected from He, Ar, N
2In one or more, total gas flow rate 30-900sccm, wherein the He flow is that 10-300sccm, Ar flow are 10-300sccm, N
2Flow is 10-300sccm.
The preferred process conditions of this step are: chamber pressure 0.01-10mT, and upper electrode power 400-500w, carrier gas is N
2Mist or N with He
2With the mist of Ar, total gas flow rate is 40-80sccm, wherein N
2Flow is that 10-30sccm, He or Ar flow are 30-40sccm.
The main effect of step (1) is a jihuokeli, and the effect in second step is under the condition of low pressure plasma particle to be taken away rapidly.
Wherein step (1) time is 2-30s, and step (2) time is 5-30s.
After silicon chip carried out preliminary treatment, carry out etching again, i.e. BT, main carve and step is carved in the back, the technological parameter in these several steps is identical with the technological parameter of routine techniques.
(3) beneficial effect
By to observing without the silicon chip preliminary treatment with through silicon chip pretreated grid etch technology gained polysilicon chip, the particles contained number of the latter obviously reduces as can be seen.Be that technology of the present invention can be carried out clean to silicon chip before next-door neighbour's etching technics step, reach the optimum efficiency of particle control.
Description of drawings
Fig. 1 is without the particle detection of silicon chip preliminary treatment etching technics gained polysilicon chip figure as a result;
Fig. 2 is through the particle detection of silicon chip preliminary treatment etching technics gained polysilicon chip figure as a result.
The used instrument of particle detection is the Surfscan 6420 Unpatterned WaferInspection (no graph silicon chip surface particles detector) of KLA company, examination criteria is that size is less than 25 (200mm wafer etch) at the granule number of 0.2um-3um, circular portion is the concrete distribution situation of particle on wafer above among the figure, setting detected particle size is 0.2-3nm, and different colours is represented the particle of different size size.As can be seen, the situation of particle is better than the situation of particle among Fig. 1 among Fig. 2, and the particle that is embodied in 0.2-3nm among Fig. 2 is 8, and the particle of 0.2-3nm is 28 among Fig. 1.
Embodiment
Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiment only to be used to the present invention is described and be not used in and limit the scope of the invention.Following examples are carried out on 200mm silicon chip erosion machine, can reflect the 200nm process results, need to prove, technology has downward compatibility, in the time of can satisfying high-end 200nm technology, the 300nm technology of low side etc. can meet the demands fully, i.e. the present invention also is applicable to 300mm silicon chip erosion machine.
Embodiment 1
In carrying out the polysilicon chip etching technics, used equipment is the PM2 at northern microelectronics base equipment technical study center.The structure of used polysilicon chip is: silica 1 00 , polysilicon 3050 , silicon chip (substrate substrate).
Etching process mainly is divided into following a few step:
1. silicon chip is delivered to the electrostatic chuck surface in the chamber;
2. add electrostatic chuck voltage, silicon chip is fixed on the electrostatic chuck surface by electrostatic attraction;
3. logical process gas;
4. the pressure regulation of pendulum valve is to set point;
5. add upper/lower electrode, build-up of luminance;
6. etching technics begins, and etching technics mainly comprises following a few step:
1) BT (Break through), it is the removal of natural oxidizing layer, technological parameter is: the strong 7mT of chamber inner pressure, upper electrode power 300W, lower electrode power 40W, flow is that the CF4 of 50sccm is carrier gas, time is 5s, has one to run through etching stabilizing step (BT stable step) before this step, and main technologic parameters is 0 for upper/lower electrode power, time is 10s, and other parameters are the same with BT;
2) ME (main etch), i.e. main etching, its effect is an etch polysilicon, form lines, technological parameter is: the strong 10mT of chamber inner pressure, upper electrode power 350W, lower electrode power 40W, carrier gas comprises that flow is the C12 of 190sccmHBr, 5sccm, the HeO2 of 15sccm, etch period is end point determination control, before this step a main etching stabilizing step (ME stable step) is arranged, and main technologic parameters is 0 for upper/lower electrode power, time is 10s, and other parameters are the same with ME;
3) OE (Over etch), be over etching, its effect is that the surface after the etching is purged, and technological parameter is: the strong 60mT of chamber inner pressure, upper electrode power 350W, lower electrode power 40W, carrier gas comprises that flow is the HeO2 of 150sccmHBr, 15sccm, the He of 100sccm, etch period 40s, an over etching stabilizing step (OE stable step) was arranged before this step, main technologic parameters is 0 for upper/lower electrode power, and the time is 10s, and other parameters are the same with OE;
7. after etching technics is finished, carry out silicon chip unloading process, be about to the residual charge that electrostatic chuck (ESC) shows and eliminate, so that silicon chip can be stable and the electrostatic chuck surface isolation;
8. get sheet, etching finishes.
After carrying out above technology, examination criteria is that size is less than 25 (200mm wafer etch) at the granule number of 0.2um-3um, Surfscan 6420 Unpatterned WaferInspection by KLA company observe, as shown in Figure 1, distribution of particles situation on the silicon chip as can be seen, the latter half is a particle size distribution range among the figure, and the particle that is specially wherein greater than 0.2um-3um is 28.
Embodiment 2
According to embodiment 1 described method, difference is, before the step silicon chip is carried out pretreated technology at BT:
(1) chamber pressure 8mT, upper electrode power 400w, carrier gas is N
260sccm, Cl
210sccm, SF
620sccm, O
210sccm, total gas flow rate 100sccm, the time is 5s.
(2) chamber pressure 1mT, upper electrode power 400w, carrier gas is He30sccm, N
220sccm, the time is 10s.
After carrying out above technology, examination criteria is that size is less than 25 (200mm wafer etch) at the granule number of 0.2um-3um, Surfscan 6420 Unpatterned WaferInspection by KLA company observe, as shown in Figure 2, distribution of particles situation on the wafer as can be seen, the latter half is a particle size distribution range among the figure, and being specially and obtaining particle size is 8 at the particle of 0.2um-3um.
Embodiment 3
According to embodiment 1 described method, difference is, before the step silicon chip is carried out pretreated technology at BT:
(1) chamber pressure 20mT, upper electrode power 200w, carrier gas is N
2100sccm, SF
640sccm, the time is 25s.
(2) chamber pressure 0.1mT, upper electrode power 500w, carrier gas is He10sccm, Ar40sccm, N
210sccm, the time is 30s.
After carrying out above technology, examination criteria is that size is less than 25 (200mm wafer etch) at the granule number of 0.2um-3um, Surfscan 6420 Unpatterned WaferInspection by KLA company detect, and we obtain particle size is 10 at the particle of 0.2um-3um.
Embodiment 4
According to embodiment 1 described method, difference is, before the step silicon chip is carried out pretreated technology at BT:
(1) chamber pressure 5mT, upper electrode power 800w, carrier gas is N
260sccm, SF
6300sccm, the time is 30s.
(2) chamber pressure 0.01mT, upper electrode power 800w, carrier gas is Ar30sccm, N
220sccm, the time is 30s.
After carrying out above technology, examination criteria is that size is less than 25 (200mm wafer etch) at the granule number of 0.2um-3um, Surfscan 6420 Unpatterned WaferInspection by KLA company detect, and we obtain particle size is 5 at the particle of 0.2um-3um.
Embodiment 5
According to embodiment 1 described method, difference is, before the step silicon chip is carried out pretreated technology at BT:
(1) chamber pressure 10mT, upper electrode power 600w, carrier gas is Cl
230sccm, SF
640sccm, O
210sccm, total gas flow rate 80sccm.Time is 15s.
(2) chamber pressure 0.01mT, upper electrode power 300w, carrier gas is Ar40sccm, the time is 18s.
After carrying out above technology, examination criteria is that size is less than 25 (200mm wafer etch) at the granule number of 0.2um-3um, Surfscan 6420UnpatternedWafer Inspection by KLA company detects, and we obtain particle size is 7 at the particle of 0.2um-3um.
Claims (8)
1. silicon chip pretreating process before the semiconductor etching may further comprise the steps:
A, particle activate: chamber pressure 5-20mT, and upper electrode power 100-800w, carrier gas is selected from N
2, Cl
2, SF
6, 0
2In one or more, total gas flow rate 5-600sccm, this step time is 2-30s;
B, particle removal: chamber pressure 0.01-20mT, upper electrode power 50-800w, carrier gas is selected from He, Ar, N
2In one or more, total gas flow rate 30-900sccm, this step time is 5-30s.
2. technology as claimed in claim 1, the gas of carrier gas total flow that it is characterized in that step a is 80-120sccm.
3. technology as claimed in claim 1, the carrier gas that it is characterized in that step a is N
2, Cl
2, SF
6, O
2Mist, N wherein
2Flow is 5-100sccm, Cl
2Flow is 5-100sccm, SF
6Flow is 10-300sccm, O
2Flow is 5-50sccm.
4. technology as claimed in claim 1 is characterized in that the process conditions of step a are: chamber pressure 5-15mT, and upper electrode power 300-500w, carrier gas is N
2, Cl
2, SF
6, O
2Mist, N wherein
2Flow is 50-80sccm, Cl
2Flow is 10-30sccm, SF
6Flow is 20-40sccm, O
2Flow is 10-20sccm.
5. technology as claimed in claim 1, the gas of carrier gas total flow that it is characterized in that step b is 40-80sccm.
6. technology as claimed in claim 1 is characterized in that the process conditions of step b are: chamber pressure 0.01-10mT, and upper electrode power 400-500w, carrier gas is He, Ar, N
2In one or more, wherein the He flow is 10-300sccm, the Ar flow is 10-300sccm, N
2Flow is 10-300sccm.
7. technology as claimed in claim 6 is characterized in that the carrier gas of step b is: N
2With the mist of He, wherein N
2Flow is 10-30sccm, and the He flow is 30-40sccm.
8. technology as claimed in claim 6 is characterized in that the carrier gas of step b is: N
2With the mist of Ar, wherein N
2Flow is 10-30sccm, and the Ar flow is 30-40sccm.
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CN101450346B (en) * | 2007-12-05 | 2012-09-05 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Dry cleaning method during preparing semi-conductor |
CN112447496A (en) * | 2019-08-28 | 2021-03-05 | 东莞新科技术研究开发有限公司 | Semiconductor ion etching cleaning method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6242350B1 (en) * | 1999-03-18 | 2001-06-05 | Taiwan Semiconductor Manufacturing Company | Post gate etch cleaning process for self-aligned gate mosfets |
CN1468977A (en) * | 2002-07-19 | 2004-01-21 | 联华电子股份有限公司 | Residual polymer eliminating method |
CN1647257A (en) * | 2002-04-16 | 2005-07-27 | 东京电子株式会社 | Method for removing photoresist and etch residues |
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2005
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6242350B1 (en) * | 1999-03-18 | 2001-06-05 | Taiwan Semiconductor Manufacturing Company | Post gate etch cleaning process for self-aligned gate mosfets |
CN1647257A (en) * | 2002-04-16 | 2005-07-27 | 东京电子株式会社 | Method for removing photoresist and etch residues |
CN1468977A (en) * | 2002-07-19 | 2004-01-21 | 联华电子股份有限公司 | Residual polymer eliminating method |
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Address after: No. 8, Wenchang Avenue, Beijing economic and Technological Development Zone, 100176 Patentee after: Beijing North China microelectronics equipment Co Ltd Address before: 100016 Jiuxianqiao East Road, Chaoyang District, Chaoyang District, Beijing Patentee before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |