CN112233977A - Method for improving lattice damage - Google Patents
Method for improving lattice damage Download PDFInfo
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- CN112233977A CN112233977A CN202011104593.8A CN202011104593A CN112233977A CN 112233977 A CN112233977 A CN 112233977A CN 202011104593 A CN202011104593 A CN 202011104593A CN 112233977 A CN112233977 A CN 112233977A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
Abstract
The invention provides a method for improving crystal lattice damage, which comprises the following steps of placing a wafer on a chuck, wherein the wafer is subjected to a plasma etching process, the chuck comprises an electrode, and the wafer is in contact with the electrode of the chuck; performing first electrostatic discharge treatment on the wafer to discharge partial charges on the wafer; performing second electrostatic discharge treatment on the wafer, wherein the electrode provides a first reverse voltage for the wafer so as to discharge partial charges on the wafer; and performing third electrostatic discharge treatment on the wafer, wherein the electrode provides a second reverse voltage for the wafer so as to complete the charge discharge on the wafer. By optimizing the static electricity releasing treatment process, the damage to crystal lattices in the contact hole etching process caused by charge accumulation is reduced, and the imaging quality of products is improved.
Description
Technical Field
The invention relates to the technical field of image sensors, in particular to a method for improving lattice damage.
Background
Compared with Charge-coupled devices (CCD) and Charge Injection Devices (CID), CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely favored by the market due to their low power consumption, high integration and low cost, and have a promising application prospect.
The CMOS image sensor generally realizes image transmission by the principle of photoelectric conversion, and the thickness of the oxide layer in the source and drain regions and the ion implantation concentration of the CMOS image sensor have a great influence on the performance of the device. In the sidewall etching process (spacer lateral etch), the thickness of the oxide layer has a great influence on the device performance, and in the conventional process, Plasma Induced Damage (PID) to the silicon surface is avoided by increasing the thickness of the oxide layer to prevent the Plasma in the etching process from directly contacting the silicon surface. The industry finds that the reasons for PID are mainly: impurities (impurities) penetrate into the substrate (substrate) by ion implantation or diffusion effects, plasma etching induced lattice damage, contamination of the substrate by heavy metals sputtered from the vacuum chamber walls, and the like. The reason why leakage (leak) of a Floating Diffusion (FD) region is easily formed by lattice damage on the silicon (Si) surface is that due to insufficient protection of an oxide layer, charge accumulation (wafer charging) on the wafer surface is formed in the sidewall etching process, the charge accumulation region on the wafer surface is weaker in the contact (contact) etching process, and lattice damage is easily caused in the etching process.
For a conventional large-sized CMOS image sensor, such as a 153nm CIS device, before ILDD or N-type lightly doped drain (NLDD) ion implantation is performed, the thickness of the oxide layer in the current mature process is about 170 angstroms, however, the thicker thickness of the oxide layer may affect the image quality. Therefore, a method for improving the lattice damage of the source/drain region without increasing the thickness of the oxide layer is needed.
Disclosure of Invention
The invention aims to provide a method for improving lattice damage so as to solve the problem that imaging quality is influenced by the lattice damage of a weak area on a wafer.
In order to solve the above technical problems, the present invention provides a method for improving lattice damage, comprising:
placing a wafer on a chuck, the wafer having completed a plasma etch process, the chuck comprising an electrode;
performing first electrostatic discharge treatment on the wafer to discharge partial charges on the wafer;
performing second electrostatic discharge treatment on the wafer, wherein the electrode provides a first reverse voltage for the wafer so as to discharge partial charges on the wafer;
and performing third electrostatic discharge treatment on the wafer, wherein the electrode provides a second reverse voltage for the wafer so as to complete the charge discharge on the wafer.
Optionally, the power of the electrode in the first electrostatic discharge treatment, the second electrostatic discharge treatment, and the third electrostatic discharge treatment is sequentially increased.
Optionally, in the second electrostatic discharge treatment, the power of the electrode is 80-120 w; in the third electrostatic discharge treatment, the power of the electrode is 350-450W.
Optionally, the process time of the first static electricity discharge treatment and the second static electricity discharge treatment is 1 second to 10 seconds.
Optionally, the process time of the electrode subjected to the third electrostatic discharge treatment is 4 seconds to 40 seconds.
Optionally, during the first electrostatic discharge treatment, the second electrostatic discharge treatment, and the third electrostatic discharge treatment, argon gas is introduced into the front surface of the wafer.
Optionally, the pressure generated by the argon gas is 1torr to 10 torr.
Optionally, the flow rate of the argon gas is 100sccm to 500 sccm.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a method for improving crystal lattice damage, which increases the process time of electrostatic discharge treatment by three electrostatic discharge treatment processes, so that the charge on a wafer is fully discharged. By optimizing the static electricity releasing treatment process, the damage to crystal lattices in the contact hole etching process caused by charge accumulation is reduced, and the imaging quality of products is improved.
Drawings
FIG. 1 is a flow chart of a method of ameliorating lattice damage in an embodiment of the present invention;
FIG. 2 is a schematic diagram of an electrostatic chuck in an embodiment of the invention;
FIG. 3 is a diagram of a FA slice of a prior art electrostatic discharge process;
FIG. 4 is a diagram of FA slices of the discharge static electricity process in an embodiment of the present invention;
FIG. 5 is an EDS diagram of a prior art discharge static process;
FIG. 6 is an EDS diagram of a discharge static process in an example of the invention;
FIG. 7 is a prior art charge distribution diagram for a wafer undergoing electrostatic discharge processing;
FIG. 8 is a graph of the charge distribution of a wafer undergoing electrostatic discharge processing in accordance with an embodiment of the present invention;
reference numerals:
10-wafer, 20-chuck, 21-electrode a, 22-electrode B, 31-lattice damage, 41-wafer interface, 51-other component, 61-wafer interface.
Detailed Description
In the existing side wall etching process, an etching machine is required to be adopted, a side wall etching process is carried out on the wafer to form a side wall, and an electrostatic Chuck (ESC) is adopted to adsorb the wafer in the side wall etching process, so that the wafer is stabilized in a reaction chamber of the etching machine to carry out plasma etching. The electrostatic adsorption chuck adopts a double-electrode structure, a one-step electrostatic releasing treatment process is generally adopted in the prior art, the electrostatic releasing treatment process is very high in speed, and if charges between a wafer and the electrostatic adsorption chuck are not completely released, the charges are accumulated on the surface of the wafer, so that static electricity is easily formed, and the surface of the wafer is damaged.
The method for improving lattice damage according to the present invention is further described in detail with reference to the accompanying drawings and the following embodiments. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
The core idea of the method is to solve the problem of processing of the wafer from the side wall etching process to the contact hole etching process, and effectively solve the problem that static electricity residue on the wafer is left after the side wall etching process, and a charge accumulation area belongs to a weak area, so that the area is more prone to causing lattice damage in the next process, namely the contact hole process, and the imaging quality of a product is influenced.
As shown in fig. 1, an embodiment of the present invention provides a method for improving lattice damage of a source/drain region of an image sensor, including:
step S10, placing the wafer which completes the plasma etching process on a chuck, wherein the chuck comprises an electrode;
step S20, performing a first electrostatic discharge process on the wafer to discharge a portion of charges on the wafer;
step S30, performing a second electrostatic discharge treatment on the wafer, wherein the electrode provides a first reverse voltage to the wafer to discharge a part of charges on the wafer;
step S40, performing a third electrostatic discharge process on the wafer, wherein the electrode provides a second reverse voltage to the wafer to complete the discharge of the charges on the wafer.
The steps of the wafer processing method of the present embodiment are described in more detail below with reference to fig. 2-8.
Referring to fig. 2, step S10 is executed to dispose the wafer 10 on the chuck 20, the chuck 20 is disposed in a reaction chamber of a sidewall etching process, the wafer 10 has already been subjected to the sidewall etching process, and in the sidewall etching process, etching process conditions of high power, high plasma density, and the like are usually adopted, which inevitably leave large charges on the wafer 10, and the charges are accumulated on the surface of the wafer 10, which is easy to form static electricity and damage the surface of the wafer.
In this embodiment, the chuck 20 is an electrostatic chuck, the electrostatic chuck can control the temperature of the wafer to promote uniformity of etching the wafer, the electrostatic chuck can be provided with an electrode layer, when a voltage is applied to the electrode layer, different charges can be generated on the electrode layer and the wafer, so that coulomb attraction is generated between the electrode layer and the wafer, and the wafer is adsorbed on the surface of the electrostatic chuck. In the side wall etching process, plasma dry etching is adopted, and an electrostatic adsorption chuck of a plasma dry etching machine is of a double-electrode structure and specifically comprises an electrode A21 and an electrode B22.
Step S20 is executed to perform a first electrostatic discharge process on the wafer 10to discharge a portion of the charges on the wafer 10.
In the first static electricity releasing treatment process, argon is introduced, the electrode A21 and the electrode B22 do not output power, the argon is not changed into plasma, partial charges on the wafer are released, and the first static electricity releasing treatment is a natural static electricity releasing process of the wafer. The process time of the first static electricity releasing treatment is 1-10 seconds.
Optionally, the flow rate of the argon gas is 100sccm to 500 sccm.
Optionally, the pressure generated by the argon gas is 1torr to 20torr, that is, in the process chamber, the argon gas may be blown to the front surface of the wafer 10 by arranging a nozzle or the like, so that the wafer 10 is in an environment with a certain pressure.
Performing step S30, performing a second electrostatic discharge process on the wafer 10, wherein the electrode provides a first reverse voltage to the wafer 10to discharge a part of the charges on the wafer 10, and the second electrostatic discharge process discharges static electricity by neutralizing charges with plasma;
in the step S30, the power of the electrode of the first reverse voltage is set to 80 w-120 w as a buffer of the power of the electrode, the electrode discharge ionizes the argon gas, and the effect of neutralizing the charge on the wafer 10 is achieved through the charge introduction of the plasma.
In the second electrostatic discharge treatment process, the time for introducing the argon gas is 1 second to 10 seconds, and the charge on the wafer 10 is released again within the time range.
In the second electrostatic discharge treatment process, the flow and pressure of the argon gas are the same as those of the first electrostatic discharge treatment process, and are not described herein again.
Step S40 is executed to perform a third electrostatic discharge process on the wafer 10, wherein the electrode provides a second reverse voltage to the wafer 10to discharge a portion of the charges on the wafer 10, and the third electrostatic discharge process discharges the static electricity by neutralizing the charges with plasma.
In the third electrostatic discharge treatment process, the power of the electrode with the second reverse voltage is increased to 350-450 watts, the time of the third electrostatic discharge treatment process is between 4 and 40 seconds, argon is ionized by the electrode discharge, and the effect of fully discharging the charges on the wafer 10 is achieved in sufficient process time through the charge introduction of the plasma.
By adopting the method for improving the crystal lattice damage provided by the invention, the wafer which completes the side wall etching process is subjected to static electricity discharge treatment.
Fig. 3 is a diagram of FA slices after electrostatic discharge treatment in the prior art, and fig. 4 is a diagram of FA slices after electrostatic discharge treatment in an embodiment of the present invention. In contrast, after performing Failure Analysis (FA) on the wafer after the contact hole etching process of the esd process in the prior art and the contact hole etching process of the embodiment of the invention, as shown in fig. 3, damage 31 to the crystal lattice of the wafer can be clearly seen in the FA slice of the wafer of the esd process in the prior art, whereas the interface 41 of the wafer of the embodiment of the invention in fig. 4 is relatively smooth. By adopting the static electricity releasing treatment process provided by the embodiment of the invention, the lattice damage in the contact hole etching process caused by charge accumulation is reduced, and the product yield is improved.
Fig. 5 is an EDS diagram of a discharge static electricity process in the related art, and fig. 6 is an EDS diagram of a discharge static electricity process in the embodiment of the present invention. In contrast, when the wafers subjected to the electrostatic discharge treatment in the prior art and the electrostatic discharge treatment in the embodiment of the present invention are subjected to X-ray energy spectrum analysis (EDS) analysis, as shown in fig. 5, the permeation of the other component 51 is clearly seen in the EDS of the wafers subjected to the electrostatic discharge treatment in the prior art, whereas the interface 61 of the wafer subjected to the electrostatic discharge treatment in the embodiment of the present invention in fig. 6 is free from the permeation of the other component, and the component obtained by the X-ray energy spectrum analysis of the permeated component in fig. 5 is titanium (Ti).
Since after the contact hole etching process, a layer of Ti needs to be deposited in the contact hole before depositing the metal tungsten, so as to increase the adhesion between layers. When more charges are accumulated in the wafer in the contact hole area in the side wall etching process, crystal lattice damage is caused, and Ti permeates into the crystal lattice damage area. When the static electricity releasing treatment process is used for releasing the charges on the wafer fully, the crystal lattice damage below the contact hole is reduced, and the leakage of Ti in a floating diffusion region is avoided.
FIG. 7 is a prior art charge distribution diagram for a wafer after a contact hole etch process with electrostatic discharge, and FIG. 8 is a prior art charge distribution diagram for a wafer after a contact hole etch process with electrostatic discharge. By contrast, when wafer charge distribution tests are performed on the wafer subjected to the electrostatic discharge treatment in the prior art and the wafer subjected to the electrostatic discharge treatment in the embodiment of the present invention, it can be seen that the residual charge amount of the wafer in fig. 7 is 0.408, and the residual charge amount of the wafer in fig. 8 is 0.591.
In summary, after the sidewall etching process is completed, a large amount of free charges exist in the process chamber and the surface of the wafer, and the charges are difficult to be effectively released without a good conduction path so as to be removed from the surface of the wafer. According to the embodiment of the invention, through optimizing the static electricity releasing treatment process in the side wall etching process, the static electricity of the wafer is reduced, and the lattice damage caused by plasma bombardment in the contact hole etching process is reduced. The imaging quality of the product is improved while the process requirements of the device are met. Meanwhile, the static electricity of the wafer is fully released, the damage to crystal lattices in the contact hole etching process is reduced, and the wafer is not required to be protected by a thicker oxide layer in the contact hole etching process, so that the thickness of the oxide layer can be reduced, and better image quality can be obtained by reducing the thickness of the oxide layer.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (8)
1. A method of ameliorating lattice damage, comprising:
placing a wafer on a chuck, the wafer having completed a plasma etch process, the chuck comprising an electrode;
performing first electrostatic discharge treatment on the wafer to discharge partial charges on the wafer;
performing second electrostatic discharge treatment on the wafer, wherein the electrode provides a first reverse voltage for the wafer so as to discharge partial charges on the wafer;
and performing third electrostatic discharge treatment on the wafer, wherein the electrode provides a second reverse voltage for the wafer so as to complete the charge discharge on the wafer.
2. A method for improving lattice damage according to claim 1, wherein the power of the electrodes in the first discharge electrostatic treatment, the second discharge electrostatic treatment and the third discharge electrostatic treatment is sequentially increased.
3. The method for improving lattice damage of claim 2, wherein in the second electrostatic discharge treatment, the power of the electrode is 80-120 w; in the third electrostatic discharge treatment, the power of the electrode is 350-450W.
4. The method according to claim 1, wherein the first electrostatic discharge treatment and the second electrostatic discharge treatment are performed for a period of time ranging from 1 second to 10 seconds.
5. The method according to claim 1, wherein the third discharge electrostatic treatment electrode is processed for 4 to 40 seconds.
6. The method according to claim 1, wherein argon gas is introduced into the front surface of the wafer during the first destaticizing treatment, the second destaticizing treatment and the third destaticizing treatment.
7. The method of claim 6, wherein the argon gas is generated at a pressure of 1torr to 10 torr.
8. The method according to claim 7, wherein the flow rate of argon gas is 100sccm to 500 sccm.
Priority Applications (1)
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| CN202011104593.8A CN112233977A (en) | 2020-10-15 | 2020-10-15 | Method for improving lattice damage |
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| CN202011104593.8A CN112233977A (en) | 2020-10-15 | 2020-10-15 | Method for improving lattice damage |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113937005A (en) * | 2021-12-16 | 2022-01-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing metal oxide semiconductor transistor |
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| US20100227470A1 (en) * | 2009-03-05 | 2010-09-09 | Renesas Technology Corp. | Manufacturing Method of Semiconductor Integrated Circuit Device |
| CN105140115A (en) * | 2015-07-22 | 2015-12-09 | 上海华力微电子有限公司 | Method for improving spherical defect by optimizing charge releasing step process condition |
| CN111223808A (en) * | 2018-11-23 | 2020-06-02 | 长鑫存储技术有限公司 | Electrostatic discharge method and device for electrostatic chuck |
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2020
- 2020-10-15 CN CN202011104593.8A patent/CN112233977A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101728230A (en) * | 2008-10-17 | 2010-06-09 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for processing semiconductor substrate |
| US20100227470A1 (en) * | 2009-03-05 | 2010-09-09 | Renesas Technology Corp. | Manufacturing Method of Semiconductor Integrated Circuit Device |
| CN105140115A (en) * | 2015-07-22 | 2015-12-09 | 上海华力微电子有限公司 | Method for improving spherical defect by optimizing charge releasing step process condition |
| CN111223808A (en) * | 2018-11-23 | 2020-06-02 | 长鑫存储技术有限公司 | Electrostatic discharge method and device for electrostatic chuck |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113937005A (en) * | 2021-12-16 | 2022-01-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing metal oxide semiconductor transistor |
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