CN100362776C - Method of proceeding resynchronization of interface link - Google Patents
Method of proceeding resynchronization of interface link Download PDFInfo
- Publication number
- CN100362776C CN100362776C CNB2004100801646A CN200410080164A CN100362776C CN 100362776 C CN100362776 C CN 100362776C CN B2004100801646 A CNB2004100801646 A CN B2004100801646A CN 200410080164 A CN200410080164 A CN 200410080164A CN 100362776 C CN100362776 C CN 100362776C
- Authority
- CN
- China
- Prior art keywords
- synchronous
- logic port
- interface
- state
- receiving entity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention discloses a method for synchronizing interface links again. The interface is provided with two logic ports, and a receiving body and a sending body are arranged on each logic port. The method comprises the step that each logic port detects whether the state of an interface link transmission signal received by the self receiving body is normal or not; when the signal state is abnormal, the logic port triggers the self sending body to send a first notification message used for requiring a synchronous training frame to the receiving body of the other logic port; after the other logic port detects the first notification message received by the self receiving body, the logic port triggers the self sending body to send the synchronous training frame to the receiving body of the logic port which detects the abnormal state of the interface link transmission signal; the receiving body processes the interface links again synchronously according to the received synchronous training frame. When the interface links are in an abnormal state, the present invention can quickly recover a synchronous state to improve the transmission performance of the interface links.
Description
Technical field
The present invention relates to the transmission signals simultaneous techniques field in the communication system, relate in particular to a kind of docking port link and carry out again synchronous method.
Background technology
At present in various communications network systems, for reliability and the transmission rate thereof that improves transmission link, in the high speed digital interface design of each node device of communication network, adopt two kinds of designs usually, to guarantee the stable transfer of high speed digital interface to signal:
(1) parallel/serial conversion designs after promptly high speed digital interface is converted to serial signal with parallel signal, is transmitted with the differential signal form by transmission mediums such as coaxial cable or light delivery modules;
(2) interface Synchronization Design promptly is provided with a synchronous state machine in high speed digital interface, come the state of effective monitoring signal link with the synchronous state machine by this setting, to reach the control signal reliability of link transmission.
See also Fig. 1, this figure is the principle schematic of a representative synchronization state machine structure being provided with in high speed digital interface in the prior art; Wherein synchronous state machine is that to make transmission link reach synchronous processing procedure as follows in the high speed digital interface:
When this synchronous state machine is powering on (Power Up) or (Reset) when operation that reset, synchronous state machine will enter the synchronization acquistion state, and (ACQ Acquisition), catches synchronous train word or synchronous control signal with wait; In case interface receives the synchronous train word or the synchronous control signal of prior regulation, this synchronous state machine will enter into synchronous regime (SYNC, Synchronization);
Sync state is the interface link normal operating conditions, if under sync state, interface receives invalid code word, and synchronous state machine will enter into the CHECK state;
The CHECK state is the state that invalid code word appears in interface link, it is in synchronous critical condition, if receive several synchronous train word or synchronically controlling informations continuously at CHECK state lower interface, then synchronous state machine will turn back to normal transmitting-receiving transmission information under the sync state; And if receive several invalid code words continuously at CHECK state lower interface, then synchronous state machine will turn back to the ACQ state, wait for catching synchronous train word or synchronically controlling information again, and will be synchronous to carry out again.
Above-mentionedly carry out in the process of Synchronous Processing at interface link, in case interface link enters non-sync state (being ACQ state and CHECK state), link just will enter abnormal operating state, its even parity check that may show as in the data frame structure of link transmission makes mistakes, or the data-frame sync signal appearance that is attended by link transmission is unusual, or phenomenons such as losing lock appear in interface chip.At this moment interface link transmission is very unsettled, promptly can not be used for normal information transmit-receive, and these phenomenons of makeing mistakes will be waited until after synchronous state machine reenters sync state always and could eliminate.
Generally, the interface Synchronization Design that high speed digital interface carried out is to adopt " open loop " method of synchronization, be not have information interaction to handle between the transmit leg of interface and the recipient, then interface recipient's synchronization acquistion handle to rely on the transmit leg cycle to send synchronous train word to control, if transmit leg not expection sends the synchronous train word that pre-sets according to the rules, perhaps the synchronous train word cycle of Fa Songing falls short of, and then all can cause the recipient to be in non-sync state (comprising CHECK state and ACQ state) all the time.
Based on above-mentioned high speed digital interface Synchronization Design principle, as working as owing to the restriction that is subjected to the Interface design bandwidth, can not transmit the sufficiently long synchronous train word cycle so that reserve, to cause interface link in start-up course, have only by software control mode control interface link and reach synchronous regime, and the interface link synchronously is in a kind of critical condition, in case because certain is unusual, interface link after the Synchronous Processing will enter asynchronous regime (CHECK state and ACQ state) from synchronous regime (sync state), synchronous state machine will be absorbed in a kind of endless loop state like this, causes interface link can not reenter link synchronization state (sync state).
Therefore reason to sum up can operate as normal in order to guarantee interface link, and can finish Synchronous Processing again smoothly when asynchronous regime appears in interface link, to change synchronous regime work over to, has tended to following several processing mode in the prior art:
A. design synchronous state machine in the high speed digital interface by expensive hardware designs mechanism, avoid the generation of interface link abnormality with the probability of minimum, thereby reach the link error probability of happening that transmission system can be tolerated.Or
B. revise the design of the high speed digital interface of each node in the transmission system, to guarantee that interface has enough transmission bandwidths to come the transmitting synchronous train word, since the control interface link generation of link abnormality appears, but this mode will all be revised the high speed digital interface that designed early stage, therefore will cause the waste to early investment undoubtedly.Or
C. by the Synchronous Processing again that high layer software comes the control interface link is set, in case promptly interface link enters the abnormal work state, can come the control interface transmitting terminal to resend synchronous train word by the high layer software of this setting, so that the synchronous train word that interface iSCSI receiving end is sent according to transmitting terminal carries out Synchronous Processing again, but this mode can increase the complexity of high layer software design on the one hand, on the other hand because software processes has the delay attribute, therefore can cause interface link bust this overlong time, thereby influence the transmission quality of whole transmission system.
Summary of the invention
The technical problem to be solved in the present invention is to propose a kind of simple and effective docking port link to carry out again synchronous method, to reduce the complexity of Interface design, and when abnormality appears in interface link, can quickly recover to synchronous regime, to improve the transmission performance of interface link.
For addressing the above problem, the present invention proposes a kind of docking port link and carry out again synchronous method, described interface has two logic ports, is respectively arranged with receiving entity and sending entity on each logic port, comprises step:
Whether the interface link transmission signals state that each logic port detection self receiving entity receives is normal; And
When described interface link transmission signals state is undesired, triggers self sending entity and send and be used to ask the receiving entity of first notification message of synchronous training frames to another logic port;
After described another logic port detects self receiving entity and receives first notification message, trigger self sending entity and send synchronous training frames, and described synchronous training frames is sent to the described receiving entity that detects the abnormal logic port of interface link transmission signals state;
Described receiving entity carries out Synchronous Processing again according to the synchronous training frames docking port link that receives.
Described method also comprises step:
Each logic port is detecting interface link transmission signals state that self receiving entity receives just often, triggers self sending entity and sends and be used to ask the receiving entity of second notification message of normal data frames to another logic port;
After described another logic port detects self receiving entity and receives second notification message, trigger self sending entity and send normal data frames to the described receiving entity that detects the normal logic port of interface link transmission signals state.
Described detection interface link transmission signals state comprises:
Detect the clock signal state in the interface link transmission signals; Or
Detect the losing lock signal condition in the interface link transmission signals; Or
Detect the check information state in the interface link transmission signals.
The state of described each logic port cycle detection interface link transmission signals.
Described each logic port detects interface link transmission signals state that self receiving entity receives when undesired in described one-period, it is the normal data frames that carries synchronous training frames solicited message that being used to of triggering that self sending entity sends asked first notification message of synchronous training frames.
Described each logic port detects interface link transmission signals state that self receiving entity receives when undesired in continuous two described cycles, it is the synchronous training frames that carries synchronous training frames solicited message that being used to of triggering that self sending entity sends asked first notification message of synchronous training frames.
Described second notification message is the normal data frames that carries the normal data frames solicited message.
The frame format of described normal data frames comprises:
Be used to carry the request domain of solicited message;
Be used to carry the synchronizing information territory of synchronous train word or synchronically controlling information; And
Be used to carry the valid data territory of regular traffic data.
Described synchronous training frames is for partly or entirely being used for carrying the Frame that synchronous train word or synchronically controlling information constitutes with valid data territory in the normal data frames.
The beneficial effect that the present invention can reach is as follows:
Docking port link of the present invention carries out again synchronous method when detecting self receiving entity and receive abnormal interface link transmission signals by each logic port, triggering self sending entity sends and is used to ask the receiving entity of first notification message of synchronous training frames to another logic port, sending entity on this another logic port just sends synchronous training frames to the receiving entity that detects the abnormal logic port of interface link transmission signals state, and this receiving entity carries out Synchronous Processing again according to the synchronous training frames docking port link that receives; So only need design a synchronous training frames and a normal data frames as required, and need not the design of the high speed digital interface of each node in the transmission system is made amendment, also need not to be provided with high layer software and come the synchronous again of control interface link, so both can save design cost in the past, can be owing to the delay attribute of software processes yet, and cause interface link bust this overlong time, thereby have influence on the transmission quality of whole transmission system, can make interface link under asynchronous operating state, can return to the synchronous working state from desynchronizing state automatically within a short period of time, reduce the complexity of Interface design, and improved the transmission performance of interface link.
Description of drawings
Fig. 1 is the principle schematic of a representative synchronization state machine structure being provided with in high speed digital interface in the prior art;
Fig. 2 is the mode schematic diagram of high speed digital interface;
Fig. 3 is the realization principle flow chart that docking port link of the present invention carries out again synchronous method;
Fig. 4 carries out again the normal data frames frame format schematic diagram that designs in the synchronous method at docking port link of the present invention;
Fig. 5 carries out again the synchronous training frames frame format schematic diagram that designs in the synchronous method at docking port link of the present invention.
Embodiment
Docking port link of the present invention carries out again synchronous method and is applicable to and all physics Interface design in the network system especially more is applicable to high speed digital interface; Because in the high speed digital interface transmission of standard, its interface two ends clock phase and data sync thereof are the prerequisites that high speed digital interface carries out stable transfer, therefore to obtain to transmit data synchronization and just need design a kind of synchronous training mechanism for high speed digital interface, usually adopt the interface two ends corresponding synchronous train word of making an appointment to make clock phase and data thereof reach synchronous, in a single day but be not enough to carry under the situation of synchronous train word bandwidth when interface transmission bandwidth occurring, at this moment just there has been very big risk in the reliability transmission of high speed digital interface, think interface, especially high speed digital interface in the existing network system provide a kind of reliably again synchronously security mechanism the transmission performance of high speed digital interface is played important effect.
Docking port link of the present invention carries out again synchronous method purpose of design just at the defective of above-mentioned existence, providing a kind of is applied in the high speed digital interface and does not need self-healing that high layer software intervenes synchronization mechanism again, make high speed digital interface constantly and (its physical cause comprises as situations such as transmission signal line are pulled out when having occurred non-physicogenic step-out operating state in the data transmission procedure at transmission start, because when transmission signal line is pulled out, transmission channel has not had transmission medium, therefore the present invention can not be worked in this case interface link step-out), automatically the transmission of restoration interface link data is synchronous, thereby improves the reliability of high speed digital interface transmission.
Below in conjunction with each accompanying drawing the specific implementation process that docking port link of the present invention carries out again synchronous method is described in detail.
The mentioned interface of the present invention comprises the various kinds of interfaces in the network system, and more is applicable to high speed digital interface, below just be that the example docking port link of the present invention that is elaborated carries out again synchronous performance with the high speed digital interface.See also Fig. 2, this figure is the mode schematic diagram of high speed digital interface; High speed digital interface mode as shown in Figure 2, a high speed digital interface logically is divided into two logic ports: logic port A and logic port B, and each logic port is provided with a sending entity and a receiving entity by logic; Each entity title on the logic port B and act on as follows wherein:
Receiving entity E0: be used for down link data and receive;
Sending entity E1: be used for uplink data and send;
Each entity title on the logic port A and act on as follows:
Receiving entity E2: be used for uplink data and receive;
Sending entity E3: be used for down link data and send;
Wherein receiving entity E0 on the logic port B and the receiving entity E2 on the logic port A belong to peer-entities, and the work behavior unanimity all is the reception behavior;
And sending entity E1 on the logic port B and the sending entity E3 on the logic port A also belong to peer-entities, and the work behavior unanimity all is the transmission behavior;
The present invention does not consider the transmission signals form of high speed digital interface here, coded system and parallel data are to the transfer process of serial data, but adopt docking port to carry out the abstract processing of logic entity, reason is that to carry out again the main points that synchronous method pays close attention to are transmission structures of interface concurrent data to docking port link of the present invention, and because the high speed digital interface transmission signals is a differential analog signal in view of the physical signalling form, from transmitting terminal, signal is before becoming differential signal, normally 0, the digital signal of 1 level form, need insert by check digit, the 8B/10B coding, the FIFO buffer memory, and string conversion, (high-frequency clock reaches hundreds of million usually in processing such as serial transmission and high-frequency clock generation, even a few gigabit HZ speed), changing the low-voltage differential analog signal at last into sends, this part signal conversion process work all is to be finished by special chip and IP kernel core module (IP core) usually, so the present invention will not consider this part signal processing.
The main design philosophy that docking port link of the present invention carries out again synchronous method is: adopt " information notification " mechanism, do not needing under the outside situation about getting involved, guaranteeing does not again simultaneously increase under the prerequisite of additional transmissions bandwidth, variation by the high speed digital interface transmission frame-form, make the receiving entity on the logic port in the interface in a single day detect the interface link transmission signals state of reception when undesired, can " inform " that the receiving entity on the other side's logic port restarts a subsynchronous training frames by the sending entity of this logic port, and synchronous training frames sent to the receiving entity that the logic port of information " is informed " in transmission, make this receiving entity carry out Synchronous Processing again according to the synchronous training frames docking port link that receives, again return to synchronous regime up to original interface link transmission, to reach the synchronous purpose of self-healing.
See also Fig. 3, this figure is the realization principle flow chart that docking port link of the present invention carries out again synchronous method; It is mainly as follows wherein the high speed digital interface link to be carried out again synchronous processing procedure:
Step S10, the receiving entity receiving interface link transmission signal on each logic port;
Step S20, whether the interface link transmission signals state that each logic port detection self receiving entity receives is normal; If normal, execution in step S60, otherwise execution in step S30; Wherein logic port detection interface link transmission signals state can be by detecting the clock signal state in the interface link transmission signals, or detect losing lock signal condition in the interface link transmission signals, or the check information state in the interface link transmission signals of detecting is judged interface link transmission signals state that self receiving entity receives whether normal (being whether interface link is in the synchronous transmission operating state); And each logic port can detect the state of interface link transmission signals periodically.
Step S30, this detects the abnormal logic port of interface link transmission signals state and triggers self sending entity and send first notification message that is used to the to ask synchronous training frames receiving entity to another logic port;
After step S40, another logic port detect self receiving entity and receive first notification message, trigger self sending entity and send synchronous training frames to the receiving entity that detects the abnormal logic port of interface link transmission signals state;
Step S50, the receiving entity that detects the abnormal logic port of interface link transmission signals state carries out Synchronous Processing again according to the synchronous training frames docking port link that receives;
Step S60 detects the normal logic port triggering of interface link transmission signals state self sending entity transmission and is used to ask the receiving entity of second notification message of normal data frames to another logic port;
After step S70, this another logic port detect self receiving entity and receive second notification message, trigger self sending entity and send normal data frames to the described receiving entity that detects the normal logic port of interface link transmission signals state.
Thereby, when just can be implemented in interface link and the step-out operating state occurring, can control in the self-healing mode high speed digital interface link is carried out again synchronous processing by above-mentioned processing procedure.
Wherein the frame format of above-mentioned described normal data frames includes but not limited to following hosting domain:
Be used to carry the request domain of solicited message; And
Be used to carry the synchronizing information territory of synchronous train word or synchronically controlling information; And
Be used to carry the valid data territory of regular traffic data.
See also Fig. 4, this figure carries out again the normal data frames frame format schematic diagram that designs in the synchronous method at docking port link of the present invention; Wherein the synchronizing information territory is used for carrying synchronous train word or the synchronically controlling information that is used for the interface link Synchronous Processing; IDLE represents request domain, is used for carrying the solicited message that is used to ask synchronous training frames or normal data frames; The valid data territory is used for carrying the business datum of normal transmission; Data keep the subsequent expansion that the position is used for the frame function, and generally " 0 " is filled out in this territory.
See also Fig. 5, this figure carries out again the synchronous training frames frame format schematic diagram that designs in the synchronous method at docking port link of the present invention; Synchronous training frames frame format shown in Figure 5 is compared with normal data frames frame format shown in Figure 4, be that valid data territory in the normal data frames partly or entirely all is used for having carried synchronous train word or synchronically controlling information, what be synchronous training frames with the valid data territory in the normal data frames partly or entirely all is used for sending synchronically controlling information or train word synchronously, She Ji synchronous training frames just can guarantee to occur under the state of step-out work at interface link like this, the Synchronous Processing that has enough synchronically controlling informations or synchronous train word to come the control interface link.
Please continue to consult simultaneously the mode schematic diagram of high speed digital interface shown in Figure 2, normal data frames frame format schematic diagram shown in Figure 4, with synchronous training frames frame format schematic diagram shown in Figure 5, the specific implementation principle that docking port link of the present invention carries out again synchronous method is elaborated with a preferred embodiment.
Because being commonly used to characterize the information of the interface link transmission signals state of high speed digital interface has: the check information state in the clock signal state in the interface link transmission signals, losing lock signal condition and the transmission data etc.; The operating state that the present invention adopts the losing lock signal condition that detects in the interface link transmission signals to characterize the interface link transmission signals here is that example describes.When in case receiving entity E0 on the logic port B or the receiving entity E2 on the logic port A receive the losing lock signal, just think that the operating state of interface link has entered abnormal operating state, at this moment the transfer of data on the interface link is insecure, needs a kind of synchronization mechanism and can the control interface link transmission return to synchronous regime again.
In normal data frames frame structure shown in Figure 4 and synchronous training frames frame structure shown in Figure 5, all defined the IDLE request domain in same position, be used for carrying and be used to ask the normal data frames or the solicited message of training frames synchronously, adopt a binary bits to represent.This IDLE request domain is primarily aimed at receiving entity E0 or receiving entity E2 is provided with, as supposing: if in the Frame that the receiving entity E0 on the logic port B (or the receiving entity E2 on the logic port A) receives, IDLE request domain loaded information is " 0 ", and expression requires the sending entity E1 (or require on the logic port A sending entity E3) on the current logic port B to send normal data frames shown in Figure 4 to the receiving entity E2 on the logic port A (or give on the logic port B receiving entity E0); And if in the Frame that the receiving entity E0 on the logic port B (or the receiving entity E2 on the logic port A) receives, IDLE request domain loaded information is " 1 ", and expression requires the sending entity E1 (or require on the logic port A sending entity E3) on the current logic port B to send synchronous training frames shown in Figure 5 to the receiving entity E2 on the logic port A (or give on the logic port B receiving entity E0); Thereby reach by above-mentioned data transmission mechanism and to make interface link return to the purpose of synchronous working state again.
Docking port link of the present invention carries out again synchronous method and has defined following transmission principle (or being called transport behavior), transmits normal data frames or synchronous training frames mutually to be used to controlling two transmitting-receiving entities between the logic port:
1) each logic port detects interface link transmission signals state that self receiving entity receives when undesired in the one-period of predesignating, trigger self sending entity send carry synchronous training frames solicited message normal data frames to be used for as first notification message of asking synchronous training frames;
As above routine, if the receiving entity E0 on the logic port B (or the receiving entity E2 on the logic port A), promptly triggers sending entity E1 (or the sending entity E3 on this logic port A) on this logic port B in case detect in the interface link transmission signals input of losing lock signal by period T and sends the set of IDLE request domain and give receiving entity E2 (or the receiving entity E0 on the logic port B) on the logic port A for the normal data frames of " 1 "; After receiving entity E2 (or E0) receives normal data frames, detect in the normal data frames IDLE request domain and be " 1 ", just the sending entity E3 (or the sending entity E1 on the logic port B) that triggers on the inherent logic port A sends synchronous training frames to the receiving entity E0 on the logic port B (or the receiving entity E2 on the logic port A), and logic port B (or logic port A) carries out Synchronous Processing again according to the synchronous training frames docking port link of self receiving entity E0 (or receiving entity E2) reception.
2) each logic port detects interface link transmission signals state that self receiving entity receives when undesired in continuous two cycles of predesignating, and triggers self sending entity and sends the synchronous training frames that carries synchronous training frames solicited message with as first notification message that is used to ask synchronous training frames;
As above routine, if the receiving entity E0 on the logic port B (or the receiving entity E2 on the logic port A) still detects losing lock signal input in the interface link transmission signals in continuous two period T, the beared information of representing IDLE request domain in the Frame that the sending entity E1 (or the sending entity E3 on this logic port A) on this logic port B sends in last one-period T does not come into force, and the synchronous training frames that need the sending entity E1 (or the sending entity E3 on this logic port A) on this logic port sends the set of IDLE request domain and be " 1 " is to the receiving entity E2 (or the receiving entity E0 on the logic port B) on the logic port A; After receiving entity E2 (or E0) receives synchronous training frames, detect in the synchronous training frames IDLE request domain and be " 1 ", just the sending entity E3 (or the sending entity E1 on the logic port B) that triggers on the inherent logic port A sends synchronous training frames to the receiving entity E0 on the logic port B (or the receiving entity E2 on the logic port A), and logic port B (or logic port A) carries out Synchronous Processing again according to the synchronous training frames docking port link of self receiving entity E0 (or receiving entity E2) reception.
3) two kinds of situations to sum up, receiving entity E0 (or receiving entity E2) on the logic port B (or logic port A) can constantly detect the solicited message of the IDLE request domain carrying in the Frame (comprising normal data frames and synchronous training frames) that receives, be " 1 " in case detect the solicited message of IDLE request domain carrying, the sending entity E1 (or sending entity E3) that then triggers on this logic port B (or logic port A) sends synchronous training frames; Wherein training frames is under default situation synchronously, and the IDLE request domain in the training frames is put invalid bit " 0 " synchronously.
To sum up, in the above-mentioned transmission principle (or transport behavior), owing in normal data frames and synchronous training frames, all defined the IDLE request domain, so send normal data frames or send synchronous training frames with whether set IDLE request domain is two independently behaviors, detect by the interface link transmission signals state that receiving entity E0/E2 is received, its detection is divided into following several situation:
Detect and whether be the input of losing lock signal; Or
Detect and whether receive the Frame of IDLE request domain set for " 1 "; Or
Whether detect when continuous two sense cycle T meter is full, still receive the losing lock signal;
By selecting above-mentioned three kinds of detection modes to decide the transport behavior of local terminal sending entity E1/E3, its transport behavior is divided into following mode:
Send normal data frames or synchronous training frames that set IDLE request domain is " 1 "; Or
Send synchronous training frames.
Docking port link of the present invention carries out again synchronous method and can be implemented in and make high speed digital interface return to the synchronous working state again from the step-out operating state in the shortest 4 sense cycle T under the situation that does not have physical device to damage, and obtains the stable data transmission.
Certainly; docking port link of the present invention carries out again synchronous method also can be not limited to losing lock signal condition in the above-mentioned detection interface link transmission signals; look concrete condition; can select by synchronizing clock signals state in the detection interface link transmission signals or check information state etc., these detection modes are also all in protection scope of the present invention.
Docking port link wherein of the present invention carries out again synchronous method and proposes when the receiving entity of each logic port receives the interface link transmission signals of abnormal state, the sending entity transmission that triggers on the port is used to ask the other side's logic port to send the notification message of synchronous training frames, after the notified message of the other side's logic port, trigger self sending entity and send synchronous training frames, but owing to this synchronous training frames is to be used for sending synchronically controlling information or the Frame transformed of train word synchronously, the transmission that can lose valid data so undoubtedly with the valid data territory in the normal data frames is all or part of; But the present invention thinks that here this valid data loss once in a while can bring being worth synchronously again of interface link, this value of the present invention just place.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. a docking port link carries out again synchronous method, and described interface has two logic ports, is respectively arranged with receiving entity and sending entity on each logic port, it is characterized in that, comprises step:
Whether the interface link transmission signals state that each logic port detection self receiving entity receives is normal; And
When described interface link transmission signals state is undesired, triggers self sending entity and send and be used to ask the receiving entity of first notification message of synchronous training frames to another logic port;
After described another logic port detects self receiving entity and receives first notification message, trigger self sending entity and send synchronous training frames, and described synchronous training frames is sent to the described receiving entity that detects the abnormal logic port of interface link transmission signals state;
Described receiving entity carries out Synchronous Processing again according to the synchronous training frames docking port link that receives.
2. docking port link according to claim 1 carries out again synchronous method, it is characterized in that, also comprises step:
Each logic port is detecting interface link transmission signals state that self receiving entity receives just often, triggers self sending entity and sends and be used to ask the receiving entity of second notification message of normal data frames to another logic port;
After described another logic port detects self receiving entity and receives second notification message, trigger self sending entity and send normal data frames to the described receiving entity that detects the normal logic port of interface link transmission signals state.
3. docking port link according to claim 1 carries out again synchronous method, it is characterized in that, described detection interface link transmission signals state comprises:
Detect the clock signal state in the interface link transmission signals; Or
Detect the losing lock signal condition in the interface link transmission signals; Or
Detect the check information state in the interface link transmission signals.
4. docking port link according to claim 1 carries out again synchronous method, it is characterized in that, the state of described each logic port cycle detection interface link transmission signals.
5. docking port link according to claim 4 carries out again synchronous method, it is characterized in that, described each logic port detects interface link transmission signals state that self receiving entity receives when undesired in described one-period, it is the normal data frames that carries synchronous training frames solicited message that being used to of triggering that self sending entity sends asked first notification message of synchronous training frames.
6. docking port link according to claim 4 carries out again synchronous method, it is characterized in that, described each logic port detects interface link transmission signals state that self receiving entity receives when undesired in continuous two described cycles, it is the synchronous training frames that carries synchronous training frames solicited message that being used to of triggering that self sending entity sends asked first notification message of synchronous training frames.
7. docking port link according to claim 2 carries out again synchronous method, it is characterized in that, described second notification message is the normal data frames that carries the normal data frames solicited message.
8. carry out again synchronous method according to claim 2,5 or 7 described docking port links, it is characterized in that the frame format of described normal data frames comprises:
Be used to carry the request domain of solicited message;
Be used to carry the synchronizing information territory of synchronous train word or synchronically controlling information; And
Be used to carry the valid data territory of regular traffic data.
9. docking port link according to claim 8 carries out again synchronous method, it is characterized in that described synchronous training frames is for partly or entirely being used for carrying the Frame that synchronous train word or synchronically controlling information constitutes with valid data territory in the normal data frames.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100801646A CN100362776C (en) | 2004-09-24 | 2004-09-24 | Method of proceeding resynchronization of interface link |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100801646A CN100362776C (en) | 2004-09-24 | 2004-09-24 | Method of proceeding resynchronization of interface link |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1753331A CN1753331A (en) | 2006-03-29 |
| CN100362776C true CN100362776C (en) | 2008-01-16 |
Family
ID=36680035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100801646A Expired - Fee Related CN100362776C (en) | 2004-09-24 | 2004-09-24 | Method of proceeding resynchronization of interface link |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100362776C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100479382C (en) * | 2006-05-11 | 2009-04-15 | 华为技术有限公司 | Device and method for implementing service automatic recovery |
| CN103427939A (en) * | 2012-05-18 | 2013-12-04 | 中兴通讯股份有限公司 | XGMII-based channel deadlock automatic recovery method and chips |
| CN103581450B (en) * | 2012-07-25 | 2018-03-23 | 中兴通讯股份有限公司 | Power-economizing method and device |
| CN114745450A (en) * | 2022-04-19 | 2022-07-12 | 苏州盛科科技有限公司 | Chip port link training connection method and application |
| CN115225113A (en) * | 2022-07-13 | 2022-10-21 | 佛山市星曼信息科技有限公司 | Communication port matching method, device, communication module and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5748684A (en) * | 1992-03-18 | 1998-05-05 | Crystal Semiconductor, Inc. | Resynchronization of a synchronous serial interface |
| JP2000224265A (en) * | 1999-02-03 | 2000-08-11 | Hitachi Telecom Technol Ltd | Communication equipment, and line fault detection method for the communication equipment |
| CN1298580A (en) * | 1998-02-27 | 2001-06-06 | 西门子公司 | Common air interface for home telecommunications systems with wireless telecommunication based on code and time-multiplex |
| CN1094009C (en) * | 1995-06-13 | 2002-11-06 | 艾利森电话股份有限公司 | Synchronizing the transmission of data via a two-way link |
| CN1097911C (en) * | 1995-04-24 | 2003-01-01 | 艾利森电话股份有限公司 | Telecommunication system and method for transferring microcells therein |
-
2004
- 2004-09-24 CN CNB2004100801646A patent/CN100362776C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5748684A (en) * | 1992-03-18 | 1998-05-05 | Crystal Semiconductor, Inc. | Resynchronization of a synchronous serial interface |
| CN1097911C (en) * | 1995-04-24 | 2003-01-01 | 艾利森电话股份有限公司 | Telecommunication system and method for transferring microcells therein |
| CN1094009C (en) * | 1995-06-13 | 2002-11-06 | 艾利森电话股份有限公司 | Synchronizing the transmission of data via a two-way link |
| CN1298580A (en) * | 1998-02-27 | 2001-06-06 | 西门子公司 | Common air interface for home telecommunications systems with wireless telecommunication based on code and time-multiplex |
| JP2000224265A (en) * | 1999-02-03 | 2000-08-11 | Hitachi Telecom Technol Ltd | Communication equipment, and line fault detection method for the communication equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1753331A (en) | 2006-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5577075A (en) | Distributed clocking system | |
| CN102684904B (en) | The system and method for dynamic management power in communication system | |
| US10892839B2 (en) | Method for fast reconfiguration of GM clocks in the TSN network by means of an explicit teardown message | |
| CN100571114C (en) | A kind of synchronised clock providing device and implementation method | |
| JPH10136000A (en) | Switching device for active reference by synchronization message | |
| US20110173347A1 (en) | Method for synchronizing local clocks in a distributed computer network | |
| CN100362776C (en) | Method of proceeding resynchronization of interface link | |
| CN101719837A (en) | Clock board, network system suitable for server and clock switching method | |
| WO1995024801A2 (en) | Hierarchical synchronization method | |
| CN101621371A (en) | Clock design method and clock device | |
| CN1151627C (en) | Synchronous clock supply device | |
| CN102170375A (en) | Method, device and system for obtaining configuration information of correspondence node, and node equipment | |
| EP3319249B1 (en) | Transmission checking method, node, system and computer storage medium | |
| CN100349469C (en) | Special small ISON exchange selecting synchronous pulse source automatically | |
| SE435011B (en) | SET UP AND DEVICE IN A TELECOMMUNICATION SYSTEM WHEN ACTIVATING SUBSCRIBER TERMINALS | |
| WO2012071838A1 (en) | Multi-link clock recovery method and apparatus | |
| CN100367717C (en) | Method for realizing OTN apparatus self-adaptation | |
| US7969870B2 (en) | Line accommodating device | |
| US5276859A (en) | Accelerated token ring network | |
| JPH118643A (en) | Timing source changeover method and system therefor | |
| JPH10322379A (en) | Clock path changeover method | |
| JP3592261B2 (en) | Clock path switching method | |
| CN100549969C (en) | A kind of driving method of clock bus | |
| JP3070546B2 (en) | Alarm transfer circuit | |
| JPS61140239A (en) | Intelligent buffer device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080116 Termination date: 20170924 |