CN103427939A - XGMII-based channel deadlock automatic recovery method and chips - Google Patents
XGMII-based channel deadlock automatic recovery method and chips Download PDFInfo
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- CN103427939A CN103427939A CN2012101578522A CN201210157852A CN103427939A CN 103427939 A CN103427939 A CN 103427939A CN 2012101578522 A CN2012101578522 A CN 2012101578522A CN 201210157852 A CN201210157852 A CN 201210157852A CN 103427939 A CN103427939 A CN 103427939A
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Abstract
The invention discloses an XGMII-based channel deadlock automatic recovery method and chips. The method is applied to the data interaction process of two chips based on 10Gb XGMII communication and comprises the steps that when either one end of chips is detected to meet the reset triggering condition, reset of the chip is conducted, and the XGMII state of the end is set to be the synchronization loss state, wherein the reset triggering condition is that in a preset detection period, the number of times for the XGMII state of the opposite end being detected to be the synchronization loss state is larger than a preset upper limit value of the number of abnormal times, or the number of times of check errors for cyclic redundancy check being conducted on a data packet sent by the opposite end is larger than a preset upper limit value of the number of error times; handshaking is conduced on the two chips again after the two chips are reset. The XGMII-based channel deadlock automatic recovery method and the chips effectively prevent channel deadlock from influencing the overall function of the chips, and ensure the accuracy and stability of communication between the chips.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of passage deadlock autorecovery method and chip based on XGMII (10Gigbit Media Independent Interface, 10Gb media independent interface) interface.
Background technology
The high wideband transmit that employing is chip chamber based on XGMII provides desirable solution.Serdes (the SERializer/DESerializer of 10G bit rate, serializer/and change device) transmission unit meets XAUI (10Gigbit Attachment Unit Interface, the Ethernet Attachment Unit Interface of 10Gb per second) agreement, used 4 pairs of differential lines to realize the transmission of full duplex.
In actual applications, the channel transfer quality of Serdes is affected by two kinds of factors often: a, soft factor: the XAUI agreement itself guarantees in normal applied environment, allows the bit error rate of the 10-12 order of magnitude to exist; B, hard factor: be mainly chip chamber plate level Serdes cabling and be subject to extraneous forceful electric power saltus step, magnetic field switching etc. to disturb and accord with the factors impacts such as border interference (Inter-Symbol Interferences, referred to as ISI), signal jitter (jitter).Therefore, under the impact of above-mentioned factor, mistake or abnormal may appear in the physical channel of Serdes, so cause that packet defines that symbol is lost, command character information errors physical channel lock-out under extreme case even.
At present, numerous upper-layer protocols and transmitter adopt based on passing through CRC (Cyclical Redundancy Check, CRC) re-transmission of verification (retry) the mode data of loading error occurring again, it is little and be the problem that single 4x passage makes a mistake that this mode also can only solve the data error amount.When the error data amount is large and the duration is long, or, under the pattern of using a plurality of 4x path bindings, due to one of them 4x physical path lock-out, and cause whole transmission link deadlock, be difficult to be recovered by present existing mechanism.
Summary of the invention
The purpose of this invention is to provide a kind of passage deadlock autorecovery method and chip based on the XGMII interface, to solve due to the problem that is disturbed the transmission channel deadlock that situations such as causing packet error, loss and passage lock-out causes.
For addressing the above problem, the invention provides a kind of method of passage deadlock autorecovery, be applied in the data exchange process of two chips based on 10Gb media independent interface (XGMII) communication, comprising:
Any end in described two chips, detecting while meeting the reset trigger condition, carries out resetting of this chip, and the state of local terminal XGMII interface is set to the lock-out state; Wherein, described reset trigger condition comprises: in default sense cycle, the number of times that the number of times that the state that opposite end XGMII interface detected is the lock-out state has surpassed default abnormal number of times higher limit or the packet sent for opposite end carries out CRC (CRC) check errors has surpassed the default number of times higher limit of makeing mistakes;
Described two chips, after all being resetted, re-start and shake hands.
Further,
Describedly carry out resetting of this chip, specifically comprise:
Stop reception and the transmission of this chip data bag.
Further,
Stop the transmission of this chip data bag, specifically comprise:
Stop the transmission of packet at the tail place of the current packet sent.
Further,
The described reception that stops this chip data bag specifically comprises:
Be at present if judge state or the receive time-out state that receives the packet retransmitted, directly end receive path, stop the reception of packet; If judge the current state that is in normal reception packet, at the bag tail place of the current packet received, stop data receiver.
Further, described method also comprises:
In described two chips carry out the process of data interaction, when the end in described two chips is wanted to other end transmission packet, for data to be transmitted is responsible for assigning the transmission identifier unique, and carry out the data CRC check according to described transmission identifier, the first check results obtained is issued to the other end with described transmission identifier together with described data to be transmitted bag;
After the transmission identifier that receives the packet of sending opposite end, described packet and described the first check results, carry out CRC check according to described transmission identifier, and second check results that will obtain is compared with described the first check results received; As inconsistent as the two, judge the CRC check mistake.
Correspondingly, the present invention also provides a kind of chip, based on 10Gb media independent interface (XGMII) and another chip, carries out data interaction, comprising:
Whether detection module, meet the reset trigger condition for detection of current; Wherein, described reset trigger condition comprises: in default sense cycle, the number of times that the number of times that the state that opposite end XGMII interface detected is the lock-out state has surpassed default abnormal number of times higher limit or the packet sent for opposite end carries out CRC (CRC) check errors has surpassed the default number of times higher limit of makeing mistakes;
Reseting module, when detecting at described detection module that this chip is current meets described reset trigger condition, carry out resetting of this chip, and the state of local terminal XGMII interface is set to the lock-out state;
Handshake module, for after knowing that this chip and described another chip are all resetted, shaken hands with described another chip.
Further,
Described reseting module, for carrying out resetting of this chip, specifically comprises:
Described reseting module is for stopping reception and the transmission of this chip data bag.
Further,
Described reseting module, for stopping the transmission of this chip data bag, specifically comprises:
Described reseting module is for stopping the transmission of packet at the tail place of the current packet sent.
Further,
Described reseting module, for stopping the reception of this chip data bag, specifically comprises:
Described reseting module is used for, when the state of judging the packet that is at present the reception re-transmission or receive time-out state, directly ending receive path, stops the reception of packet; Also, for when judging the current state that is in normal reception packet, at the bag tail place of the current packet received, stop data receiver.
Further, described chip also comprises:
Sending module, for the process carrying out data interaction with described another chip, while wanting to other end transmission packet, for data to be transmitted is responsible for assigning the transmission identifier unique, and carry out the data CRC check according to described transmission identifier, the first check results obtained is issued to the other end with described transmission identifier together with described data to be transmitted bag;
Receiver module, after transmission identifier and described the first check results receiving the packet that described another chip sends, described packet, carry out CRC check according to described transmission identifier, and second check results that will obtain is compared with described the first check results received; As inconsistent as the two, judge the CRC check mistake.
The present invention can be applied in to flexibility and reliability in the environment based on communicating by letter between the XGMII interface chip, open the control informations such as register, channel status sense cycle register by pre-configured function, do not need the extra control logic of upper-layer protocol just can automatically solve the passage deadlock state and recover normal condition, effectively evaded due to the impact of passage deadlock on the chip allomeric function, guaranteed correctness and the stability of interchip communication.
The accompanying drawing explanation
The flow chart that Fig. 1 is a kind of solution transmission channel deadlock based on the XGMII interface in the embodiment of the present invention;
Fig. 2 is that the signal that solves the channel transfer deadlock in the embodiment of the present invention flows to schematic diagram.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, hereinafter in connection with accompanying drawing, embodiments of the invention are elaborated.It should be noted that, in the situation that do not conflict, the embodiment in the application and the feature in embodiment be combination in any mutually.
The present embodiment provides a kind of method of the solution transmission channel deadlock based on the XGMII interface.The method starts passage solution deadlock mechanism by the receiving terminal data detection testing mechanism of chip both sides, if the reception data detected continuously makes mistakes within the some time, while reaching the abnormal and expendable condition of channel transfer, receiver side Serdes physical path and link logic are carried out to local reset, evaded the impact of integral reset on upper system.Simultaneously, the transmitter side chip starts local local reset flow process according to the reset mode testing mechanism of current Serdes physical path, reinitializes and sets up physical path.
As shown in Figure 1, a kind of passage deadlock autorecovery method, be applied in the data exchange process of two chips based on the XGMII interface communication, comprising:
When the end in step 10, this two chip is wanted to the transmission of the other end in this two chip packet, for data to be transmitted is responsible for assigning transmission identifier (Identification unique, referred to as ID), and carry out the data CRC check according to this transmission ID, check results is issued to the above-mentioned other end with transmission ID together with above-mentioned data to be transmitted bag;
Step 20, receive the packet that send opposite end, all according to this packet received, corresponding transmission ID carries out local CRC check to the end in this two chip at every turn, and the check results obtained and the check results received are compared;
Any end in step 30, this two chip, after judging and meeting the reset trigger condition, confirms that transmission channel is abnormal, and this end starts passage solution deadlock mechanism--enter reset mode, local terminal Serdes physical transfer path is set to the lock-out state; Wherein, the reset trigger condition comprises: in default sense cycle, the number of times that the CRC check result is made mistakes has surpassed the default number of times higher limit or the number of times that opposite end Serdes physical transmission channel state is the lock-out state detected and surpassed default abnormal number of times higher limit of makeing mistakes;
Step 40, after two ends are all resetted, two chips re-start shakes hands and subsequent operation.
Wherein, in above-mentioned steps 30, reset mode duration can be arranged by the susceptibility to the time according to system, guarantees can active homing to fall invalid path transfer of data and get final product resetting time, can set longer resetting time in the insensitive situation of system, such as the ms level.
The level saltus step under the interference such as extraneous forceful electric power, magnetic field, occurs for likely being subject under the environment in chip chamber high speed Serdes transmission in said method, causes the loading error occurring deadlock; When perhaps a plurality of paths transmit, one of them or several passage physical transfer crash, whole transmission link is difficult to by the situation of the at present existing life-and-death lock of MECHANISM SOLUTION, and then a kind of device of the solution transmission channel deadlock based on the XGMII interface proposed, passage Deadlock Detection wherein and Restoration Mechanism have effectively been evaded the impact of chip chamber transmission Serdes physical path deadlock on the chip allomeric function, have guaranteed correctness and the stability of interchip communication.
As shown in Figure 2, the passage deadlock autorecovery method based on the XGMII interface comprises:
1, the first chip (originating end) is detecting while meeting the reset trigger condition, stop reception and the transmission processing of packet, start the local reset (comprising all physical paths and the link transmission state removed) of this chip, the state of local terminal XGMII interface is set to the lock-out state;
In the processing procedure of the transmission that stops packet, stop the transmission of packet at the tail place of the current packet sent, guarantee that data are complete cut-offs.In the process of the reception that stops packet, be at present if judge state or the receive time-out state that receives the packet retransmitted, directly end receive path, stop the reception of packet; Be in the state of normal reception packet if current, should stop data receiver at the bag tail place of the current packet received.
In addition, above-mentioned reset trigger condition refers to: in default sense cycle, the number of times that Serdes physical path state continuance remains the lock-out state detected and reach default abnormal number of times higher limit.
2, can affect the state of the XGMII interface on the second chip (responder) due to the state of the XGMII interface on the first chip, therefore, the second chip is detecting local XGMII interface after the lock-out state, stop reception and the transmission processing of packet, start the local reset of this chip;
In the processing procedure of the transmission that stops packet, stop the transmission of packet at the tail place of the current packet sent, guarantee that data are complete cut-offs.In the process of the reception that stops packet, be at present if judge state or the receive time-out state that receives the packet retransmitted, directly end receive path, stop the reception of packet; Be in the state of normal reception packet if current, guarantee to stop data receiver at the bag tail place of the current data that receiving.
3, after having resetted of the first chip and the second chip both sides, can in succession enter XGMII interface re-synchronization aligned condition, and the data initialization handshake mechanism of follow-up link layer, and again indicate the initialization completion status, proceed the transfer of data of the two.At the reseting stage of physical path, can produce corresponding feedback states and be used to refer to current state.
Correspondingly, in the present embodiment, a kind of chip, carry out data interaction based on XGMII and another chip, comprising:
Whether detection module, meet the reset trigger condition for detection of current; Wherein, described reset trigger condition comprises: in default sense cycle, the number of times that the number of times that the state that opposite end XGMII interface detected is the lock-out state has surpassed default abnormal number of times higher limit or the packet sent for opposite end carries out CRC (CRC) check errors has surpassed the default number of times higher limit of makeing mistakes;
Reseting module, when detecting at described detection module that this chip is current meets described reset trigger condition, carry out resetting of this chip, and the state of local terminal XGMII interface is set to the lock-out state;
Handshake module, for after knowing that this chip and described another chip are all resetted, shaken hands with described another chip.
Preferably,
Described reseting module, for carrying out resetting of this chip, specifically comprises:
Described reseting module is for stopping reception and the transmission of this chip data bag.
Preferably,
Described reseting module, for stopping the transmission of this chip data bag, specifically comprises:
Described reseting module is for stopping the transmission of packet at the tail place of the current packet sent.
Preferably,
Described reseting module, for stopping the reception of this chip data bag, specifically comprises:
Described reseting module is used for, when the state of judging the packet that is at present the reception re-transmission or receive time-out state, directly ending receive path, stops the reception of packet; Also, for when judging the current state that is in normal reception packet, at the bag tail place of the current packet received, stop data receiver.
Preferably, described chip also comprises:
Sending module, for the process carrying out data interaction with described another chip, while wanting to other end transmission packet, for data to be transmitted is responsible for assigning the transmission identifier unique, and carry out the data CRC check according to described transmission identifier, the first check results obtained is issued to the other end with described transmission identifier together with described data to be transmitted bag;
Receiver module, after transmission identifier and described the first check results receiving the packet that described another chip sends, described packet, carry out CRC check according to described transmission identifier, and second check results that will obtain is compared with described the first check results received; As inconsistent as the two, judge the CRC check mistake.
One of ordinary skill in the art will appreciate that all or part of step in said method can come the instruction related hardware to complete by program, described program can be stored in computer-readable recording medium, as read-only memory, disk or CD etc.Alternatively, all or part of step of above-described embodiment also can realize with one or more integrated circuits.Correspondingly, each the module/unit in above-described embodiment can adopt the form of hardware to realize, also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
The foregoing is only the preferred embodiments of the present invention, be not intended to limit protection scope of the present invention.According to summary of the invention of the present invention; also other various embodiments can be arranged; in the situation that do not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art are when making according to the present invention various corresponding changes and distortion; within the spirit and principles in the present invention all; any modification of doing, be equal to replacement, improvement etc., within protection scope of the present invention all should be included in.
Claims (10)
1. the method for a passage deadlock autorecovery, be applied in the data exchange process of two chips based on 10Gb media independent interface (XGMII) communication, comprising:
Any end in described two chips, detecting while meeting the reset trigger condition, carries out resetting of this chip, and the state of local terminal XGMII interface is set to the lock-out state; Wherein, described reset trigger condition comprises: in default sense cycle, the number of times that the number of times that the state that opposite end XGMII interface detected is the lock-out state has surpassed default abnormal number of times higher limit or the packet sent for opposite end carries out CRC (CRC) check errors has surpassed the default number of times higher limit of makeing mistakes;
Described two chips, after all being resetted, re-start and shake hands.
2. the method for claim 1 is characterized in that:
Describedly carry out resetting of this chip, specifically comprise:
Stop reception and the transmission of this chip data bag.
3. method as claimed in claim 2 is characterized in that:
Stop the transmission of this chip data bag, specifically comprise:
Stop the transmission of packet at the tail place of the current packet sent.
4. method as claimed in claim 2 or claim 3 is characterized in that:
The described reception that stops this chip data bag specifically comprises:
Be at present if judge state or the receive time-out state that receives the packet retransmitted, directly end receive path, stop the reception of packet; If judge the current state that is in normal reception packet, at the bag tail place of the current packet received, stop data receiver.
5. the method for claim 1, is characterized in that, also comprises:
In described two chips carry out the process of data interaction, when the end in described two chips is wanted to other end transmission packet, for data to be transmitted is responsible for assigning the transmission identifier unique, and carry out the data CRC check according to described transmission identifier, the first check results obtained is issued to the other end with described transmission identifier together with described data to be transmitted bag;
After the transmission identifier that receives the packet of sending opposite end, described packet and described the first check results, carry out CRC check according to described transmission identifier, and second check results that will obtain is compared with described the first check results received; As inconsistent as the two, judge the CRC check mistake.
6. a chip, carry out data interaction based on 10Gb media independent interface (XGMII) and another chip, comprising:
Whether detection module, meet the reset trigger condition for detection of current; Wherein, described reset trigger condition comprises: in default sense cycle, the number of times that the number of times that the state that opposite end XGMII interface detected is the lock-out state has surpassed default abnormal number of times higher limit or the packet sent for opposite end carries out CRC (CRC) check errors has surpassed the default number of times higher limit of makeing mistakes;
Reseting module, when detecting at described detection module that this chip is current meets described reset trigger condition, carry out resetting of this chip, and the state of local terminal XGMII interface is set to the lock-out state;
Handshake module, for after knowing that this chip and described another chip are all resetted, shaken hands with described another chip.
7. chip as claimed in claim 6 is characterized in that:
Described reseting module, for carrying out resetting of this chip, specifically comprises:
Described reseting module is for stopping reception and the transmission of this chip data bag.
8. chip as claimed in claim 7 is characterized in that:
Described reseting module, for stopping the transmission of this chip data bag, specifically comprises:
Described reseting module is for stopping the transmission of packet at the tail place of the current packet sent.
9. method as claimed in claim 7 or 8 is characterized in that:
Described reseting module, for stopping the reception of this chip data bag, specifically comprises:
Described reseting module is used for, when the state of judging the packet that is at present the reception re-transmission or receive time-out state, directly ending receive path, stops the reception of packet; Also, for when judging the current state that is in normal reception packet, at the bag tail place of the current packet received, stop data receiver.
10. chip as claimed in claim 6, is characterized in that, also comprises:
Sending module, for the process carrying out data interaction with described another chip, while wanting to other end transmission packet, for data to be transmitted is responsible for assigning the transmission identifier unique, and carry out the data CRC check according to described transmission identifier, the first check results obtained is issued to the other end with described transmission identifier together with described data to be transmitted bag;
Receiver module, after transmission identifier and described the first check results receiving the packet that described another chip sends, described packet, carry out CRC check according to described transmission identifier, and second check results that will obtain is compared with described the first check results received; As inconsistent as the two, judge the CRC check mistake.
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| US20070162823A1 (en) * | 2003-03-28 | 2007-07-12 | International Business Machines Corporation | System and method for optimizing iterative circuit for cyclic redundency check (crc) calculation |
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