CN100356545C - 在半导体器件的双镶嵌结构中降低接触电阻的方法和结构 - Google Patents
在半导体器件的双镶嵌结构中降低接触电阻的方法和结构 Download PDFInfo
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- CN100356545C CN100356545C CNB2004100666644A CN200410066664A CN100356545C CN 100356545 C CN100356545 C CN 100356545C CN B2004100666644 A CNB2004100666644 A CN B2004100666644A CN 200410066664 A CN200410066664 A CN 200410066664A CN 100356545 C CN100356545 C CN 100356545C
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- interlayer dielectric
- barrier layer
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- contact openings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2004100666644A CN100356545C (zh) | 2004-09-21 | 2004-09-21 | 在半导体器件的双镶嵌结构中降低接触电阻的方法和结构 |
US10/969,886 US8158520B2 (en) | 2004-09-21 | 2004-10-20 | Method of forming a via structure dual damascene structure for the manufacture of semiconductor integrated circuit devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2004100666644A CN100356545C (zh) | 2004-09-21 | 2004-09-21 | 在半导体器件的双镶嵌结构中降低接触电阻的方法和结构 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1753162A CN1753162A (zh) | 2006-03-29 |
CN100356545C true CN100356545C (zh) | 2007-12-19 |
Family
ID=36073074
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100666644A Active CN100356545C (zh) | 2004-09-21 | 2004-09-21 | 在半导体器件的双镶嵌结构中降低接触电阻的方法和结构 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8158520B2 (zh) |
CN (1) | CN100356545C (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100483235C (zh) * | 2006-12-04 | 2009-04-29 | 中芯国际集成电路制造(上海)有限公司 | 硅基液晶显示器单元及其形成方法 |
US8580687B2 (en) | 2010-09-30 | 2013-11-12 | Infineon Technologies Ag | Semiconductor structure and method for making same |
DE102011101035B4 (de) * | 2011-05-10 | 2014-07-10 | Infineon Technologies Ag | Ein Verfahren zum Herstelllen eines Anschlussgebiets an einer Seitenwand eines Halbleiterkörpers |
US8778758B2 (en) * | 2012-08-30 | 2014-07-15 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device and semiconductor device |
JP2016115698A (ja) * | 2014-12-11 | 2016-06-23 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
CN112752994B (zh) * | 2019-08-30 | 2022-08-02 | 京东方科技集团股份有限公司 | 背板、背光源、显示装置及背板的制造方法 |
CN114078749A (zh) | 2020-08-18 | 2022-02-22 | 长鑫存储技术有限公司 | 半导体结构及其形成方法 |
CN112201622A (zh) * | 2020-09-30 | 2021-01-08 | 长江存储科技有限责任公司 | 一种半导体器件及其制造方法 |
CN114725006A (zh) * | 2021-01-04 | 2022-07-08 | 长鑫存储技术有限公司 | 半导体结构及其形成方法 |
CN117525030A (zh) * | 2022-07-25 | 2024-02-06 | 长鑫存储技术有限公司 | 半导体结构及其制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1434509A (zh) * | 2002-01-22 | 2003-08-06 | 联华电子股份有限公司 | 双镶嵌金属内连线结构及其制作方法 |
US6767788B2 (en) * | 2001-06-12 | 2004-07-27 | Hynix Semiconductor Inc. | Semiconductor device having a metal insulator metal capacitor |
US6774031B2 (en) * | 2002-12-17 | 2004-08-10 | Texas Instruments Incorporated | Method of forming dual-damascene structure |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5904565A (en) * | 1997-07-17 | 1999-05-18 | Sharp Microelectronics Technology, Inc. | Low resistance contact between integrated circuit metal levels and method for same |
US6180516B1 (en) * | 1998-11-05 | 2001-01-30 | United Microelectronics Corp, | Method of fabricating a dual damascene structure |
TW587306B (en) * | 2001-03-02 | 2004-05-11 | Macronix Int Co Ltd | Manufacturing method of low-resistance dual damascene via |
US6753260B1 (en) * | 2001-10-05 | 2004-06-22 | Taiwan Semiconductor Manufacturing Company | Composite etching stop in semiconductor process integration |
US7088003B2 (en) * | 2004-02-19 | 2006-08-08 | International Business Machines Corporation | Structures and methods for integration of ultralow-k dielectrics with improved reliability |
US7244674B2 (en) * | 2004-04-27 | 2007-07-17 | Agency For Science Technology And Research | Process of forming a composite diffusion barrier in copper/organic low-k damascene technology |
US7285474B2 (en) * | 2004-09-16 | 2007-10-23 | International Business Machines Corporation | Air-gap insulated interconnections |
-
2004
- 2004-09-21 CN CNB2004100666644A patent/CN100356545C/zh active Active
- 2004-10-20 US US10/969,886 patent/US8158520B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6767788B2 (en) * | 2001-06-12 | 2004-07-27 | Hynix Semiconductor Inc. | Semiconductor device having a metal insulator metal capacitor |
CN1434509A (zh) * | 2002-01-22 | 2003-08-06 | 联华电子股份有限公司 | 双镶嵌金属内连线结构及其制作方法 |
US6774031B2 (en) * | 2002-12-17 | 2004-08-10 | Texas Instruments Incorporated | Method of forming dual-damascene structure |
Also Published As
Publication number | Publication date |
---|---|
US20060060971A1 (en) | 2006-03-23 |
CN1753162A (zh) | 2006-03-29 |
US8158520B2 (en) | 2012-04-17 |
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C06 | Publication | ||
PB01 | Publication | ||
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Semiconductor Manufacturing International (Beijing) Corporation Assignor: Semiconductor Manufacturing International (Shanghai) Corporation Contract fulfillment period: 2009.4.29 to 2014.4.29 contract change Contract record no.: 2009990000626 Denomination of invention: Method and structure for lowering contact electric resistance in double inlay structure of semiconductor device Granted publication date: 20071219 License type: Exclusive license Record date: 2009.6.5 |
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LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2009.4.29 TO 2014.4.29; CHANGE OF CONTRACT Name of requester: SEMICONDUCTOR MANUFACTURING INTERNATIONAL ( BEIJIN Effective date: 20090605 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111129 |
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C41 | Transfer of patent application or patent right or utility model | ||
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Effective date of registration: 20111129 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |