CN100353543C - 半导体组件及其制作方法 - Google Patents

半导体组件及其制作方法 Download PDF

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CN100353543C
CN100353543C CNB2004100808240A CN200410080824A CN100353543C CN 100353543 C CN100353543 C CN 100353543C CN B2004100808240 A CNB2004100808240 A CN B2004100808240A CN 200410080824 A CN200410080824 A CN 200410080824A CN 100353543 C CN100353543 C CN 100353543C
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余振华
曾鸿辉
胡正明
王昭雄
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明是揭示一种半导体组件及其制作方法。其利用一高温超导(HighTemperature Surperconductor，HTS)层与一典型的扩散层组合，其中该扩散层于介电材料与铜(或其它金属)导线之间。该高温超导体层材料包括钡铜氧以及一稀土元素，而该稀土元素以钇(yttrium)特别合适。如欲在导线上方形成其它半导体电路或组件，可于沉积一介电覆盖层前，沉积一高温超导材料覆盖层于导线上。本发明亦揭示将高温超导体填充于极微小的孔隙或沟槽内以形成联线。

Description

半导体组件及其制作方法
技术领域
本发明是有关于一种半导体组件及其制作方法，特别是有关于镶嵌工艺的扩散阻障层与覆盖层，以及一种于沟槽、介层孔或其它宽度小于300的孔隙中的高温超导体(High Temperature Superconductor，HTS)层的使用，其中钇钡铜氧是一适合的高温超导体。
背景技术
如业界人士所周知，在半导体制作与生产的目标在于不断地缩小组件尺寸及电路大小，但在此同时亦会造成于单一半导体组件上的电路及/或电路组件在数量上的增加，例如，晶体管、电容器...等。因此在持续且成功地将电路要件的大小减小时亦需将导线连接至组件与电路的大小减小。然而，当导线被设计得越来越小则互相连接的电阻会持续增加。
过去，常使用铝做为金属互联线并以二氧化硅做为介电层。然而，目前较新的制作技巧是以铜做为金属互联线者较佳而以低介电常数(lowdielectric constant，low-k)材料(包括无机或有机的)做为介电材料较佳。不意外地，此材料上的改变亦会造成工艺方法上的变动。特别是当在蚀刻铜的同时要不损坏介电材料并不容易，因此在形成金属互联线的技巧上经历了重要的改变。即铝互联线是于沉积一层铝后利用光致抗蚀剂，黄光及蚀刻以留下需要的铝线图案，而铜互联线的形成方式现通称为单镶嵌与双镶嵌工艺。该双镶嵌工艺几乎将蚀刻顺序颠倒，简单地说，一沟槽、介层孔、沟渠的孔隙先以切割、蚀刻或以其它方式形成于介层孔中然后再以金属填充之(例如：铜)。
不幸地，虽铜具有上述讨论的优点，却很容易扩散至用于半导体组件制造的介电材料中。半导体组件中的铜扩散至介电材料中会造成可靠度上的问题包括短路。因此，典型的方式是形成一扩散阻障层于做为导体及导线的铜及半导体组件的介电材料之间。典型的阻障层可由耐火金属及其氮化物所形成。先前技术的扩散层包括例如，钽(tantalum，Ta)，氮化钽(tantalumnitride，TaN)，钛(titanium)，氮化钛(titanium nitride，TiN)及上述金属和其它金属的各种组合。该扩散阻障层典型地形成于铜互联线的沟槽及介电孔的底部或侧壁以避免铜扩散至周围二氧化硅或其它介电材料中。另外，根据先前技术，可将适当材料的覆盖层(例如：氮化硅层)沉积于该完成结构上，其中该结构包括其它层或表面介电结构沉积前的导电区域以及介电层。
不幸地，传统扩散阻障材料对铜的黏着力差且会剥离因而产生不良的界面特性，例如会造成铜扩散至随后或介电材料覆盖层的途径。此路径亦会提供外界湿气或污染物扩散至铜并形成多孔的氧化铜。另外，在小的孔隙尺寸下(例如低于300)，太薄的传统阻障材料会产生高电阻。
Tanaka等人的美国专利6,541,136“超导体结构”中提到一种超导体结构，其中包括“稀土钡铜氧及特别是钇钡铜氧”。
Tanaka等人的美国专利5,629,268“制备一层状的超导体结构的工艺”中亦提到制备一层状的超导体结构其材料包括钡铜氧与稀土元素(包括钇)的结合。
Lopatin的美国专利6,518,648“电路互联线整合的超导体阻障层”中提供一整合电路，其中包括例如以钇钡铜氧做为阻障层的高温超导材料。
发明内容
有鉴于此，本发明的目的在于提供一种半导体组件及其制作方法，其包括一定义孔隙(例如：沟槽、介层孔及其它类似结构)于其中的第一介电层，接着填入铜并利用双镶嵌工艺以形成金属互联线，该互联线以介电质与非导体区域分隔。
在形成铜导线于孔隙或沟槽中之前，并根据一实施例，利用一或多种耐火金属(refractory metal)组成的阻障层为保护层顺应性地形成于该孔隙或沟槽的侧壁及底部，其中，该耐火金属包括钛、钽、钨(tungsten)及该些金属的氮化物。沉积一高温超导体层于阻障层上，其中该高温超导体层包括，一稀土钡铜氧，例如：钇钡铜氧。沉积一由一或多个下列金属组成的导电金属并覆盖该高温超导体层以做为导线或半导体组件互联线，其中该导电金属，其包括，铜、铜合金、金、银及该些金属的化合物。
根据其它实施例，该导线将被一高温超导体层覆盖再覆盖上其它介电层。
附图说明
图1-图2、图3A、图3B及图4-图6是绘示出本发明实施例的半导体组件的形成方法步骤与最后结构示意图。
符号说明：
10、10A、10B～基底层；12～第一介电材料层；14A，14B，14C～沟槽；16～介层孔；18～保护阻障层；20～高温超导体层(HTS)；22～钽层；28A、28B、28C～导电材料区域；30～覆盖层；32～图案化硬屏蔽；34～第一介电材料层。
具体实施方式
为让本发明的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附图式，作详细说明如下：
以下配合图1一图2、图3A、图3B及图4-图6说明本发明实施例的半导体组件的形成方法步骤与结果装置。首先，请参照图1，其是显示一典型半导体结构，其中包括由一或多层(例如：10A及10B)形成的基底10。覆盖一第一层12介电材料于基底10上，藉由该介电材料以定义出一或多个孔隙(hole)、沟槽(trench)或介层孔(via hole)。如图1所示，形成三个沟槽14A、14B、14C并准备以镶嵌工艺填入铜或其它导电金属。值得注意的是该沟槽14B亦包括一延伸并穿过基底层10B的介层孔16，此乃现有技术常用的方法。另外，本发明使用的基底10可为一简单的单层硅芯片或代表一或多层含有其它金属互联线的不同的半导体组件，因此该基底可被广泛的解释。例如典型的基底10会包括与介电层12相似的介电层。介电层12可为任何适合的介电材料，但在高速集成电路，为降低电容值以提升电路速度，则以低介电常数的介电材料较理想，例如，介电常数小于2.5的多孔性介电材料(porousdielectric)，但不限制于多孔性介电材料，以自旋涂布技术形成的有机低介电常数的介电材料，或以化学气相沉积技术形成的无机低介电常数的介电材料均可。
利用现有的镶嵌工艺技术及使用铜做为互联线层虽可解决许多问题但亦同时产生其它问题。例如，以铜为导电或互联线层材料，若无采取其它预防扩散的步骤，则会导致铜扩散至周围的介电质区域。因此，如图2所示，形成一保护阻障层18，利用该层可停止或阻障该铜离子由铜互联线导线扩散至周围的非导线部分或区域12及基底10。该薄层保护阻障层18可由现有技术中常见的多种阻障层材料里选出，其适合的材料包括例如钽(tantalum)、氮化钽(tantalum nitride)、钛(titanium)、氮化钛(titanium nitride)、钨(tungsten)、氮化钨(tungsten nitride)及上述或其它金属的不同结合物，并利用该些不同的现有技术的任一适合方式沉积形成此阻障层18。
接着，如图3A所示，于阻障层18上形成或以沉积方式顺应性覆盖一高温超导体(High Temperature Superconductor，HTS)层20。该高温超导体层20的典型厚度约10-500。如图3A所示，该高温超导体层20是第二种类型(type 2)的金属化合物及合金的超导体，例如将氧化铜(cupper oxides)于高临界温度(Tc)与周遭压力下超导的使其转变成超导态。例如：Hg0.8Tl0.2Ba2Ca2Cu3O8.33的临界温度为138K。此外，该多层结构放大图如图3B所示。
虽其它非钇的稀土元素(例如：钐(samarium)、钕(neodymium)、铒(erbium)、钆(gadolinium)、镱(ytterbium)、镝(dysprosium)、钬(holmium)、镏(lutetium))亦可与钡铜氧结合形成超导体，但利用钇与钡铜氧结合(例如：YBa2Cu3O7+or Y2Ba4Cu7O15)形成的超导体特别有效。除上述之外相信仍有其它合金分子式适合与稀土元素结合。其它合金例如：稀土钌铜氧(rutheniumoxocuprate)像是钌锶铜氧(RuSrxCuyOz)，其分子式中的x为1.55-2.45、y为1.55-2.45而z为7.55-8.45。
接着，于该高温超导体层(High Temperature Superconductor，HTS)20的材料上典型地覆盖上一钽层。因此，扩散阻障层更包括高温超导体层(HTS)，例如“稀土”钡铜氧以类似三明治被夹于以第一阻障层例如钽或富含钽的氮化钽层为底层18及以第二阻障层的钽层为顶层22之间。
沉积一导电金属(例如：铜)于沟槽、介层孔及/或孔硅中以形成半导体导线及/或互联线28A、28B及28C如图4所示。上述的现有的金属氮化物扩散阻障层对于铜的黏着力不佳，且若使用小尺寸的孔隙则容易造成高电阻，而本发明的高温超导体层20具有良好的黏着力以及在孔隙、沟槽或介层孔的宽度低于300时仍能提供低电阻。
如图5所示，在许多应用上均需要提供一覆盖层30于导电材料区域28A、28B、28C上。虽然该覆盖层30可加在所有应用上，但在此若仍有其它层形成于该半导体组件的导电导线28A、28B、28C上，则该覆盖层将变得特别重要。不幸的，如上述说明，该典型现有的金属氮化物层无法与铜互联线有较佳的黏着将会使后续的研磨受到影响。而且，因为铜与现有技术的金属氮化物保护覆盖层间不佳的黏着品质，将导致严重的可靠度问题产生。例如，该金属氮化物层常会剥离而造成铜与第二介电层之间无阻障层的问题。在本技术中，若缺少氮化金属阻障层时，则铜离子会扩散至第二介电层而产生电性短路。
因此，再参考图5，根据本发明该覆盖层30以高温超导体覆盖层取代典型的金属氮化物覆盖层。该高温超导体覆盖层30以相同于上述高温超导体层20的方法形成，并以典型的方式沉积约10-500的厚度。该高温超导体覆盖层30典型地以图案化硬屏蔽32例如一抗反射涂层(ARC)覆盖于导线28A、28B、28C上亦如图5所示。在后续工艺中可视需要硬屏蔽或反射涂层(ARC32)与否来决定是否移除。
在图案化的高温超导体覆盖层30形成并覆盖于该导电导线28A、28B、28C上之后，沉积一第二层介电质34如图6所示，藉此制作半导体组件的其它层。该第二层介电材料34可为任何适合介电材料，包括介电常数小于2.5的多孔性介电材料(porous dielectric)。
更进一步，当孔隙或沟槽的尺寸小于300时，可直接将高温超导体填充于孔隙或沟槽内，以作为集成电路的联线，以大幅降低电阻，提升电路速度。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求范围所界定者为准。

Claims (18)

1.一种半导体组件，包括：
一介电层，其中定义有至少一孔隙；
一第一阻障层，形成于该至少一孔隙之中；
一高温超导层，形成于该至少一孔隙中的该第一阻障层上；
一第二阻障层，形成于该高温超导层上；以及
一导电材料，填充于该介电层的该孔隙中。
2.根据权利要求1所述的半导体组件，其中该第一阻障层，沿着该至少一孔隙的底部及侧壁形成于介电层上。
3.根据权利要求1所述的半导体组件，其中该第一阻障层包含氮化钽层或钽层，而该第二阻障层包含钽层。
4.根据权利要求1所述的半导体组件，其中该高温超导材料是择自由稀土铜氧及稀土元素与钡铜氧的组合所组成的族群。
5.根据权利要求4所述的半导体组件，其中该稀土元素与钡铜氧的组合是钇钡铜氧。
6.根据权利要求1所述的半导体组件，其中该高温超导体层为一稀土钌铜氧。
7.根据权利要求6所述的半导体组件，其中该稀土钌铜氧以分子式RuSrxCuyOz定义，其x为1.55-2.45，y为1.55-2.45，z为7.55-8.45。
8.根据权利要求1所述的半导体组件，更包括一覆盖层于该导电材料上。
9.根据权利要求8所述的半导体组件，其中该覆盖层是一高温超导覆盖层。
10.根据权利要求8所述的半导体组件，更包括于该介电层与该覆盖层上的另一介电层。
11.一种半导体组件的制作方法，该步骤包括：
形成一介电层于一基底上；
定义至少一孔隙于该介电层中；
形成一第一阻障层于该至少一孔隙之中；
形成一高温超导层于该第一阻障层上；
形成一第二阻障层于该高温超导层上；以及沉积一导电材料于该介电层中的该至少一孔隙内。
12.根据权利要求11所述的半导体组件的制作方法，其中该第一阻障层，沿着该至少一孔隙的底部及侧壁形成于介电层上。
13.根据权利要求11所述的半导体组件的制作方法，其中该第一阻障层包括钽层或氧化钽层，而该第二阻障层包括钽层。
14.根据权利要求11所述的半导体组件的制作方法，其中该高温超导材料是择自由稀土铜氧及稀土元素与钡铜氧的组合所组成的族群。
15.根据权利要求14所述的半导体组件的制作方法，其中该稀土元素与钡铜氧的组合是钇钡铜氧。
16.根据权利要求11所述的半导体组件的制作方法，其中该高温超导体层为一稀土钌铜氧。
17.根据权利要求16所述的半导体组件的制作方法，其中该稀土钌铜氧以分子式RuSrxCuyOz定义其x为1.55-2.45，y为1.55-2.45，z为7.55-8.45。
18.根据权利要求11所述的半导体组件的制作方法更包括形成一覆盖层于该导电材料上的步骤，其中该导电材料沉积于该定义于介电层中的孔隙内。
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