CN100346679C - Circuit board, electronic equipment using the circuit board and method of sorting circuit board - Google Patents
Circuit board, electronic equipment using the circuit board and method of sorting circuit board Download PDFInfo
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- CN100346679C CN100346679C CNB018200664A CN01820066A CN100346679C CN 100346679 C CN100346679 C CN 100346679C CN B018200664 A CNB018200664 A CN B018200664A CN 01820066 A CN01820066 A CN 01820066A CN 100346679 C CN100346679 C CN 100346679C
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
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- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
In a circuit board having lands 2 each of which has through hole 4 through which lead 3 of an electrical part is inserted, the lead 3 and the land 2 being mounted in the circuit board by using lead-free solder 6, solder resist 5 which protects circuit board 1 is formed to cover at least a part of land circumference end portion 2a, whereby land exfoliation is suppressed. In the land circumference end portion 2a, the solder resist 5 is formed to cover at least the part that influence of the thermal shrinkage of the solder is large. The solder resist 5 is formed to cover an end portion at the side connected with the circuit that is formed on a circuit board, in land circumference end part, or to cover an end portion at the opposite side to the end portion.
Description
Technical field
The present invention relates to circuit substrate, use the electronic equipment of this circuit substrate and the method for separating of circuit substrate, particularly relate to the use Pb-free solder and the circuit substrate of insert type electronic component is installed, is used the electronic equipment of this circuit substrate and the method for separating of circuit substrate.
Background technology
Below utilize Figure 15 to Figure 18, existing circuit board structure is elaborated.Figure 15 is the perspective view that electronic component is installed in the solder joint on the circuit substrate, and Figure 16 is the cutaway view of the b-b ' of Figure 15.
As shown in figure 16, existing circuit substrate 11 is Copper Foil to be carried out heating and pressurizing handle, then it is attached on the insulation board and forms copper-clad base plate, above-mentioned insulation board is with epoxy resin, phenolic resins etc. infiltrate paper base material and glass baseplate, form in the polyester fiber base material etc., after forming copper-clad base plate, on the assigned position of this substrate, form through hole, on the side of through hole, add after the catalyst, carrying out substrate by electroless plating copper electroplates, carry out electrolytic copper plating thereon then and form electric conductor, the copper film on this electric conductor and copper-clad base plate surface is engaged and form through hole 4.Then, by the conducting film that constitutes by copper on the corrosion copper-clad base plate surface, thereby form pad 2.
At last, solder resist 5 printings are coated on pad 2 part in addition of carrying out soldering, make it not adhere to plumber's solder 12, form circuit substrate 11 by sensitization then.At this moment, solder resist 5 is born the effect that the circuit 7 beyond 3 the pad 2 that goes between has been installed in protection.
As shown in figure 15, printing solder resist 5 makes its area than pad 2 big, and makes solder resist 5 not cover pad 2 on circuit substrate 11.This is because use in the soldering of maximum slicker solder eutectic solders (Sn63wt%, all the other are Pb) in utilizing the electronic equipment soldered joint, if solder resist 5 covering pads 2 then can hinder the leg 12a of plumber's solder 12 to form.
In addition, in recent years along with densification is installed,, in the scope that can guarantee the bottom line weld strength, try one's best to such an extent that formation is littler for pad 2.Therefore, the electronic equipment that uses above-mentioned existing circuit substrate 11 to make engages the effect of the thermal expansion mismatch (mismatch) that produces owing to having stress mitigation slicker solder eutectic solder with impurity, so do not have problem on reliability.
But along with the raising of environmental consciousness, the environmental pollution that lead causes becomes distinct issues in recent years, carries out to the research of the conversion of lead-free Pb-free solder.This Pb-free solder is main component with tin, constitute by copper, silver, zinc, bismuth, indium, antimony, nickel, germanium etc., with the present maximum slicker solder eutectic solder (Sn63wt% of use in electronic equipment scolding tin engages, all the other are Pb, below be designated as Pb-63Sn) compare, have metallic characters such as the big and elongation of the hot strength, creep strength of metal is little.Therefore, be difficult for causing that by lead welding tin stress relaxes, and compare for 183 ℃ that the melt temperature of Pb-free solder can be brought up to 190～230 ℃ in soldering portion with the melt temperature of slicker solder eutectic solder.
Main Pb-free solder as present use, tin zinc series scolding tin is arranged, and (the eutectic composition Sn-9.0wt%Zn with tin zinc is the center, by changing the amount of zinc, or add other yuan and usually improve characteristic, be referred to as tin zinc series scolding tin, its typical example is Sn-8.0Zn-3.0Bi), (the eutectic composition Sn-0.7wt%Cu with tin copper is the center to tin copper series scolding tin, by changing the amount of copper, or add other yuan and usually improve characteristic, be referred to as tin copper series scolding tin, its typical example is Sn-0.7Cu-0.3Ag) and the serial scolding tin of tin silver (the eutectic composition Sn-3.5wt%Ag with Xi Yin is the center, by changing the amount of silver, or add other yuan and usually improve characteristic, being referred to as the serial scolding tin of tin silver, its typical example is Sn-3.0Ag-0.5cu, Sn-3.5Ag-0.75Cu) etc.
Above-mentioned tin zinc series scolding tin has the advantage of melting point low (about 190 ℃), but because so must carry out soldering in inert atmosphere or vacuum, there is the problem of operation difference in easily oxidation.
In addition, there are not the problem of oxidation in tin copper series scolding tin and Xi Yin series scolding tin, but the shortcoming that exists melt temperature height (about 230 ℃), pad easily to peel off of tin copper series scolding tin.
On the other hand, be 125～140 ℃ as the vitrification point of the epoxy series material of circuit substrate main material, when using tin-lead solder, it is big that the solidification shrinkage temperature difference becomes, thus the stress that acts on the junction surface of Pb-free solder becomes big.According to the metallic character of this Pb-free solder,, when utilizing Pb-free solder 6 to carry out plug-in mounting, be easy to generate pad and peel off phenomenon, and this does not almost take place when utilizing tin-lead solder 12 when using existing circuit substrate 11.
Below utilize accompanying drawing, the example that the generation pad is peeled off is elaborated.Figure 17 is the cutaway view of the generation state of representing that schematically pad is peeled off.Figure 18 be illustrated in the generation confirmed in the confirmatory experiment pad peel off the figure of phenomenon, be the cross sectional photograph of the B part (about counter-rotating) of Figure 17.
As shown in figure 17, when using existing circuit substrate 11 to carry out the soldering of Pb-free solder 6, peel off between pad 2 and the circuit substrate 11, pad 2 becomes the state that floats.At this moment, the circuit 7 that connects with pad 2 is pulled up in advance, thereby is subjected to excessive stress.Under this state, if be subjected to thermal stress repeatedly, then circuit 7 breaks easily, shown in the cross sectional photograph of Figure 18.
Like this, have following problem, promptly pad is peeled off the reliability of electronic equipment is significantly descended.In addition, use and the available circuit substrate 11 that pad peels off to have taken place carry out the manufacturing of electronic equipment, the reliability of electronic equipment is significantly descended.
The present invention is exactly in view of the above problems and proposes, even its main purpose provides a kind of use Pb-free solder, do not take place yet pad peel off with leg peel off, circuit substrate that reliability is high.
In addition, another object of the present invention provides and uses foregoing circuit substrate, electronic equipment that reliability is high.
Summary of the invention
To achieve these goals, circuit substrate of the present invention, at least has wiring on the surface and the back side, be provided with the through hole of conductive component insertion with electronic component at surperficial and the back side, the pad that this through hole is covered by conducting film and this conducting film prolongs on the circuit substrate face and form, thereby Pb-free solder is filled in this through hole above-mentioned conductive component is installed on above-mentioned conducting film and the above-mentioned pad, and on the above-mentioned pad of being located at the surface and the back side, form the leg of above-mentioned Pb-free solder, it is characterized in that, has at least a portion that covers above-mentioned pad peripheral end and the solder resist that forms, on at least a portion zone of above-mentioned solder resist, the radius of above-mentioned leg is below the opening radius of above-mentioned solder resist.
In the present invention, preferably within the above-mentioned pad peripheral end, be formed at the foregoing circuit substrate on the circuit end that is connected a side be coated with above-mentioned solder resist.In addition, preferably within the above-mentioned pad peripheral end, be formed at the foregoing circuit substrate on the circuit end that connects the relative side of a side be coated with above-mentioned solder resist.Preferred above-mentioned solder resist covers forming than the end of the pad end of length direction and a side relative with it of a plurality of Long Circle pads of being provided with continuously.The shape of above-mentioned pad can be distortion of for example circle, Long Circle, polygonal, cross or star etc.In addition, preferably at above-mentioned pad be formed on the connecting portion between the circuit on the foregoing circuit substrate and form auxiliary pad.In addition, above-mentioned Pb-free solder can be enumerated tin zinc series scolding tin, zinc-silver series scolding tin or tin copper series scolding tin etc.
Electronic equipment of the present invention is the equipment with Pb-free solder inserting electronic components on the circuit substrate of above-mentioned formation.
Circuit substrate of the present invention is to have wiring on the surface and the back side, is provided with the circuit substrate of the pad that the through hole of conductive component with insertion electronic component and this through hole covered by conducting film, promptly is applicable to two sides substrate or multilager base plate etc.
In addition, so-called Pb-free solder is also contained in and also contains the lead that exists as impurity under the prerequisite that does not change character sometimes.
Therefore, circuit substrate of the present invention forms by (so long as pad formation method gets final product) formed pads 2 such as etch on the surface of circuit substrate 1 as shown in Figure 1.Be formed for the through hole of the lead-in wire (as conductive component) 3 of inserting electronic components at the central part of this pad 2, electroplate on surface to through hole, and engage with the pad 2 on circuit substrate 1 surface, form through hole 4, in order not apply Pb-free solder 6 on the part beyond the pad 2 that in the end carries out soldering, and printing applies solder resist 5, is shaped by sensitization then.
At this moment, as shown in Figure 2, make solder resist 5 cover a whole circumference or the part of pad end 2a, and to make the radius of leg be below the solder resist opening radius, thereby can prevent that Pb-free solder 6 infiltrations are diffused into pad end 2a, prevent that leg 6a is formed into pad end 2a.
Because leg 6a is in the inboard formation of pad end 2a, when so Pb-free solder 6 shrinks along the tension force of the oblique upper of leg 6a and according to and leg form relation active force that produce, that repel the thermal contraction of circuit substrate 1 between the angle be not act on the most weak pad end 2a of circuit substrate bonding strength on, but act on pad 2 inboards bigger with the bonding strength of circuit substrate 1, so pad 2 is not easy to peel off.In addition, owing to pad end 2a is not fixed by Pb-free solder 6, so pad 2 shrinks along with the thermal expansions of circuit substrate 1 easily and moves.
In addition, utilize and to satisfy the circuit substrate of following formula (1), be subject to because under the situation that the Pb-free solder 6 of the influence of the high coefficient of thermal expansion mismatch that produces of melt temperature is made, can suppress also to cause that the pad that circuit 7 breaks peels off in use.Thus, can obtain such effect, even promptly use Pb-free solder, also can the very high electronic equipment of fabrication reliability.
Description of drawings
Fig. 1 is the perspective view of first execution mode of expression circuit substrate of the present invention.
Fig. 2 is the cutaway view of first execution mode of expression circuit substrate of the present invention.
Fig. 3 is the plane graph of expression second embodiment of the invention.
Fig. 4 is the plane graph of expression third embodiment of the invention.
Fig. 5 is the plane graph of expression four embodiment of the invention.
Fig. 6 is the plane graph of the another kind structure of expression four embodiment of the invention.
Fig. 7 is the plane graph of the another kind structure of expression four embodiment of the invention.
Fig. 8 is the plane graph of the another kind structure of expression four embodiment of the invention.
Fig. 9 is the plane graph of the another kind structure of expression four embodiment of the invention.
Figure 10 is the experimental data of expression based on table 1, the cross sectional photograph of existing configuration example generation manufacturing defect.
Figure 11 is the partial enlarged drawing of Figure 10.
Figure 12 is the cross sectional photograph of expression based on the effect of the first embodiment of the invention of the experimental data of table 1.
Figure 13 is the figure that the pad of expression fifth embodiment of the invention is peeled off the defective incidence.
Figure 14 is the result of calculation of expression table 2 and the graph of a relation of peeling off incidence based on the pad of experimental data.
Figure 15 is the perspective view of the configuration example of the existing circuit substrate of expression.
Figure 16 is the cutaway view of the configuration example of the existing circuit substrate of expression.
Figure 17 is the cutaway view that manufacturing defect takes place when using the configuration example of existing circuit substrate in expression.
Figure 18 is the cross sectional photograph that manufacturing defect takes place when using existing configuration example in expression.
Embodiment
Following with reference to accompanying drawing, the preferred implementation of circuit substrate of the present invention is elaborated.
(first execution mode)
At first with reference to Fig. 1, Fig. 2 and Figure 10～Figure 12, the circuit substrate of first execution mode of the present invention is described.Fig. 1 is the perspective view that electronic component is installed in the state on the circuit substrate of the present invention, and Fig. 2 is the cutaway view of the a-a ' of Fig. 1.Figure 10～Figure 12 is the figure that is used to illustrate the effect of present embodiment.Because the manufacture method of circuit substrate is same as the prior art, so omit its explanation.
As depicted in figs. 1 and 2, solder resist 5 is covered on the 2a of pad end, the radius of leg 6a is less than the opening radius of solder resist 5.
Adopt above-mentioned formation, leg 6a is in the inboard formation of pad end 2a, when Pb-free solder 6 shrinks along leg 6a obliquely tension force and according to and leg form relation active force that produce, that repel the thermal contraction of circuit substrate 1 between the angle be not act on the most weak pad end 2a of circuit substrate bonding strength on, but act on pad 2 inboards bigger with the bonding strength of circuit substrate 1, so pad 2 is not easy to peel off.In addition, owing to pad end 2a is not fixed by Pb-free solder 6, so pad 2 shrinks along with the thermal expansions of circuit substrate 1 easily and moves.Thus, can suppress because Pb-free solder 6 and multiple pad is peeled off.
Below effect when the circuit substrate 1 that uses present embodiment made electronic equipment verify.Utilize its result's (table 1) to be specifically described.
Table 1
| Cycle-index | Existing circuit substrate | The circuit substrate of |
| 0 time | ○ | ○ |
| 100 times | ○ | ○ |
| 200 times | ×1※ | ○ |
| 300 times | ○ | ○ |
| 400 times | ×3，△1 | ○ |
| 500 times | ×1 | ○ |
Zero: resistance value is no abnormal
△: resistance value rises
*: broken string (off state)
For the circuit substrate 1 of existing circuit substrate 11 and present embodiment, under identical condition, use Pb-free solder (Sn-3.0Ag-0.5Cu) to carry out soldering.Then, carry out thermal stress cycle test (25 ℃ of (5 minutes) of 40 ℃ of (30 minutes) 125 ℃ of (30 minutes), several 10 pieces of samples, 16 places/piece) repeatedly, relatively the cycle-index when broken string.The decision method of broken string is, electronic component is installed on the figure that makes inter-pad short circuits, measures its resistance then, when resistance is infinitely great, just is judged to be broken string.
Checking is the result show, in the circuit substrate 11 that existing Pb-free solder is used, through broken string occurring after 200 circulations, the broken string place increases then, but broken string does not appear in the circuit substrate 1 of present embodiment after through 500 circulations.
Figure 10 shows the cross sectional photograph of the circuit substrate 11 shown in the ※ mark in the table 1 (200 circulation broken string places (the C part of Figure 17)).As shown in figure 10, pad 2 floats bigger from circuit substrate 11, and the circuit 7 that is attached thereto also floats bigger.In addition, from amplifying expression arrow D Figure 11 partly as can be seen, the boundary member generation moderate finite deformation of pad end 2a and circuit 7 is up to broken string.That is, peel off because pad takes place, circuit 7 breaks, thereby the reliability of electronic equipment is significantly descended.
Figure 12 shows the cross sectional photograph (the A part of Fig. 2) of the circuit substrate 1 of the present embodiment of carrying out confirmatory experiment under same condition.As can be seen from Figure 12, in the circuit substrate 1 of present embodiment, pad 2 does not take place unusual, thereby the formation that can confirm present embodiment is peeled off effectively suppressing pad.
Therefore, applying repeatedly under the situation of thermal stress circulation, by the cycle-index when the broken string relatively as can be known, the useful life of available circuit substrate 11 when broken string of taking place easily that pad peels off is little than the circuit substrate 1 of present embodiment obviously.In addition, in addition, circuit substrate of present embodiment 1 and the electronic equipment that uses this circuit substrate 1 to make can suppress because Pb-free solder and multiple pad is peeled off phenomenon, thereby can the high electronic equipment of fabrication reliability.
The opening scope of solder resist gets final product than pad diameter is little, make between pad 2 and the solder resist 5 overlapping, this overlapping lower limit makes solder resist 5 cover pad end 2a in principle, but the width of the lap between preferred pad 2 and the solder resist 5 is more than the 0.01mm, to be preferably more than the 0.02mm.Its reason is, the lower limit of overlapping width is by the coupling surplus (margin) in when exposure and the decision of the relation between the stress, only considering that leg forms under the situation of the stress that produces, overlapping 0.01mm is above to be peeled off with regard to not producing pad, if the matching precision when considering exposure, then above overlapping of 0.02mm is difficult to take place manufacturing defect.
On the other hand, the upper limit of overlapping width is to form leg, and the solder resist opening scope scope bigger than through-hole diameter.
(second execution mode)
Following with reference to Fig. 3, the circuit substrate of second embodiment of the invention is described.Fig. 3 is the plane graph of the example of expression when solder resist 5 being covered on the Long Circle pad 8 of continuous adjacent with the unit of classifying as.
Be provided with the solder resist 5 of narrow slit shape mouth in Fig. 3, this solder resist 5 is across the central portion of the length direction of a plurality of Long Circle pads 8 that dispose continuously.On each Long Circle pad 8, solder resist 5 does not have near the pad end 8a of the Width of the central portion of overlay length direction, and only covering the pad end 8b and the part on the other side of thermal contraction length direction influence, that be connected with circuit 7 more be subject to Pb-free solder 6, other parts do not form solder resist.As shown in Figure 3, a plurality of Long Circle pads 8 are exposed in the solder resist peristome 5a and form solder resist 5.
Adopt above-mentioned formation, can prevent that Pb-free solder 6 from soaking into the pad end 8b of Long Circle pad 8 length directions, thereby realize and the roughly the same purpose of above-mentioned first execution mode.This second execution mode is little to the spacing of the lead-in wire of electronic component, it is effective especially to be difficult to situation that solder resist is printed on therebetween.
(the 3rd execution mode)
Following with reference to Fig. 4, the circuit substrate of third embodiment of the invention is described.
As shown in Figure 4, in bond pad shapes is under the situation of the circle shown in first execution mode, only form on the pad end of circuit 7 one sides and the pad on the other side end and cover solder resist 5 in circular pad 2, can prevent that thus circuit 7 from floating from circuit substrate 1, thereby obtain the effect identical with first execution mode.
In addition, only on the pad end of circular pad 2 formation circuit 7 one sides, cover solder resist 5, can prevent that also circuit 7 from floating from circuit substrate 1, thereby obtain the effect identical with first execution mode.In addition, only cover solder resist 5 on the pad end relative with the pad end of circular pad 2 formation circuit 7 one sides, the pad that also can be suppressed at the generation of pad end is peeled off.
(the 4th execution mode)
Following with reference to Fig. 5～Fig. 9, the circuit substrate of four embodiment of the invention is described.The plane graph of Fig. 5 example that to be expression make up the special-shaped pad 9 and circular solder resist 5 openings of star, Fig. 6, Fig. 7 are the plane graphs that expression is provided with the formation of auxiliary pad 10, Fig. 8, Fig. 9 make up criss-cross special-shaped pad and circular solder resist 5 openings, and the plane graph of the example that octagonal special-shaped pad and circular solder resist 5 openings are made up.
In the combination of above-mentioned any bond pad shapes, solder resist 5 opening shapes, all make solder resist 5 cover the end 9a of special-shaped pad 9, can prevent that thus Pb-free solder from soaking into special-shaped pad end 9a, thereby realize purpose of the present invention.
In addition, in the above-described embodiment, the situation that auxiliary pad 10 is set for the junction surface between pad 2 and circuit 7 too.Fig. 6, Fig. 7 show such example.As Fig. 6, shown in Figure 7, under situation with auxiliary pad 10, make the center-aligned of the center of pad 2 of inserting electronic components lead-in wire 3 and solder resist 5 peristomes and cover solder resist 5, thus, can not only realize purpose of the present invention, can also obtain such effect, promptly pad 2 and being connected more of circuit 7 be strengthened by auxiliary pad 10.The shape of auxiliary pad 10 may be thought of as semicircle (Fig. 6), water droplet (tear drop) shape (Fig. 7) etc., can be any above-mentioned shape, also can be other shape.
(the 5th execution mode)
Following with reference to Figure 13, the circuit substrate of fifth embodiment of the invention is described.The 5th execution mode uses the high insulated substrate of vitrification point.Following coefficient of linear expansion is the coefficient of linear expansion of expression substrate thickness direction.
(vitrification point is 125～140 ℃, is being 50～70ppm less than the coefficient of linear expansion under the temperature of vitrification point (α 1), is being on 200～350ppm) the circuit substrate in the coefficient of linear expansion more than the vitrification point (α 2) the electronic component soldering to have been used the insulated substrate that existing epoxy resin makes in 250 ℃/5 seconds/atmosphere with the Pb-free solder (Sn-3.0Ag-0.5Cu) of tin silver series.
Relative therewith; with the Pb-free solder (Sn-3.0Ag-0.5Cu) of tin silver series in 250 ℃/5 seconds/atmosphere with electronic component soldering on the substrate of the high vitrification point of low-thermal-expansion (Figure 13); aforesaid substrate be to use constitute by the epoxy resin of having removed halogen, Hitachi change into system MCL-RO-67G (vitrification point be 150 ℃, less than the coefficient of linear expansion under the temperature of vitrification point (α 1) for 38ppm, coefficient of linear expansion (α 2) more than vitrification point for 185ppm, below brief note is 150 ℃, 38ppm, 185ppm) circuit substrate.
Above-mentioned two kinds of circuit substrates are carried out thermal stress cycle test (25 ℃ of (5 minutes) of 40 ℃ of (30 minutes) 125 ℃ of (30 minutes), several 10 pieces of samples, 16 places/piece) 500 times repeatedly, confirm its reliability.Consequently; in the circuit substrate of the substrate that uses existing epoxy resin to make pad having taken place peels off; and in the circuit substrate of the MCL-RO-67G (150 ℃, 38ppm, 185ppm) that changes into system as the high vitrification point substrate of low-thermal-expansion, Hitachi; as shown in figure 13, pad not taking place peels off.
From above result as can be seen, if vitrification point is more than the setting, and the above coefficient of linear expansion of vitrification point is below the setting, pad then can not take place peel off.
In addition; experimental data is shown particularly, can understands that from this experimental data the vitrification point Tg, substrate thickness direction of circuit substrate when carrying out soldering with Pb-free solder are in coefficient of linear expansion α under the temperature conditions littler than vitrification point and the relation between the fusion point Tm of the coefficient of linear expansion α 2 under the above condition of vitrification point, scolding tin.
Following formula (2) shows the substrate expansion rate L that the vitrification point Tg of circuit substrate, substrate thickness direction are calculated as parameter at fusion point Tm, the normal temperature Ts (being generally 25 ℃) of the coefficient of linear expansion α under the temperature conditions littler than vitrification point 1 and the coefficient of linear expansion α 2 under the above condition of vitrification point, scolding tin.
Substrate expansion rate L shown in the formula (2) is in the process that makes the circuit substrate cooling of having carried out soldering, scolding tin after molten condition begins to solidify by fusion point, the thermal expansion rate of change of the circuit substrate when recovering normal temperature up to the scolding tin junction surface.
{ α 1 (Tg-Ts)+α 2 (tm-Tg) }/10
4=L ... formula (2)
L: substrate expansion rate (%)
Tg: vitrification point (℃)
α 1: the coefficient of linear expansion under the temperature conditions littler than vitrification point (ppm)
α 2: the coefficient of linear expansion under the condition more than the vitrification point (ppm)
Tm: the fusion point of scolding tin (solidifying when being equivalent to cool off starting point) (℃)
Ts: normal temperature (temperature that the scolding tin junction surface returns to normal) (℃)
The inventor is empirical tests, if the coefficient of thermal expansion L that is obtained by formula (2) is below the coefficient of thermal expansion L1 of regulation, pad then can take place peel off.
Utilize formula (2), the substrate expansion rate L of 5 kinds of circuit substrates (embodiment 1～3, comparative example 1,2) of carrying out soldering with Sn-Ag-Cu scolding tin is calculated, its result of calculation is illustrated in the table 2.Wherein, the substrate of embodiment 2 is identical with the MCL-RO-67G that above-mentioned Hitachi changes into system.
Table 2
| The embodiment | Embodiment | 1 | | | Comparative example 1 | Comparative example 2 |
| Tg | 152 | 141 | 150 | 133 | 129 | |
| α1 | 25 | 36 | 57 | 56 | 54 | |
| α2 | 144 | 205 | 264 | 289 | 286 | |
| L | 1.30 | 2.04 | 2.56 | 3.12 | 3.16 | |
| Pad is peeled off defective incidence (%) | 0 | 0 | 0 | 86 | 61 |
Pad is peeled off defective incidence experiment condition
Through-hole diameter: 1.0mm
Pad diameter: 1.6mm
Installing component: DIP-IC (Ni-Pd plating)
Soldering condition: in the 250 ℃/5 seconds/atmosphere
In table 2, be to be that 25 ℃, Tm calculate under 220 ℃ the condition suitable with the Sn-Ag-Cu Pb-free solder at Ts.
Figure 14 is the result of calculation according to table 2, substrate expansion rate L with utilize experimental data and the pad that obtains is peeled off the chart of incidence.As can be seen from Figure 14, in substrate expansion rate L is circuit substrate below 2.56% pad not taking place peels off.That is, establish L1=2.56%, select coefficient of thermal expansion L, pad then can not take place peel off for the following circuit substrate of this value.
Thus; be that 220 ℃ Sn-Ag-Cu scolding tin is when carrying out soldering for example when using fusion point Tm; at vitrification point Tg is under 141 ℃ of coefficient of linear expansion α 2 situations for the substrate of the embodiment 1～3 below the 264ppm of asking more than the vitrification point; if the substrate expansion rate L that calculates according to vitrification point and coefficient of linear expansion is below 2.56%, then can suppresses pad and peel off.
Formula (3) is according to The above results, the calculating formula that formula (2) is put in order again.Formula (3) is made as 25 ℃ with normal temperature.
L={ α 1 (Tg-25)+α 2 (Tm-Tg) }/10
4≤ 2.56 ... formula (3)
L: substrate expansion rate (%)
Tg: vitrification point (℃)
α 1: the coefficient of linear expansion under the temperature conditions littler than vitrification point (ppm)
α 2: the coefficient of linear expansion under the condition more than the vitrification point (ppm)
Tm: the fusion point of scolding tin (solidifying when being equivalent to cool off starting point) (℃)
Utilize formula (3),, then can predict the generation that pad is peeled off if know vitrification point Tg, the coefficient of linear expansion (α 1, α 2) of circuit substrate, the fusion point TM of scolding tin.
In addition, utilize formula (3), can easily select to have the inhibition pad and peel off the circuit substrate of effect, peel off thereby can suppress pad.
Even change the kind of scolding tin, by displacement Tm, also can carry out same calculating, the fusion point of employed scolding tin is low more, and substrate expansion rate L is just many more in the kind of the circuit substrate below 2.56.
For example; if with existing Sn-37Pb scolding tin (fusion point: 183 ℃) calculate with Sn-Ag-Cu scolding tin easily take place the insulated substrate that epoxy resin that pad is peeled off, existing makes (1125～140 ℃ of vitrification points, at the coefficient of linear expansion under the temperature conditions littler (α 1) 50～70ppm, the substrate expansion rate L of coefficient of linear expansion (α 2) 200～350ppm) under the condition more than the vitrification point than vitrification point; be about 1.9%; so satisfy formula (3), can think that then pad can not take place to be peeled off in existing soldering.
Use the foregoing circuit substrate to make electronic equipment, can make cyclic thermal stres intensity height, long service life and the high electronic equipment of reliability.As above-mentioned electronic equipment, for example printer, facsimile machine, LCD monitor, personal computer, mainframe computer (comprising server, supercomputer), switch, transmission equipment, base station apparatus etc. are arranged.
The invention is not restricted to the respective embodiments described above, in the scope of technological thought of the present invention, can suitably change the respective embodiments described above.
As mentioned above, adopt the present invention, can prevent that the Pb-free solder infiltration is diffused into the pad end, thereby prevent that leg is formed up to the pad end.By making leg be formed on inboard, pad end, thereby can be suppressed at the thermal expansion shrinkage stress of the Pb-free solder of pad end generation, make pad be easy to shrink and move, can suppress owing to Pb-free solder and the circuit substrate that the pad of pilosity is peeled off thereby can provide along with the circuit substrate thermal expansion.
In addition, the electronic equipment that uses this circuit substrate manufacturing is in the thermal stress circulation experiment that carries out repeatedly, and its useful life is more much higher than the electronic equipment that uses existing circuit substrate.Thus, the use Pb-free solder also can the very high electronic equipment of fabrication reliability.
In addition, utilize formula (1), can easily select to have pad and peel off the circuit substrate that suppresses effect, thereby can suppress the generation that pad is peeled off.
Claims (8)
1. circuit substrate, at least has wiring on the surface and the back side, the pad that through hole, this through hole that is provided with the conductive component insertion with electronic component at surface and the back side covered by conducting film and this conducting film prolongs on the circuit substrate face and form, thereby Pb-free solder is filled in this through hole above-mentioned conductive component is installed on above-mentioned conducting film and the above-mentioned pad, and be located at the leg that forms above-mentioned Pb-free solder on the above-mentioned pad at the surface and the back side, it is characterized in that
Have at least a portion that covers above-mentioned pad peripheral end and the solder resist that forms, at least a portion zone of above-mentioned solder resist, the radius of above-mentioned leg is less than the opening radius of above-mentioned solder resist.
2. circuit substrate according to claim 1 is characterized in that, within the above-mentioned pad peripheral end, be formed at the foregoing circuit substrate on the circuit end that is connected a side be coated with above-mentioned solder resist.
3. circuit substrate according to claim 1 is characterized in that, within the above-mentioned pad peripheral end, be formed at the foregoing circuit substrate on the circuit end that connects the relative side of a side be coated with above-mentioned solder resist.
4. circuit substrate according to claim 2 is characterized in that, within the above-mentioned pad peripheral end, be formed at the foregoing circuit substrate on the circuit end that connects the relative side of a side be coated with above-mentioned solder resist.
5. circuit substrate according to claim 1 is characterized in that, above-mentioned solder resist covers the end of the pad end of length direction of a plurality of Long Circle pads that are provided with continuously and a side relative with it and forms.
6. circuit substrate according to claim 1 is characterized in that, any in the distortion that is shaped as circle, Long Circle, polygonal, cross or star of above-mentioned pad.
7. circuit substrate according to claim 1 is characterized in that, at above-mentioned pad be formed on the connecting portion between the circuit on the foregoing circuit substrate and form auxiliary pad.
8. an electronic equipment is characterized in that, use with the Pb-free solder inserting electronic components, the described circuit substrate of claim 1.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000374174 | 2000-12-08 | ||
| JP374174/2000 | 2000-12-08 | ||
| JP2001343511A JP3686861B2 (en) | 2000-12-08 | 2001-11-08 | Circuit board and electronic device using the same |
| JP343511/2001 | 2001-11-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1480014A CN1480014A (en) | 2004-03-03 |
| CN100346679C true CN100346679C (en) | 2007-10-31 |
Family
ID=26605493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB018200664A Expired - Fee Related CN100346679C (en) | 2000-12-08 | 2001-11-27 | Circuit board, electronic equipment using the circuit board and method of sorting circuit board |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP3686861B2 (en) |
| CN (1) | CN100346679C (en) |
| TW (1) | TW511403B (en) |
| WO (1) | WO2002047449A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002246734A (en) * | 2001-02-19 | 2002-08-30 | Sony Corp | Substrate and electronic equipment having substrate |
| CN100362640C (en) * | 2004-06-04 | 2008-01-16 | 英业达股份有限公司 | Method for preventing semiconductor assembly pin welding from shorting circuit |
| JP4841865B2 (en) * | 2005-06-01 | 2011-12-21 | 株式会社バッファロー | Printed circuit board |
| JP2007266510A (en) * | 2006-03-29 | 2007-10-11 | Sanyo Electric Co Ltd | Printed wiring board and electric apparatus |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5544367Y2 (en) * | 1976-11-04 | 1980-10-17 | ||
| JPH028080U (en) * | 1988-06-27 | 1990-01-18 | ||
| GB2247361A (en) * | 1990-08-10 | 1992-02-26 | Nippon Cmk Kk | Conductive through-holes in printed wiring boards |
| JPH05343602A (en) * | 1992-06-11 | 1993-12-24 | Hitachi Ltd | High density mounted semiconductor device and semiconductor module using the same |
| JPH08181424A (en) * | 1994-12-26 | 1996-07-12 | Sony Corp | Printed board and its soldering method |
| JPH11145607A (en) * | 1997-11-11 | 1999-05-28 | Murata Mach Ltd | Method of forming soldered resist film on printed circuit board and printed circuit board manufactured there by |
| JPH11145605A (en) * | 1997-11-10 | 1999-05-28 | Matsushita Electric Ind Co Ltd | Printed wiring board |
| JPH11251728A (en) * | 1998-02-27 | 1999-09-17 | Fuji Photo Film Co Ltd | Printed board and method for coating cream solder |
| JP2000332401A (en) * | 1999-05-18 | 2000-11-30 | Tamura Seisakusho Co Ltd | Method of cooling soldered product, soldered product cooling apparatus and soldering apparatus |
-
2001
- 2001-11-08 JP JP2001343511A patent/JP3686861B2/en not_active Expired - Fee Related
- 2001-11-27 CN CNB018200664A patent/CN100346679C/en not_active Expired - Fee Related
- 2001-11-27 WO PCT/JP2001/010312 patent/WO2002047449A1/en active Application Filing
- 2001-11-29 TW TW90129517A patent/TW511403B/en not_active IP Right Cessation
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5544367Y2 (en) * | 1976-11-04 | 1980-10-17 | ||
| JPH028080U (en) * | 1988-06-27 | 1990-01-18 | ||
| GB2247361A (en) * | 1990-08-10 | 1992-02-26 | Nippon Cmk Kk | Conductive through-holes in printed wiring boards |
| JPH05343602A (en) * | 1992-06-11 | 1993-12-24 | Hitachi Ltd | High density mounted semiconductor device and semiconductor module using the same |
| JPH08181424A (en) * | 1994-12-26 | 1996-07-12 | Sony Corp | Printed board and its soldering method |
| JPH11145605A (en) * | 1997-11-10 | 1999-05-28 | Matsushita Electric Ind Co Ltd | Printed wiring board |
| JPH11145607A (en) * | 1997-11-11 | 1999-05-28 | Murata Mach Ltd | Method of forming soldered resist film on printed circuit board and printed circuit board manufactured there by |
| JPH11251728A (en) * | 1998-02-27 | 1999-09-17 | Fuji Photo Film Co Ltd | Printed board and method for coating cream solder |
| JP2000332401A (en) * | 1999-05-18 | 2000-11-30 | Tamura Seisakusho Co Ltd | Method of cooling soldered product, soldered product cooling apparatus and soldering apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002237674A (en) | 2002-08-23 |
| CN1480014A (en) | 2004-03-03 |
| WO2002047449A1 (en) | 2002-06-13 |
| JP3686861B2 (en) | 2005-08-24 |
| TW511403B (en) | 2002-11-21 |
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Granted publication date: 20071031 Termination date: 20151127 |