CH629057A5 - Method for designing electrically conductive layers for producing printed circuits, as well as a multi-layer base material for carrying out the method - Google Patents

Method for designing electrically conductive layers for producing printed circuits, as well as a multi-layer base material for carrying out the method Download PDF

Info

Publication number
CH629057A5
CH629057A5 CH837078A CH837078A CH629057A5 CH 629057 A5 CH629057 A5 CH 629057A5 CH 837078 A CH837078 A CH 837078A CH 837078 A CH837078 A CH 837078A CH 629057 A5 CH629057 A5 CH 629057A5
Authority
CH
Switzerland
Prior art keywords
grid
base material
electrically conductive
circuit
conductive layers
Prior art date
Application number
CH837078A
Other languages
German (de)
English (en)
Inventor
Hans Juergen Reuter
Original Assignee
Contraves Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Contraves Ag filed Critical Contraves Ag
Priority to CH837078A priority Critical patent/CH629057A5/de
Priority to DE19792929050 priority patent/DE2929050A1/de
Priority to DE19797920552U priority patent/DE7920552U1/de
Priority to BE0/196406A priority patent/BE877834A/fr
Priority to LU81560A priority patent/LU81560A1/de
Priority to IT24906/79A priority patent/IT1122413B/it
Publication of CH629057A5 publication Critical patent/CH629057A5/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09681—Mesh conductors, e.g. as a ground plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09945—Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
CH837078A 1978-08-07 1978-08-07 Method for designing electrically conductive layers for producing printed circuits, as well as a multi-layer base material for carrying out the method CH629057A5 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CH837078A CH629057A5 (en) 1978-08-07 1978-08-07 Method for designing electrically conductive layers for producing printed circuits, as well as a multi-layer base material for carrying out the method
DE19792929050 DE2929050A1 (de) 1978-08-07 1979-07-18 Mehrschichtige gedruckte leiterplatte und verfahren zu ihrer auslegung
DE19797920552U DE7920552U1 (de) 1978-08-07 1979-07-18 Mehrschichtige gedruckte leiterplatte
BE0/196406A BE877834A (fr) 1978-08-07 1979-07-23 Plaquette de circuits imprimes a plusieurs couches et procede pour la conception de cette plaquette
LU81560A LU81560A1 (de) 1978-08-07 1979-07-27 Mehrschichtige gedruckte leiterplatte und verfahren zu ihrer auslegung
IT24906/79A IT1122413B (it) 1978-08-07 1979-08-03 Circuito stampato a piu'strati e procedimento per la sua progettazione

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH837078A CH629057A5 (en) 1978-08-07 1978-08-07 Method for designing electrically conductive layers for producing printed circuits, as well as a multi-layer base material for carrying out the method

Publications (1)

Publication Number Publication Date
CH629057A5 true CH629057A5 (en) 1982-03-31

Family

ID=4339271

Family Applications (1)

Application Number Title Priority Date Filing Date
CH837078A CH629057A5 (en) 1978-08-07 1978-08-07 Method for designing electrically conductive layers for producing printed circuits, as well as a multi-layer base material for carrying out the method

Country Status (5)

Country Link
BE (1) BE877834A (fr)
CH (1) CH629057A5 (fr)
DE (2) DE7920552U1 (fr)
IT (1) IT1122413B (fr)
LU (1) LU81560A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3020196C2 (de) * 1980-05-28 1982-05-06 Ruwel-Werke Spezialfabrik für Leiterplatten GmbH, 4170 Geldern Mehrebenen-Leiterplatte und Verfahren zu deren Herstellung
FR2512315A1 (fr) * 1981-09-02 1983-03-04 Rouge Francois Ebauche de circuit electrique multicouche et procede de fabrication de circuits multicouches en comportant application
SE462071B (sv) * 1985-12-23 1990-04-30 Perstorp Ab Moensterkort
US5165166A (en) * 1987-09-29 1992-11-24 Microelectronics And Computer Technology Corporation Method of making a customizable circuitry
AU610249B2 (en) * 1987-09-29 1991-05-16 Microelectronics And Computer Technology Corporation Customizable circuitry
JP4496922B2 (ja) 2004-11-02 2010-07-07 株式会社ジェイテクト 電気配線板及びこれの製造方法

Also Published As

Publication number Publication date
IT1122413B (it) 1986-04-23
DE2929050A1 (de) 1980-02-21
BE877834A (fr) 1979-11-16
LU81560A1 (de) 1979-10-31
IT7924906A0 (it) 1979-08-03
DE7920552U1 (de) 1979-10-11

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Legal Events

Date Code Title Description
PL Patent ceased