CH508278A - Integrierte Schaltung und Verfahren zu ihrer Herstellung - Google Patents
Integrierte Schaltung und Verfahren zu ihrer HerstellungInfo
- Publication number
- CH508278A CH508278A CH1324069A CH1324069A CH508278A CH 508278 A CH508278 A CH 508278A CH 1324069 A CH1324069 A CH 1324069A CH 1324069 A CH1324069 A CH 1324069A CH 508278 A CH508278 A CH 508278A
- Authority
- CH
- Switzerland
- Prior art keywords
- making
- integrated circuit
- integrated
- circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/858—Complementary IGFETs, e.g. CMOS comprising a P-type well but not an N-type well
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/30—Isolation regions comprising PN junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W15/00—Highly-doped buried regions of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W15/00—Highly-doped buried regions of integrated devices
- H10W15/01—Manufacture or treatment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/037—Diffusion-deposition
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/098—Layer conversion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/151—Simultaneous diffusion
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB41476/68A GB1280022A (en) | 1968-08-30 | 1968-08-30 | Improvements in and relating to semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CH508278A true CH508278A (de) | 1971-05-31 |
Family
ID=10419864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CH1324069A CH508278A (de) | 1968-08-30 | 1969-09-01 | Integrierte Schaltung und Verfahren zu ihrer Herstellung |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US3748545A (de) |
| BE (1) | BE738309A (de) |
| CA (1) | CA993119A (de) |
| CH (1) | CH508278A (de) |
| DE (1) | DE1944793C3 (de) |
| FR (1) | FR2017125A1 (de) |
| GB (1) | GB1280022A (de) |
| NL (1) | NL6913300A (de) |
| SE (1) | SE362540B (de) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3885998A (en) * | 1969-12-05 | 1975-05-27 | Siemens Ag | Method for the simultaneous formation of semiconductor components with individually tailored isolation regions |
| US4032372A (en) * | 1971-04-28 | 1977-06-28 | International Business Machines Corporation | Epitaxial outdiffusion technique for integrated bipolar and field effect transistors |
| IT947674B (it) * | 1971-04-28 | 1973-05-30 | Ibm | Tecnica di diffusione epitassiale per la fabbricazione di transisto ri bipolari e transistori fet |
| US3993512A (en) * | 1971-11-22 | 1976-11-23 | U.S. Philips Corporation | Method of manufacturing an integrated circuit utilizing outdiffusion and multiple layer epitaxy |
| GB1361303A (en) * | 1972-02-11 | 1974-07-24 | Ferranti Ltd | Manufacture of semiconductor devices |
| US3945032A (en) * | 1972-05-30 | 1976-03-16 | Ferranti Limited | Semiconductor integrated circuit device having a conductive plane and a diffused network of conductive tracks |
| US3881179A (en) * | 1972-08-23 | 1975-04-29 | Motorola Inc | Zener diode structure having three terminals |
| US3793088A (en) * | 1972-11-15 | 1974-02-19 | Bell Telephone Labor Inc | Compatible pnp and npn devices in an integrated circuit |
| US3841918A (en) * | 1972-12-01 | 1974-10-15 | Bell Telephone Labor Inc | Method of integrated circuit fabrication |
| US3992232A (en) * | 1973-08-06 | 1976-11-16 | Hitachi, Ltd. | Method of manufacturing semiconductor device having oxide isolation structure and guard ring |
| US3920481A (en) * | 1974-06-03 | 1975-11-18 | Fairchild Camera Instr Co | Process for fabricating insulated gate field effect transistor structure |
| JPS51135385A (en) * | 1975-03-06 | 1976-11-24 | Texas Instruments Inc | Method of producing semiconductor device |
| US4028717A (en) * | 1975-09-22 | 1977-06-07 | Ibm Corporation | Field effect transistor having improved threshold stability |
| US4203126A (en) * | 1975-11-13 | 1980-05-13 | Siliconix, Inc. | CMOS structure and method utilizing retarded electric field for minimum latch-up |
| US4205330A (en) * | 1977-04-01 | 1980-05-27 | National Semiconductor Corporation | Method of manufacturing a low voltage n-channel MOSFET device |
| US4168997A (en) * | 1978-10-10 | 1979-09-25 | National Semiconductor Corporation | Method for making integrated circuit transistors with isolation and substrate connected collectors utilizing simultaneous outdiffusion to convert an epitaxial layer |
| JPS5574059U (de) * | 1978-11-15 | 1980-05-21 | ||
| JPS58225663A (ja) * | 1982-06-23 | 1983-12-27 | Toshiba Corp | 半導体装置の製造方法 |
| US5529939A (en) * | 1986-09-26 | 1996-06-25 | Analog Devices, Incorporated | Method of making an integrated circuit with complementary isolated bipolar transistors |
| JP2575876B2 (ja) * | 1989-05-17 | 1997-01-29 | 株式会社東芝 | 半導体装置 |
| US5227654A (en) * | 1989-05-17 | 1993-07-13 | Kabushiki Kaisha Toshiba | Semiconductor device with improved collector structure |
| JP3017809B2 (ja) * | 1991-01-09 | 2000-03-13 | 株式会社東芝 | アナログ・デジタル混載半導体集積回路装置 |
| WO2022204913A1 (en) * | 2021-03-30 | 2022-10-06 | Innoscience (Suzhou) Technology Co., Ltd. | Iii nitride semiconductor devices on patterned substrates |
| US12324179B2 (en) * | 2021-12-16 | 2025-06-03 | Wolfspeed, Inc. | Group III-nitride high-electron mobility transistors with a buried metallic conductive material layer and process for making the same |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1050805A (de) * | 1964-06-23 | 1900-01-01 | ||
| US3386865A (en) * | 1965-05-10 | 1968-06-04 | Ibm | Process of making planar semiconductor devices isolated by encapsulating oxide filled channels |
| US3404450A (en) * | 1966-01-26 | 1968-10-08 | Westinghouse Electric Corp | Method of fabricating an integrated circuit structure including unipolar transistor and bipolar transistor portions |
| US3481801A (en) * | 1966-10-10 | 1969-12-02 | Frances Hugle | Isolation technique for integrated circuits |
| US3474308A (en) * | 1966-12-13 | 1969-10-21 | Texas Instruments Inc | Monolithic circuits having matched complementary transistors,sub-epitaxial and surface resistors,and n and p channel field effect transistors |
| US3447046A (en) * | 1967-05-31 | 1969-05-27 | Westinghouse Electric Corp | Integrated complementary mos type transistor structure and method of making same |
-
1968
- 1968-08-30 GB GB41476/68A patent/GB1280022A/en not_active Expired
-
1969
- 1969-08-27 SE SE11885/69A patent/SE362540B/xx unknown
- 1969-08-28 US US00853714A patent/US3748545A/en not_active Expired - Lifetime
- 1969-09-01 FR FR6929831A patent/FR2017125A1/fr active Pending
- 1969-09-01 CH CH1324069A patent/CH508278A/de not_active IP Right Cessation
- 1969-09-01 BE BE738309D patent/BE738309A/xx unknown
- 1969-09-01 NL NL6913300A patent/NL6913300A/xx unknown
- 1969-09-01 DE DE1944793A patent/DE1944793C3/de not_active Expired
- 1969-09-02 CA CA060,866A patent/CA993119A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CA993119A (en) | 1976-07-13 |
| US3748545A (en) | 1973-07-24 |
| DE1944793B2 (de) | 1977-10-06 |
| DE1944793C3 (de) | 1979-06-07 |
| BE738309A (de) | 1970-03-02 |
| FR2017125A1 (de) | 1970-05-15 |
| NL6913300A (de) | 1970-03-03 |
| SE362540B (de) | 1973-12-10 |
| DE1944793A1 (de) | 1970-05-06 |
| GB1280022A (en) | 1972-07-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PL | Patent ceased |