CH506132A - Dringlichkeitsstufen-Erkennungs-Einrichtung für eine Datenverarbeitungsanlage - Google Patents

Dringlichkeitsstufen-Erkennungs-Einrichtung für eine Datenverarbeitungsanlage

Info

Publication number
CH506132A
CH506132A CH736467A CH736467A CH506132A CH 506132 A CH506132 A CH 506132A CH 736467 A CH736467 A CH 736467A CH 736467 A CH736467 A CH 736467A CH 506132 A CH506132 A CH 506132A
Authority
CH
Switzerland
Prior art keywords
data processing
processing system
recognition device
urgency level
level recognition
Prior art date
Application number
CH736467A
Other languages
English (en)
Inventor
William John
Joseph Goss Gary
John Porcelli Ernest
Bertrand Banan Frederick
Charles Mcgee Russell
Leslie Rakoczi Laszlo
Original Assignee
Gen Electric
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Electric filed Critical Gen Electric
Publication of CH506132A publication Critical patent/CH506132A/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor
CH736467A 1966-05-25 1967-05-25 Dringlichkeitsstufen-Erkennungs-Einrichtung für eine Datenverarbeitungsanlage CH506132A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US55298166A 1966-05-25 1966-05-25

Publications (1)

Publication Number Publication Date
CH506132A true CH506132A (de) 1971-04-15

Family

ID=24207624

Family Applications (7)

Application Number Title Priority Date Filing Date
CH737067A CH495016A (de) 1966-05-25 1967-05-25 Datenverarbeitungsanlage
CH736767A CH489847A (de) 1966-05-25 1967-05-25 Steuerwerk für eine digitale Rechenanlage
CH736667A CH495014A (de) 1966-05-25 1967-05-25 Datenverarbeitungsanlage
CH736967A CH493886A (de) 1966-05-25 1967-05-25 Datenverarbeitungsanlage
CH736867A CH505430A (de) 1966-05-25 1967-05-25 Datenverarbeitungsanlage
CH736567A CH486738A (de) 1966-05-25 1967-05-25 Datenverarbeitungsanlage
CH736467A CH506132A (de) 1966-05-25 1967-05-25 Dringlichkeitsstufen-Erkennungs-Einrichtung für eine Datenverarbeitungsanlage

Family Applications Before (6)

Application Number Title Priority Date Filing Date
CH737067A CH495016A (de) 1966-05-25 1967-05-25 Datenverarbeitungsanlage
CH736767A CH489847A (de) 1966-05-25 1967-05-25 Steuerwerk für eine digitale Rechenanlage
CH736667A CH495014A (de) 1966-05-25 1967-05-25 Datenverarbeitungsanlage
CH736967A CH493886A (de) 1966-05-25 1967-05-25 Datenverarbeitungsanlage
CH736867A CH505430A (de) 1966-05-25 1967-05-25 Datenverarbeitungsanlage
CH736567A CH486738A (de) 1966-05-25 1967-05-25 Datenverarbeitungsanlage

Country Status (6)

Country Link
JP (3) JPS4510707B1 (de)
CH (7) CH495016A (de)
DE (8) DE1549423A1 (de)
FR (6) FR1564477A (de)
GB (10) GB1167945A (de)
SE (5) SE329279B (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3675209A (en) * 1970-02-06 1972-07-04 Burroughs Corp Autonomous multiple-path input/output control system
FR2289003A1 (fr) * 1974-02-01 1976-05-21 Honeywell Bull Soc Ind Dispositif de commande de transferts de donnees entre la memoire centrale et les unites peripheriques d'un systeme informatique
US4209839A (en) * 1978-06-16 1980-06-24 International Business Machines Corporation Shared synchronous memory multiprocessing arrangement
US4306287A (en) * 1979-08-31 1981-12-15 Bell Telephone Laboratories, Incorporated Special address generation arrangement
GB2092341B (en) * 1981-02-02 1984-09-12 Picker Int Ltd Computer peripheral selection
GB2147126B (en) * 1983-09-29 1987-01-07 Memory Ireland Limited Improvements in and relating to computers
EP0690399A3 (de) * 1994-06-30 1997-05-02 Tandem Computers Inc System für fernbediente finanzielle Transaktionen

Also Published As

Publication number Publication date
GB1150489A (en) 1969-04-30
DE1298318B (de) 1969-06-26
GB1174069A (en) 1969-12-10
DE1549428B2 (de) 1973-02-01
DE1549431A1 (de) 1971-04-01
CH486738A (de) 1970-02-28
GB1167945A (en) 1969-10-22
GB1154516A (en) 1969-06-11
GB1173356A (en) 1969-12-10
CH505430A (de) 1971-03-31
DE1549428A1 (de) 1972-08-10
DE1549423A1 (de) 1971-02-18
FR1545595A (fr) 1968-11-15
JPS5323059B1 (de) 1978-07-12
FR1564478A (de) 1969-04-25
GB1137784A (en) 1968-12-27
GB1164000A (en) 1969-09-10
FR1528181A (fr) 1968-06-07
DE1549422A1 (de) 1971-01-07
DE1549424A1 (de) 1971-03-04
SE329287B (de) 1970-10-05
JPS4510707B1 (de) 1970-04-17
GB1186414A (en) 1970-04-02
DE1549426A1 (de) 1971-01-21
SE340192B (de) 1971-11-08
FR1564477A (de) 1969-04-25
DE1549429A1 (de) 1971-01-21
GB1142290A (en) 1969-02-05
CH489847A (de) 1970-04-30
CH495016A (de) 1970-08-15
CH493886A (de) 1970-07-15
JPS45236860B1 (de) 1970-08-10
FR1564476A (de) 1969-04-25
GB1177109A (en) 1970-01-07
CH495014A (de) 1970-08-15
DE1549422B2 (de) 1977-05-05
SE329279B (de) 1970-10-05
SE329282B (de) 1970-10-05
FR1545594A (fr) 1968-11-15
SE329517B (de) 1970-10-12

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Legal Events

Date Code Title Description
PL Patent ceased