CH451325A - Verfahren zum Herstellen integrierter Schaltungen mit durch eingebettete Trennfugen aus dielektrischem Material gegenseitig elektrisch isolierten Schaltelementen - Google Patents
Verfahren zum Herstellen integrierter Schaltungen mit durch eingebettete Trennfugen aus dielektrischem Material gegenseitig elektrisch isolierten SchaltelementenInfo
- Publication number
- CH451325A CH451325A CH38167A CH38167A CH451325A CH 451325 A CH451325 A CH 451325A CH 38167 A CH38167 A CH 38167A CH 38167 A CH38167 A CH 38167A CH 451325 A CH451325 A CH 451325A
- Authority
- CH
- Switzerland
- Prior art keywords
- production
- dielectric material
- integrated circuits
- switching elements
- electrically insulated
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/928—Front and rear surface processing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Weting (AREA)
- Electrodes Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US520245A US3357871A (en) | 1966-01-12 | 1966-01-12 | Method for fabricating integrated circuits |
| US522278A US3419956A (en) | 1966-01-12 | 1966-01-21 | Technique for obtaining isolated integrated circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CH451325A true CH451325A (de) | 1968-05-15 |
Family
ID=27060085
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CH38167A CH451325A (de) | 1966-01-12 | 1967-01-01 | Verfahren zum Herstellen integrierter Schaltungen mit durch eingebettete Trennfugen aus dielektrischem Material gegenseitig elektrisch isolierten Schaltelementen |
| CH88067A CH451326A (de) | 1966-01-12 | 1967-01-20 | Verfahren zum gegenseitigen elektrischen Isolieren verschiedener in einer integrierten oder monolithischen Halbleitervorrichtung zusammengefasster Schaltelemente |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CH88067A CH451326A (de) | 1966-01-12 | 1967-01-20 | Verfahren zum gegenseitigen elektrischen Isolieren verschiedener in einer integrierten oder monolithischen Halbleitervorrichtung zusammengefasster Schaltelemente |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US3357871A (de) |
| BE (2) | BE691802A (de) |
| CH (2) | CH451325A (de) |
| DE (2) | DE1589918B2 (de) |
| FR (2) | FR1509408A (de) |
| GB (2) | GB1137577A (de) |
| NL (2) | NL154062B (de) |
| SE (1) | SE326504B (de) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5696402A (en) * | 1965-09-28 | 1997-12-09 | Li; Chou H. | Integrated circuit device |
| US3440498A (en) * | 1966-03-14 | 1969-04-22 | Nat Semiconductor Corp | Contacts for insulation isolated semiconductor integrated circuitry |
| US3471922A (en) * | 1966-06-02 | 1969-10-14 | Raytheon Co | Monolithic integrated circuitry with dielectric isolated functional regions |
| US3575740A (en) * | 1967-06-08 | 1971-04-20 | Ibm | Method of fabricating planar dielectric isolated integrated circuits |
| US3460007A (en) * | 1967-07-03 | 1969-08-05 | Rca Corp | Semiconductor junction device |
| US3753803A (en) * | 1968-12-06 | 1973-08-21 | Hitachi Ltd | Method of dividing semiconductor layer into a plurality of isolated regions |
| US3844858A (en) * | 1968-12-31 | 1974-10-29 | Texas Instruments Inc | Process for controlling the thickness of a thin layer of semiconductor material and semiconductor substrate |
| US3755012A (en) * | 1971-03-19 | 1973-08-28 | Motorola Inc | Controlled anisotropic etching process for fabricating dielectrically isolated field effect transistor |
| US3969749A (en) * | 1974-04-01 | 1976-07-13 | Texas Instruments Incorporated | Substrate for dielectric isolated integrated circuit with V-etched depth grooves for lapping guide |
| US3928094A (en) * | 1975-01-16 | 1975-12-23 | Fairchild Camera Instr Co | Method of aligning a wafer beneath a mask and system therefor and wafer having a unique alignment pattern |
| JPS5351970A (en) * | 1976-10-21 | 1978-05-11 | Toshiba Corp | Manufacture for semiconductor substrate |
| US4502913A (en) * | 1982-06-30 | 1985-03-05 | International Business Machines Corporation | Total dielectric isolation for integrated circuits |
| AU2003234403A1 (en) * | 2002-05-16 | 2003-12-02 | Nova Research, Inc. | Methods of fabricating magnetoresistive memory devices |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2967344A (en) * | 1958-02-14 | 1961-01-10 | Rca Corp | Semiconductor devices |
| FR1217793A (fr) * | 1958-12-09 | 1960-05-05 | Perfectionnements à la fabrication des éléments semi-conducteurs | |
| NL252131A (de) * | 1959-06-30 | |||
| US3179543A (en) * | 1961-03-30 | 1965-04-20 | Philips Corp | Method of manufacturing plates having funnel-shaped cavities or perforations obtained by etching |
| GB967002A (en) * | 1961-05-05 | 1964-08-19 | Standard Telephones Cables Ltd | Improvements in or relating to semiconductor devices |
| US3290753A (en) * | 1963-08-19 | 1966-12-13 | Bell Telephone Labor Inc | Method of making semiconductor integrated circuit elements |
-
1966
- 1966-01-12 US US520245A patent/US3357871A/en not_active Expired - Lifetime
- 1966-01-16 FR FR8304A patent/FR1509408A/fr not_active Expired
- 1966-01-21 US US522278A patent/US3419956A/en not_active Expired - Lifetime
- 1966-11-29 GB GB53268/66A patent/GB1137577A/en not_active Expired
- 1966-12-21 GB GB54901/66A patent/GB1096484A/en not_active Expired
- 1966-12-27 BE BE691802D patent/BE691802A/xx unknown
-
1967
- 1967-01-01 CH CH38167A patent/CH451325A/de unknown
- 1967-01-05 FR FR8271A patent/FR1507802A/fr not_active Expired
- 1967-01-06 NL NL676700219A patent/NL154062B/xx not_active IP Right Cessation
- 1967-01-12 DE DE19671589918 patent/DE1589918B2/de not_active Withdrawn
- 1967-01-17 DE DE19671589920 patent/DE1589920B2/de not_active Withdrawn
- 1967-01-19 BE BE692869D patent/BE692869A/xx unknown
- 1967-01-20 SE SE00880/67A patent/SE326504B/xx unknown
- 1967-01-20 CH CH88067A patent/CH451326A/de unknown
- 1967-01-20 NL NL676700993A patent/NL154060B/xx not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US3419956A (en) | 1969-01-07 |
| NL6700993A (de) | 1967-07-24 |
| GB1137577A (en) | 1968-12-27 |
| GB1096484A (en) | 1967-12-29 |
| US3357871A (en) | 1967-12-12 |
| DE1589918B2 (de) | 1971-01-14 |
| BE691802A (de) | 1967-05-29 |
| BE692869A (de) | 1967-07-03 |
| SE326504B (de) | 1970-07-27 |
| DE1589920B2 (de) | 1971-02-18 |
| DE1589918A1 (de) | 1970-06-04 |
| FR1507802A (fr) | 1967-12-29 |
| DE1589920A1 (de) | 1970-09-17 |
| CH451326A (de) | 1968-05-15 |
| NL6700219A (de) | 1967-07-13 |
| FR1509408A (fr) | 1968-01-12 |
| NL154060B (nl) | 1977-07-15 |
| NL154062B (nl) | 1977-07-15 |
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